Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org> |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Rob Clark <robclark@freedesktop.org> |
| 25 | */ |
| 26 | |
| 27 | #include "pipe/p_state.h" |
| 28 | #include "util/u_string.h" |
| 29 | #include "util/u_memory.h" |
| 30 | #include "util/u_inlines.h" |
| 31 | #include "util/u_format.h" |
| 32 | |
| 33 | #include "freedreno_draw.h" |
| 34 | #include "freedreno_state.h" |
| 35 | #include "freedreno_resource.h" |
| 36 | |
| 37 | #include "fd5_gmem.h" |
| 38 | #include "fd5_context.h" |
| 39 | #include "fd5_draw.h" |
| 40 | #include "fd5_emit.h" |
| 41 | #include "fd5_program.h" |
| 42 | #include "fd5_format.h" |
| 43 | #include "fd5_zsa.h" |
| 44 | |
| 45 | static void |
| 46 | emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs, |
| 47 | struct pipe_surface **bufs, struct fd_gmem_stateobj *gmem) |
| 48 | { |
| 49 | enum a5xx_tile_mode tile_mode; |
| 50 | unsigned i; |
| 51 | |
| 52 | if (gmem) { |
| 53 | tile_mode = TILE5_2; |
| 54 | } else { |
| 55 | tile_mode = TILE5_LINEAR; |
| 56 | } |
| 57 | |
| 58 | for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) { |
| 59 | enum a5xx_color_fmt format = 0; |
| 60 | enum a3xx_color_swap swap = WZYX; |
Ilia Mirkin | a00727a | 2017-07-07 00:19:03 -0400 | [diff] [blame] | 61 | bool srgb = false, sint = false, uint = false; |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 62 | struct fd_resource *rsc = NULL; |
| 63 | struct fd_resource_slice *slice = NULL; |
| 64 | uint32_t stride = 0; |
| 65 | uint32_t size = 0; |
| 66 | uint32_t base = 0; |
| 67 | uint32_t offset = 0; |
| 68 | |
| 69 | if ((i < nr_bufs) && bufs[i]) { |
| 70 | struct pipe_surface *psurf = bufs[i]; |
| 71 | enum pipe_format pformat = psurf->format; |
| 72 | |
| 73 | rsc = fd_resource(psurf->texture); |
| 74 | |
| 75 | slice = fd_resource_slice(rsc, psurf->u.tex.level); |
| 76 | format = fd5_pipe2color(pformat); |
| 77 | swap = fd5_pipe2swap(pformat); |
| 78 | srgb = util_format_is_srgb(pformat); |
Ilia Mirkin | a00727a | 2017-07-07 00:19:03 -0400 | [diff] [blame] | 79 | sint = util_format_is_pure_sint(pformat); |
| 80 | uint = util_format_is_pure_uint(pformat); |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 81 | |
| 82 | debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer); |
| 83 | |
| 84 | offset = fd_resource_offset(rsc, psurf->u.tex.level, |
| 85 | psurf->u.tex.first_layer); |
| 86 | |
| 87 | if (gmem) { |
| 88 | stride = gmem->bin_w * rsc->cpp; |
| 89 | size = stride * gmem->bin_h; |
| 90 | base = gmem->cbuf_base[i]; |
| 91 | } else { |
| 92 | stride = slice->pitch * rsc->cpp; |
| 93 | size = slice->size0; |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5); |
| 98 | OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) | |
| 99 | A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) | |
| 100 | A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) | |
Rob Clark | 6f93c75 | 2016-12-09 18:23:10 -0500 | [diff] [blame] | 101 | COND(gmem, 0x800) | /* XXX 0x1000 for RECTLIST clear, 0x0 for BLIT.. */ |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 102 | COND(srgb, A5XX_RB_MRT_BUF_INFO_COLOR_SRGB)); |
| 103 | OUT_RING(ring, A5XX_RB_MRT_PITCH(stride)); |
| 104 | OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(size)); |
| 105 | if (gmem || (i >= nr_bufs) || !bufs[i]) { |
| 106 | OUT_RING(ring, base); /* RB_MRT[i].BASE_LO */ |
| 107 | OUT_RING(ring, 0x00000000); /* RB_MRT[i].BASE_HI */ |
| 108 | } else { |
Rob Clark | c1e9cca | 2016-12-03 12:34:10 -0500 | [diff] [blame] | 109 | debug_assert((offset + size) <= fd_bo_size(rsc->bo)); |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 110 | OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */ |
| 111 | } |
| 112 | |
| 113 | OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1); |
Rob Clark | 141a4f8 | 2017-01-15 13:19:47 -0500 | [diff] [blame] | 114 | OUT_RING(ring, A5XX_SP_FS_MRT_REG_COLOR_FORMAT(format) | |
Ilia Mirkin | a00727a | 2017-07-07 00:19:03 -0400 | [diff] [blame] | 115 | COND(sint, A5XX_SP_FS_MRT_REG_COLOR_SINT) | |
| 116 | COND(uint, A5XX_SP_FS_MRT_REG_COLOR_UINT) | |
Rob Clark | 141a4f8 | 2017-01-15 13:19:47 -0500 | [diff] [blame] | 117 | COND(srgb, A5XX_SP_FS_MRT_REG_COLOR_SRGB)); |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 118 | |
| 119 | /* when we support UBWC, these would be the system memory |
| 120 | * addr/pitch/etc: |
| 121 | */ |
| 122 | OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4); |
| 123 | OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */ |
| 124 | OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */ |
| 125 | OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_PITCH(0)); |
| 126 | OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0)); |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | static void |
| 131 | emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf, |
| 132 | struct fd_gmem_stateobj *gmem) |
| 133 | { |
| 134 | if (zsbuf) { |
| 135 | struct fd_resource *rsc = fd_resource(zsbuf->texture); |
| 136 | enum a5xx_depth_format fmt = fd5_pipe2depth(zsbuf->format); |
| 137 | uint32_t cpp = rsc->cpp; |
| 138 | uint32_t stride = 0; |
| 139 | uint32_t size = 0; |
| 140 | |
| 141 | if (gmem) { |
| 142 | stride = cpp * gmem->bin_w; |
| 143 | size = stride * gmem->bin_h; |
| 144 | } else { |
| 145 | struct fd_resource_slice *slice = fd_resource_slice(rsc, 0); |
| 146 | stride = slice->pitch * rsc->cpp; |
| 147 | size = slice->size0; |
| 148 | } |
| 149 | |
| 150 | OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5); |
| 151 | OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt)); |
| 152 | if (gmem) { |
| 153 | OUT_RING(ring, gmem->zsbuf_base[0]); /* RB_DEPTH_BUFFER_BASE_LO */ |
| 154 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */ |
| 155 | } else { |
| 156 | OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */ |
| 157 | } |
| 158 | OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_PITCH(stride)); |
| 159 | OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size)); |
| 160 | |
| 161 | OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1); |
| 162 | OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt)); |
| 163 | |
| 164 | OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3); |
| 165 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */ |
| 166 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */ |
| 167 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */ |
| 168 | |
Rob Clark | 5b60004 | 2017-06-03 13:36:25 -0400 | [diff] [blame] | 169 | if (rsc->lrz) { |
| 170 | OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3); |
| 171 | OUT_RELOCW(ring, rsc->lrz, 0x1000, 0, 0); |
| 172 | OUT_RING(ring, A5XX_GRAS_LRZ_BUFFER_PITCH(rsc->lrz_pitch)); |
| 173 | |
| 174 | OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2); |
| 175 | OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); |
| 176 | } else { |
| 177 | OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3); |
| 178 | OUT_RING(ring, 0x00000000); |
| 179 | OUT_RING(ring, 0x00000000); |
| 180 | OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */ |
| 181 | |
| 182 | OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2); |
| 183 | OUT_RING(ring, 0x00000000); |
| 184 | OUT_RING(ring, 0x00000000); |
| 185 | } |
| 186 | |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 187 | if (rsc->stencil) { |
| 188 | if (gmem) { |
| 189 | stride = 1 * gmem->bin_w; |
| 190 | size = stride * gmem->bin_h; |
| 191 | } else { |
| 192 | struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0); |
| 193 | stride = slice->pitch * rsc->cpp; |
| 194 | size = slice->size0; |
| 195 | } |
| 196 | |
| 197 | OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 5); |
| 198 | OUT_RING(ring, A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL); |
| 199 | if (gmem) { |
| 200 | OUT_RING(ring, gmem->zsbuf_base[1]); /* RB_STENCIL_BASE_LO */ |
| 201 | OUT_RING(ring, 0x00000000); /* RB_STENCIL_BASE_HI */ |
| 202 | } else { |
| 203 | OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */ |
| 204 | } |
| 205 | OUT_RING(ring, A5XX_RB_STENCIL_PITCH(stride)); |
| 206 | OUT_RING(ring, A5XX_RB_STENCIL_ARRAY_PITCH(size)); |
| 207 | } else { |
| 208 | OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1); |
| 209 | OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */ |
| 210 | } |
| 211 | } else { |
| 212 | OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5); |
| 213 | OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE)); |
| 214 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */ |
| 215 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */ |
| 216 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */ |
| 217 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */ |
| 218 | |
| 219 | OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1); |
| 220 | OUT_RING(ring, A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH5_NONE)); |
| 221 | |
| 222 | OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3); |
| 223 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */ |
| 224 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */ |
| 225 | OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */ |
| 226 | |
| 227 | OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1); |
| 228 | OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */ |
| 229 | } |
| 230 | } |
| 231 | |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 232 | static bool |
| 233 | use_hw_binning(struct fd_batch *batch) |
| 234 | { |
| 235 | struct fd_gmem_stateobj *gmem = &batch->ctx->gmem; |
| 236 | |
Rob Clark | dafc2f1 | 2017-05-16 08:37:50 -0400 | [diff] [blame] | 237 | if ((gmem->maxpw * gmem->maxph) > 32) |
| 238 | return false; |
| 239 | |
| 240 | if ((gmem->maxpw > 15) || (gmem->maxph > 15)) |
| 241 | return false; |
| 242 | |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 243 | return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) && |
| 244 | (batch->num_draws > 0); |
| 245 | } |
| 246 | |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 247 | static void |
| 248 | patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode) |
| 249 | { |
| 250 | unsigned i; |
| 251 | for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) { |
| 252 | struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i); |
| 253 | *patch->cs = patch->val | DRAW4(0, 0, 0, vismode); |
| 254 | } |
| 255 | util_dynarray_resize(&batch->draw_patches, 0); |
| 256 | } |
| 257 | |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 258 | static void |
| 259 | update_vsc_pipe(struct fd_batch *batch) |
| 260 | { |
| 261 | struct fd_context *ctx = batch->ctx; |
| 262 | struct fd5_context *fd5_ctx = fd5_context(ctx); |
| 263 | struct fd_gmem_stateobj *gmem = &batch->ctx->gmem; |
| 264 | struct fd_ringbuffer *ring = batch->gmem; |
| 265 | int i; |
| 266 | |
| 267 | OUT_PKT4(ring, REG_A5XX_VSC_BIN_SIZE, 3); |
| 268 | OUT_RING(ring, A5XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) | |
| 269 | A5XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h)); |
| 270 | OUT_RELOCW(ring, fd5_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */ |
| 271 | |
| 272 | OUT_PKT4(ring, REG_A5XX_UNKNOWN_0BC5, 2); |
| 273 | OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC5 */ |
| 274 | OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC6 */ |
| 275 | |
| 276 | OUT_PKT4(ring, REG_A5XX_VSC_PIPE_CONFIG_REG(0), 16); |
| 277 | for (i = 0; i < 16; i++) { |
Rob Clark | 9c32333 | 2017-08-24 09:30:25 -0400 | [diff] [blame] | 278 | struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i]; |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 279 | OUT_RING(ring, A5XX_VSC_PIPE_CONFIG_REG_X(pipe->x) | |
| 280 | A5XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) | |
| 281 | A5XX_VSC_PIPE_CONFIG_REG_W(pipe->w) | |
| 282 | A5XX_VSC_PIPE_CONFIG_REG_H(pipe->h)); |
| 283 | } |
| 284 | |
| 285 | OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(0), 32); |
| 286 | for (i = 0; i < 16; i++) { |
Rob Clark | 9c32333 | 2017-08-24 09:30:25 -0400 | [diff] [blame] | 287 | struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i]; |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 288 | if (!pipe->bo) { |
| 289 | pipe->bo = fd_bo_new(ctx->dev, 0x20000, |
| 290 | DRM_FREEDRENO_GEM_TYPE_KMEM); |
| 291 | } |
| 292 | OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */ |
| 293 | } |
| 294 | |
| 295 | OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(0), 16); |
| 296 | for (i = 0; i < 16; i++) { |
Rob Clark | 9c32333 | 2017-08-24 09:30:25 -0400 | [diff] [blame] | 297 | struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i]; |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 298 | OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */ |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | static void |
| 303 | emit_binning_pass(struct fd_batch *batch) |
| 304 | { |
| 305 | struct fd_context *ctx = batch->ctx; |
| 306 | struct fd_ringbuffer *ring = batch->gmem; |
| 307 | struct fd_gmem_stateobj *gmem = &batch->ctx->gmem; |
| 308 | |
| 309 | uint32_t x1 = gmem->minx; |
| 310 | uint32_t y1 = gmem->miny; |
| 311 | uint32_t x2 = gmem->minx + gmem->width - 1; |
| 312 | uint32_t y2 = gmem->miny + gmem->height - 1; |
| 313 | |
| 314 | fd5_set_render_mode(batch->ctx, ring, BINNING); |
| 315 | |
| 316 | OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1); |
| 317 | OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) | |
| 318 | A5XX_RB_CNTL_HEIGHT(gmem->bin_h)); |
| 319 | |
| 320 | OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2); |
| 321 | OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) | |
| 322 | A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1)); |
| 323 | OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) | |
| 324 | A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2)); |
| 325 | |
| 326 | OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2); |
| 327 | OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) | |
| 328 | A5XX_RB_RESOLVE_CNTL_1_Y(y1)); |
| 329 | OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) | |
| 330 | A5XX_RB_RESOLVE_CNTL_2_Y(y2)); |
| 331 | |
| 332 | update_vsc_pipe(batch); |
| 333 | |
| 334 | OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1); |
| 335 | OUT_RING(ring, A5XX_VPC_MODE_CNTL_BINNING_PASS); |
| 336 | |
| 337 | OUT_PKT7(ring, CP_EVENT_WRITE, 1); |
| 338 | OUT_RING(ring, UNK_2C); |
| 339 | |
| 340 | OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1); |
| 341 | OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) | |
| 342 | A5XX_RB_WINDOW_OFFSET_Y(0)); |
| 343 | |
| 344 | /* emit IB to binning drawcmds: */ |
| 345 | ctx->emit_ib(ring, batch->binning); |
| 346 | |
| 347 | fd_reset_wfi(batch); |
| 348 | |
| 349 | OUT_PKT7(ring, CP_EVENT_WRITE, 1); |
| 350 | OUT_RING(ring, UNK_2D); |
| 351 | |
| 352 | OUT_PKT7(ring, CP_EVENT_WRITE, 4); |
| 353 | OUT_RING(ring, CACHE_FLUSH_TS); |
| 354 | OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */ |
| 355 | OUT_RING(ring, 0x00000000); |
| 356 | |
| 357 | // TODO CP_COND_WRITE's for all the vsc buffers (check for overflow??) |
| 358 | |
| 359 | fd_wfi(batch, ring); |
| 360 | |
| 361 | OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1); |
| 362 | OUT_RING(ring, 0x0); |
| 363 | } |
| 364 | |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 365 | /* before first tile */ |
| 366 | static void |
| 367 | fd5_emit_tile_init(struct fd_batch *batch) |
| 368 | { |
Rob Clark | 5b60004 | 2017-06-03 13:36:25 -0400 | [diff] [blame] | 369 | struct fd_context *ctx = batch->ctx; |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 370 | struct fd_ringbuffer *ring = batch->gmem; |
Rob Clark | 5b60004 | 2017-06-03 13:36:25 -0400 | [diff] [blame] | 371 | struct pipe_framebuffer_state *pfb = &batch->framebuffer; |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 372 | |
| 373 | fd5_emit_restore(batch, ring); |
| 374 | |
Rob Clark | 5b60004 | 2017-06-03 13:36:25 -0400 | [diff] [blame] | 375 | if (batch->lrz_clear) |
| 376 | ctx->emit_ib(ring, batch->lrz_clear); |
| 377 | |
Rob Clark | 5589ba9 | 2017-06-03 12:42:35 -0400 | [diff] [blame] | 378 | fd5_emit_lrz_flush(ring); |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 379 | |
Rob Clark | 5b60004 | 2017-06-03 13:36:25 -0400 | [diff] [blame] | 380 | OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1); |
| 381 | OUT_RING(ring, 0x00000080); /* GRAS_CL_CNTL */ |
| 382 | |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 383 | OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1); |
| 384 | OUT_RING(ring, 0x0); |
| 385 | |
| 386 | OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1); |
| 387 | OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */ |
| 388 | |
| 389 | OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1); |
| 390 | OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */ |
| 391 | |
| 392 | /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */ |
| 393 | fd_wfi(batch, ring); |
| 394 | OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1); |
| 395 | OUT_RING(ring, 0x7c13c080); /* RB_CCU_CNTL */ |
| 396 | |
Rob Clark | 5b60004 | 2017-06-03 13:36:25 -0400 | [diff] [blame] | 397 | emit_zs(ring, pfb->zsbuf, &ctx->gmem); |
| 398 | emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, &ctx->gmem); |
| 399 | |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 400 | if (use_hw_binning(batch)) { |
| 401 | emit_binning_pass(batch); |
Rob Clark | 5b60004 | 2017-06-03 13:36:25 -0400 | [diff] [blame] | 402 | fd5_emit_lrz_flush(ring); |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 403 | patch_draws(batch, USE_VISIBILITY); |
| 404 | } else { |
| 405 | patch_draws(batch, IGNORE_VISIBILITY); |
| 406 | } |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 407 | |
| 408 | fd5_set_render_mode(batch->ctx, ring, GMEM); |
| 409 | } |
| 410 | |
| 411 | /* before mem2gmem */ |
| 412 | static void |
| 413 | fd5_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile) |
| 414 | { |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 415 | struct fd_context *ctx = batch->ctx; |
| 416 | struct fd5_context *fd5_ctx = fd5_context(ctx); |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 417 | struct fd_ringbuffer *ring = batch->gmem; |
| 418 | |
| 419 | uint32_t x1 = tile->xoff; |
| 420 | uint32_t y1 = tile->yoff; |
| 421 | uint32_t x2 = tile->xoff + tile->bin_w - 1; |
| 422 | uint32_t y2 = tile->yoff + tile->bin_h - 1; |
| 423 | |
| 424 | OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2); |
| 425 | OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) | |
| 426 | A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1)); |
| 427 | OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) | |
| 428 | A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2)); |
| 429 | |
| 430 | OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2); |
| 431 | OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(x1) | |
| 432 | A5XX_RB_RESOLVE_CNTL_1_Y(y1)); |
| 433 | OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(x2) | |
| 434 | A5XX_RB_RESOLVE_CNTL_2_Y(y2)); |
| 435 | |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 436 | if (use_hw_binning(batch)) { |
Rob Clark | 9c32333 | 2017-08-24 09:30:25 -0400 | [diff] [blame] | 437 | struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p]; |
Rob Clark | 8efaae3 | 2017-05-12 09:56:56 -0400 | [diff] [blame] | 438 | |
| 439 | OUT_PKT7(ring, CP_WAIT_FOR_ME, 0); |
| 440 | |
| 441 | OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1); |
| 442 | OUT_RING(ring, 0x0); |
| 443 | |
| 444 | OUT_PKT7(ring, CP_SET_BIN_DATA5, 5); |
| 445 | OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) | |
| 446 | CP_SET_BIN_DATA5_0_VSC_N(tile->n)); |
| 447 | OUT_RELOC(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[p].DATA_ADDRESS */ |
| 448 | OUT_RELOC(ring, fd5_ctx->vsc_size_mem, /* VSC_SIZE_ADDRESS + (p * 4) */ |
| 449 | (tile->p * 4), 0, 0); |
| 450 | } else { |
| 451 | OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1); |
| 452 | OUT_RING(ring, 0x1); |
| 453 | } |
| 454 | |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 455 | OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1); |
| 456 | OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(x1) | |
| 457 | A5XX_RB_WINDOW_OFFSET_Y(y1)); |
| 458 | } |
| 459 | |
| 460 | |
| 461 | /* |
| 462 | * transfer from system memory to gmem |
| 463 | */ |
| 464 | |
| 465 | static void |
| 466 | emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base, |
| 467 | struct pipe_surface *psurf, enum a5xx_blit_buf buf) |
| 468 | { |
| 469 | struct fd_ringbuffer *ring = batch->gmem; |
Rob Clark | 5e632b3 | 2016-12-07 10:17:17 -0500 | [diff] [blame] | 470 | struct fd_gmem_stateobj *gmem = &batch->ctx->gmem; |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 471 | struct fd_resource *rsc = fd_resource(psurf->texture); |
Rob Clark | 5e632b3 | 2016-12-07 10:17:17 -0500 | [diff] [blame] | 472 | uint32_t stride, size; |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 473 | |
| 474 | debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer); |
| 475 | |
Rob Clark | 010ebed | 2017-11-17 11:12:45 -0500 | [diff] [blame^] | 476 | if (buf == BLIT_ZS) { |
| 477 | // XXX hack import via BLIT_MRT0 instead of BLIT_ZS, since I don't |
| 478 | // know otherwise how to go from linear in sysmem to tiled in gmem. |
| 479 | // possibly we want to flip this around gmem2mem and keep depth |
| 480 | // tiled in sysmem (and fixup sampler state to assume tiled).. this |
| 481 | // might be required for doing depth/stencil in bypass mode? |
| 482 | struct fd_resource_slice *slice = fd_resource_slice(rsc, 0); |
| 483 | enum a5xx_color_fmt format = |
| 484 | fd5_pipe2color(fd_gmem_restore_format(rsc->base.b.format)); |
| 485 | |
| 486 | OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5); |
| 487 | OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) | |
| 488 | A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) | |
| 489 | A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX)); |
| 490 | OUT_RING(ring, A5XX_RB_MRT_PITCH(slice->pitch * rsc->cpp)); |
| 491 | OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(slice->size0)); |
| 492 | OUT_RELOC(ring, rsc->bo, 0, 0, 0); /* BASE_LO/HI */ |
| 493 | |
| 494 | buf = BLIT_MRT0; |
| 495 | } |
| 496 | |
Rob Clark | 5e632b3 | 2016-12-07 10:17:17 -0500 | [diff] [blame] | 497 | stride = gmem->bin_w * rsc->cpp; |
| 498 | size = stride * gmem->bin_h; |
| 499 | |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 500 | OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4); |
| 501 | OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */ |
| 502 | OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */ |
| 503 | OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */ |
| 504 | OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */ |
| 505 | |
| 506 | OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5); |
| 507 | OUT_RING(ring, 0x00000000); /* RB_RESOLVE_CNTL_3 */ |
| 508 | OUT_RING(ring, base); /* RB_BLIT_DST_LO */ |
| 509 | OUT_RING(ring, 0x00000000); /* RB_BLIT_DST_HI */ |
Rob Clark | 5e632b3 | 2016-12-07 10:17:17 -0500 | [diff] [blame] | 510 | OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(stride)); |
| 511 | OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(size)); |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 512 | |
| 513 | OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1); |
| 514 | OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf)); |
| 515 | |
| 516 | fd5_emit_blit(batch->ctx, ring); |
| 517 | } |
| 518 | |
| 519 | static void |
| 520 | fd5_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile) |
| 521 | { |
| 522 | struct fd_ringbuffer *ring = batch->gmem; |
| 523 | struct fd_context *ctx = batch->ctx; |
| 524 | struct fd_gmem_stateobj *gmem = &ctx->gmem; |
| 525 | struct pipe_framebuffer_state *pfb = &batch->framebuffer; |
| 526 | |
| 527 | /* |
| 528 | * setup mrt and zs with system memory base addresses: |
| 529 | */ |
| 530 | |
| 531 | emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL); |
Rob Clark | 939486d | 2016-12-12 16:06:55 -0500 | [diff] [blame] | 532 | // emit_zs(ring, pfb->zsbuf, NULL); |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 533 | |
| 534 | OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1); |
| 535 | OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) | |
| 536 | A5XX_RB_CNTL_HEIGHT(gmem->bin_h) | |
| 537 | A5XX_RB_CNTL_BYPASS); |
| 538 | |
| 539 | if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) { |
| 540 | unsigned i; |
| 541 | for (i = 0; i < pfb->nr_cbufs; i++) { |
| 542 | if (!pfb->cbufs[i]) |
| 543 | continue; |
| 544 | if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i))) |
| 545 | continue; |
| 546 | emit_mem2gmem_surf(batch, gmem->cbuf_base[i], |
| 547 | pfb->cbufs[i], BLIT_MRT0 + i); |
| 548 | } |
| 549 | } |
| 550 | |
| 551 | if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) { |
| 552 | struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture); |
Rob Clark | 939486d | 2016-12-12 16:06:55 -0500 | [diff] [blame] | 553 | |
Rob Clark | 010ebed | 2017-11-17 11:12:45 -0500 | [diff] [blame^] | 554 | emit_mem2gmem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf, BLIT_ZS); |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 555 | } |
| 556 | } |
| 557 | |
| 558 | |
| 559 | /* before IB to rendering cmds: */ |
| 560 | static void |
| 561 | fd5_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile) |
| 562 | { |
| 563 | struct fd_ringbuffer *ring = batch->gmem; |
| 564 | struct fd_gmem_stateobj *gmem = &batch->ctx->gmem; |
| 565 | struct pipe_framebuffer_state *pfb = &batch->framebuffer; |
| 566 | |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 567 | OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1); |
| 568 | OUT_RING(ring, A5XX_RB_CNTL_WIDTH(gmem->bin_w) | |
| 569 | A5XX_RB_CNTL_HEIGHT(gmem->bin_h)); |
| 570 | |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 571 | emit_zs(ring, pfb->zsbuf, gmem); |
| 572 | emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem); |
| 573 | |
| 574 | // TODO MSAA |
| 575 | OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2); |
| 576 | OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE)); |
| 577 | OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) | |
| 578 | A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE); |
| 579 | |
| 580 | OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2); |
| 581 | OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE)); |
| 582 | OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) | |
| 583 | A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE); |
| 584 | |
| 585 | OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2); |
| 586 | OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE)); |
| 587 | OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) | |
| 588 | A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE); |
| 589 | } |
| 590 | |
| 591 | |
| 592 | /* |
| 593 | * transfer from gmem to system memory (ie. normal RAM) |
| 594 | */ |
| 595 | |
| 596 | static void |
| 597 | emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base, |
| 598 | struct pipe_surface *psurf, enum a5xx_blit_buf buf) |
| 599 | { |
| 600 | struct fd_ringbuffer *ring = batch->gmem; |
| 601 | struct fd_resource *rsc = fd_resource(psurf->texture); |
| 602 | struct fd_resource_slice *slice; |
| 603 | uint32_t offset; |
| 604 | |
| 605 | slice = fd_resource_slice(rsc, psurf->u.tex.level); |
| 606 | offset = fd_resource_offset(rsc, psurf->u.tex.level, |
| 607 | psurf->u.tex.first_layer); |
| 608 | |
| 609 | debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer); |
| 610 | |
| 611 | OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4); |
| 612 | OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_LO */ |
| 613 | OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_HI */ |
| 614 | OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_PITCH */ |
| 615 | OUT_RING(ring, 0x00000000); /* RB_BLIT_FLAG_DST_ARRAY_PITCH */ |
| 616 | |
| 617 | OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5); |
| 618 | OUT_RING(ring, 0x00000004); /* XXX RB_RESOLVE_CNTL_3 */ |
| 619 | OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */ |
| 620 | OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch * rsc->cpp)); |
| 621 | OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice->size0)); |
| 622 | |
| 623 | OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1); |
| 624 | OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf)); |
| 625 | |
| 626 | fd5_emit_blit(batch->ctx, ring); |
| 627 | } |
| 628 | |
| 629 | static void |
| 630 | fd5_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile) |
| 631 | { |
| 632 | struct fd_context *ctx = batch->ctx; |
| 633 | struct fd_gmem_stateobj *gmem = &ctx->gmem; |
| 634 | struct pipe_framebuffer_state *pfb = &batch->framebuffer; |
| 635 | |
| 636 | if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) { |
| 637 | struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture); |
| 638 | // XXX BLIT_ZS vs BLIT_Z32 .. need some more cmdstream traces |
| 639 | // with z32_x24s8.. |
| 640 | if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) |
| 641 | emit_gmem2mem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf, BLIT_ZS); |
| 642 | if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) |
| 643 | emit_gmem2mem_surf(batch, gmem->zsbuf_base[1], pfb->zsbuf, BLIT_ZS); |
| 644 | } |
| 645 | |
| 646 | if (batch->resolve & FD_BUFFER_COLOR) { |
| 647 | unsigned i; |
| 648 | for (i = 0; i < pfb->nr_cbufs; i++) { |
| 649 | if (!pfb->cbufs[i]) |
| 650 | continue; |
| 651 | if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i))) |
| 652 | continue; |
| 653 | emit_gmem2mem_surf(batch, gmem->cbuf_base[i], |
| 654 | pfb->cbufs[i], BLIT_MRT0 + i); |
| 655 | } |
| 656 | } |
| 657 | } |
| 658 | |
| 659 | static void |
| 660 | fd5_emit_tile_fini(struct fd_batch *batch) |
| 661 | { |
Rob Clark | 6f93c75 | 2016-12-09 18:23:10 -0500 | [diff] [blame] | 662 | struct fd_ringbuffer *ring = batch->gmem; |
| 663 | |
| 664 | OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1); |
| 665 | OUT_RING(ring, 0x0); |
| 666 | |
Rob Clark | 5589ba9 | 2017-06-03 12:42:35 -0400 | [diff] [blame] | 667 | fd5_emit_lrz_flush(ring); |
Rob Clark | 6f93c75 | 2016-12-09 18:23:10 -0500 | [diff] [blame] | 668 | |
| 669 | fd5_cache_flush(batch, ring); |
| 670 | fd5_set_render_mode(batch->ctx, ring, BYPASS); |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 671 | } |
| 672 | |
Rob Clark | ec24f00 | 2016-12-06 14:21:22 -0500 | [diff] [blame] | 673 | static void |
| 674 | fd5_emit_sysmem_prep(struct fd_batch *batch) |
| 675 | { |
| 676 | struct pipe_framebuffer_state *pfb = &batch->framebuffer; |
| 677 | struct fd_ringbuffer *ring = batch->gmem; |
| 678 | |
| 679 | fd5_emit_restore(batch, ring); |
| 680 | |
Rob Clark | 5589ba9 | 2017-06-03 12:42:35 -0400 | [diff] [blame] | 681 | fd5_emit_lrz_flush(ring); |
Rob Clark | ec24f00 | 2016-12-06 14:21:22 -0500 | [diff] [blame] | 682 | |
| 683 | OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1); |
| 684 | OUT_RING(ring, 0x0); |
| 685 | |
Rob Clark | abcf8f5 | 2016-12-07 15:21:56 -0500 | [diff] [blame] | 686 | OUT_PKT7(ring, CP_EVENT_WRITE, 1); |
| 687 | OUT_RING(ring, UNK_19); |
| 688 | |
Rob Clark | ec24f00 | 2016-12-06 14:21:22 -0500 | [diff] [blame] | 689 | OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1); |
| 690 | OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */ |
| 691 | |
| 692 | OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1); |
| 693 | OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */ |
| 694 | |
| 695 | /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */ |
| 696 | fd_wfi(batch, ring); |
| 697 | OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1); |
| 698 | OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */ |
| 699 | |
| 700 | OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2); |
| 701 | OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) | |
| 702 | A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0)); |
| 703 | OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) | |
| 704 | A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1)); |
| 705 | |
| 706 | OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2); |
| 707 | OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) | |
| 708 | A5XX_RB_RESOLVE_CNTL_1_Y(0)); |
| 709 | OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(pfb->width - 1) | |
| 710 | A5XX_RB_RESOLVE_CNTL_2_Y(pfb->height - 1)); |
| 711 | |
| 712 | OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1); |
| 713 | OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) | |
| 714 | A5XX_RB_WINDOW_OFFSET_Y(0)); |
| 715 | |
| 716 | OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1); |
| 717 | OUT_RING(ring, 0x1); |
| 718 | |
| 719 | OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1); |
| 720 | OUT_RING(ring, A5XX_RB_CNTL_WIDTH(0) | |
| 721 | A5XX_RB_CNTL_HEIGHT(0) | |
| 722 | A5XX_RB_CNTL_BYPASS); |
| 723 | |
| 724 | patch_draws(batch, IGNORE_VISIBILITY); |
| 725 | |
| 726 | emit_zs(ring, pfb->zsbuf, NULL); |
| 727 | emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL); |
| 728 | |
| 729 | // TODO MSAA |
| 730 | OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2); |
| 731 | OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE)); |
| 732 | OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) | |
| 733 | A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE); |
| 734 | |
| 735 | OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2); |
| 736 | OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE)); |
| 737 | OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) | |
| 738 | A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE); |
| 739 | |
| 740 | OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2); |
| 741 | OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE)); |
| 742 | OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) | |
| 743 | A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE); |
| 744 | } |
| 745 | |
Rob Clark | 6f93c75 | 2016-12-09 18:23:10 -0500 | [diff] [blame] | 746 | static void |
| 747 | fd5_emit_sysmem_fini(struct fd_batch *batch) |
| 748 | { |
| 749 | struct fd5_context *fd5_ctx = fd5_context(batch->ctx); |
| 750 | struct fd_ringbuffer *ring = batch->gmem; |
| 751 | |
| 752 | OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1); |
| 753 | OUT_RING(ring, 0x0); |
| 754 | |
Rob Clark | 5589ba9 | 2017-06-03 12:42:35 -0400 | [diff] [blame] | 755 | fd5_emit_lrz_flush(ring); |
Rob Clark | 6f93c75 | 2016-12-09 18:23:10 -0500 | [diff] [blame] | 756 | |
| 757 | OUT_PKT7(ring, CP_EVENT_WRITE, 4); |
| 758 | OUT_RING(ring, UNK_1D); |
| 759 | OUT_RELOCW(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */ |
| 760 | OUT_RING(ring, 0x00000000); |
| 761 | } |
| 762 | |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 763 | void |
| 764 | fd5_gmem_init(struct pipe_context *pctx) |
| 765 | { |
| 766 | struct fd_context *ctx = fd_context(pctx); |
| 767 | |
| 768 | ctx->emit_tile_init = fd5_emit_tile_init; |
| 769 | ctx->emit_tile_prep = fd5_emit_tile_prep; |
| 770 | ctx->emit_tile_mem2gmem = fd5_emit_tile_mem2gmem; |
| 771 | ctx->emit_tile_renderprep = fd5_emit_tile_renderprep; |
| 772 | ctx->emit_tile_gmem2mem = fd5_emit_tile_gmem2mem; |
| 773 | ctx->emit_tile_fini = fd5_emit_tile_fini; |
Rob Clark | ec24f00 | 2016-12-06 14:21:22 -0500 | [diff] [blame] | 774 | ctx->emit_sysmem_prep = fd5_emit_sysmem_prep; |
Rob Clark | 6f93c75 | 2016-12-09 18:23:10 -0500 | [diff] [blame] | 775 | ctx->emit_sysmem_fini = fd5_emit_sysmem_fini; |
Rob Clark | 946cf4e | 2016-11-08 10:50:03 -0500 | [diff] [blame] | 776 | } |