Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Alyssa Rosenzweig |
| 3 | * Copyright (C) 2020 Collabora Ltd. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | |
Boris Brezillon | 0d75eb0 | 2020-03-06 09:59:56 +0100 | [diff] [blame] | 25 | #include "util/macros.h" |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 26 | #include "util/u_prim.h" |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 27 | #include "util/u_vbuf.h" |
Boris Brezillon | 0d75eb0 | 2020-03-06 09:59:56 +0100 | [diff] [blame] | 28 | |
| 29 | #include "panfrost-quirks.h" |
| 30 | |
Alyssa Rosenzweig | c8d848b | 2020-07-07 16:24:41 -0400 | [diff] [blame] | 31 | #include "pan_pool.h" |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 32 | #include "pan_bo.h" |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 33 | #include "pan_cmdstream.h" |
| 34 | #include "pan_context.h" |
| 35 | #include "pan_job.h" |
| 36 | |
Alyssa Rosenzweig | 02a638c | 2020-03-23 19:10:06 -0400 | [diff] [blame] | 37 | /* If a BO is accessed for a particular shader stage, will it be in the primary |
| 38 | * batch (vertex/tiler) or the secondary batch (fragment)? Anything but |
| 39 | * fragment will be primary, e.g. compute jobs will be considered |
| 40 | * "vertex/tiler" by analogy */ |
| 41 | |
| 42 | static inline uint32_t |
| 43 | panfrost_bo_access_for_stage(enum pipe_shader_type stage) |
| 44 | { |
| 45 | assert(stage == PIPE_SHADER_FRAGMENT || |
| 46 | stage == PIPE_SHADER_VERTEX || |
| 47 | stage == PIPE_SHADER_COMPUTE); |
| 48 | |
| 49 | return stage == PIPE_SHADER_FRAGMENT ? |
| 50 | PAN_BO_ACCESS_FRAGMENT : |
| 51 | PAN_BO_ACCESS_VERTEX_TILER; |
| 52 | } |
| 53 | |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 54 | static void |
| 55 | panfrost_vt_emit_shared_memory(struct panfrost_context *ctx, |
| 56 | struct mali_vertex_tiler_postfix *postfix) |
| 57 | { |
| 58 | struct panfrost_device *dev = pan_device(ctx->base.screen); |
| 59 | struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); |
| 60 | |
| 61 | unsigned shift = panfrost_get_stack_shift(batch->stack_size); |
| 62 | struct mali_shared_memory shared = { |
| 63 | .stack_shift = shift, |
| 64 | .scratchpad = panfrost_batch_get_scratchpad(batch, shift, dev->thread_tls_alloc, dev->core_count)->gpu, |
| 65 | .shared_workgroup_count = ~0, |
| 66 | }; |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 67 | postfix->shared_memory = panfrost_pool_upload(&batch->pool, &shared, sizeof(shared)); |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 68 | } |
Boris Brezillon | 0d75eb0 | 2020-03-06 09:59:56 +0100 | [diff] [blame] | 69 | |
Alyssa Rosenzweig | aee68b0 | 2020-04-06 20:14:23 -0400 | [diff] [blame] | 70 | static void |
Boris Brezillon | 0d75eb0 | 2020-03-06 09:59:56 +0100 | [diff] [blame] | 71 | panfrost_vt_attach_framebuffer(struct panfrost_context *ctx, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 72 | struct mali_vertex_tiler_postfix *postfix) |
Boris Brezillon | 0d75eb0 | 2020-03-06 09:59:56 +0100 | [diff] [blame] | 73 | { |
Boris Brezillon | 0d75eb0 | 2020-03-06 09:59:56 +0100 | [diff] [blame] | 74 | struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); |
Alyssa Rosenzweig | 34a0310 | 2020-07-15 13:10:02 -0400 | [diff] [blame] | 75 | postfix->shared_memory = panfrost_batch_reserve_framebuffer(batch); |
Boris Brezillon | 0d75eb0 | 2020-03-06 09:59:56 +0100 | [diff] [blame] | 76 | } |
| 77 | |
Alyssa Rosenzweig | aee68b0 | 2020-04-06 20:14:23 -0400 | [diff] [blame] | 78 | static void |
Boris Brezillon | e94076f | 2020-03-05 11:52:12 +0100 | [diff] [blame] | 79 | panfrost_vt_update_rasterizer(struct panfrost_context *ctx, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 80 | struct mali_vertex_tiler_prefix *prefix, |
| 81 | struct mali_vertex_tiler_postfix *postfix) |
Boris Brezillon | e94076f | 2020-03-05 11:52:12 +0100 | [diff] [blame] | 82 | { |
| 83 | struct panfrost_rasterizer *rasterizer = ctx->rasterizer; |
| 84 | |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 85 | postfix->gl_enables |= 0x7; |
| 86 | SET_BIT(postfix->gl_enables, MALI_FRONT_CCW_TOP, |
Boris Brezillon | e94076f | 2020-03-05 11:52:12 +0100 | [diff] [blame] | 87 | rasterizer && rasterizer->base.front_ccw); |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 88 | SET_BIT(postfix->gl_enables, MALI_CULL_FACE_FRONT, |
Boris Brezillon | e94076f | 2020-03-05 11:52:12 +0100 | [diff] [blame] | 89 | rasterizer && (rasterizer->base.cull_face & PIPE_FACE_FRONT)); |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 90 | SET_BIT(postfix->gl_enables, MALI_CULL_FACE_BACK, |
Boris Brezillon | e94076f | 2020-03-05 11:52:12 +0100 | [diff] [blame] | 91 | rasterizer && (rasterizer->base.cull_face & PIPE_FACE_BACK)); |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 92 | SET_BIT(prefix->unknown_draw, MALI_DRAW_FLATSHADE_FIRST, |
Boris Brezillon | e94076f | 2020-03-05 11:52:12 +0100 | [diff] [blame] | 93 | rasterizer && rasterizer->base.flatshade_first); |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 94 | } |
| 95 | |
| 96 | void |
| 97 | panfrost_vt_update_primitive_size(struct panfrost_context *ctx, |
| 98 | struct mali_vertex_tiler_prefix *prefix, |
| 99 | union midgard_primitive_size *primitive_size) |
| 100 | { |
| 101 | struct panfrost_rasterizer *rasterizer = ctx->rasterizer; |
Boris Brezillon | e94076f | 2020-03-05 11:52:12 +0100 | [diff] [blame] | 102 | |
| 103 | if (!panfrost_writes_point_size(ctx)) { |
Alyssa Rosenzweig | 32dbc80 | 2020-08-05 18:44:36 -0400 | [diff] [blame] | 104 | bool points = prefix->draw_mode == MALI_DRAW_MODE_POINTS; |
Boris Brezillon | e94076f | 2020-03-05 11:52:12 +0100 | [diff] [blame] | 105 | float val = 0.0f; |
| 106 | |
| 107 | if (rasterizer) |
| 108 | val = points ? |
| 109 | rasterizer->base.point_size : |
| 110 | rasterizer->base.line_width; |
| 111 | |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 112 | primitive_size->constant = val; |
Boris Brezillon | e94076f | 2020-03-05 11:52:12 +0100 | [diff] [blame] | 113 | } |
| 114 | } |
| 115 | |
Alyssa Rosenzweig | aee68b0 | 2020-04-06 20:14:23 -0400 | [diff] [blame] | 116 | static void |
Boris Brezillon | 56aeb92 | 2020-03-05 11:47:04 +0100 | [diff] [blame] | 117 | panfrost_vt_update_occlusion_query(struct panfrost_context *ctx, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 118 | struct mali_vertex_tiler_postfix *postfix) |
Boris Brezillon | 56aeb92 | 2020-03-05 11:47:04 +0100 | [diff] [blame] | 119 | { |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 120 | SET_BIT(postfix->gl_enables, MALI_OCCLUSION_QUERY, ctx->occlusion_query); |
Icecream95 | 3e3958c | 2020-06-28 20:48:36 +1200 | [diff] [blame] | 121 | if (ctx->occlusion_query) { |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 122 | postfix->occlusion_counter = ctx->occlusion_query->bo->gpu; |
Icecream95 | 3e3958c | 2020-06-28 20:48:36 +1200 | [diff] [blame] | 123 | panfrost_batch_add_bo(ctx->batch, ctx->occlusion_query->bo, |
| 124 | PAN_BO_ACCESS_SHARED | |
| 125 | PAN_BO_ACCESS_RW | |
| 126 | PAN_BO_ACCESS_FRAGMENT); |
| 127 | } else { |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 128 | postfix->occlusion_counter = 0; |
Icecream95 | 3e3958c | 2020-06-28 20:48:36 +1200 | [diff] [blame] | 129 | } |
Boris Brezillon | 56aeb92 | 2020-03-05 11:47:04 +0100 | [diff] [blame] | 130 | } |
| 131 | |
Boris Brezillon | d66ef69 | 2020-03-06 11:31:06 +0100 | [diff] [blame] | 132 | void |
| 133 | panfrost_vt_init(struct panfrost_context *ctx, |
| 134 | enum pipe_shader_type stage, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 135 | struct mali_vertex_tiler_prefix *prefix, |
| 136 | struct mali_vertex_tiler_postfix *postfix) |
Boris Brezillon | d66ef69 | 2020-03-06 11:31:06 +0100 | [diff] [blame] | 137 | { |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 138 | struct panfrost_device *device = pan_device(ctx->base.screen); |
| 139 | |
Boris Brezillon | d66ef69 | 2020-03-06 11:31:06 +0100 | [diff] [blame] | 140 | if (!ctx->shader[stage]) |
| 141 | return; |
| 142 | |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 143 | memset(prefix, 0, sizeof(*prefix)); |
| 144 | memset(postfix, 0, sizeof(*postfix)); |
| 145 | |
| 146 | if (device->quirks & IS_BIFROST) { |
| 147 | postfix->gl_enables = 0x2; |
| 148 | panfrost_vt_emit_shared_memory(ctx, postfix); |
| 149 | } else { |
| 150 | postfix->gl_enables = 0x6; |
| 151 | panfrost_vt_attach_framebuffer(ctx, postfix); |
| 152 | } |
Boris Brezillon | d66ef69 | 2020-03-06 11:31:06 +0100 | [diff] [blame] | 153 | |
| 154 | if (stage == PIPE_SHADER_FRAGMENT) { |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 155 | panfrost_vt_update_occlusion_query(ctx, postfix); |
| 156 | panfrost_vt_update_rasterizer(ctx, prefix, postfix); |
Boris Brezillon | d66ef69 | 2020-03-06 11:31:06 +0100 | [diff] [blame] | 157 | } |
| 158 | } |
| 159 | |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 160 | static unsigned |
| 161 | panfrost_translate_index_size(unsigned size) |
| 162 | { |
| 163 | switch (size) { |
| 164 | case 1: |
| 165 | return MALI_DRAW_INDEXED_UINT8; |
| 166 | |
| 167 | case 2: |
| 168 | return MALI_DRAW_INDEXED_UINT16; |
| 169 | |
| 170 | case 4: |
| 171 | return MALI_DRAW_INDEXED_UINT32; |
| 172 | |
| 173 | default: |
| 174 | unreachable("Invalid index size"); |
| 175 | } |
| 176 | } |
| 177 | |
| 178 | /* Gets a GPU address for the associated index buffer. Only gauranteed to be |
| 179 | * good for the duration of the draw (transient), could last longer. Also get |
| 180 | * the bounds on the index buffer for the range accessed by the draw. We do |
| 181 | * these operations together because there are natural optimizations which |
| 182 | * require them to be together. */ |
| 183 | |
| 184 | static mali_ptr |
| 185 | panfrost_get_index_buffer_bounded(struct panfrost_context *ctx, |
| 186 | const struct pipe_draw_info *info, |
| 187 | unsigned *min_index, unsigned *max_index) |
| 188 | { |
| 189 | struct panfrost_resource *rsrc = pan_resource(info->index.resource); |
| 190 | struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); |
| 191 | off_t offset = info->start * info->index_size; |
| 192 | bool needs_indices = true; |
| 193 | mali_ptr out = 0; |
| 194 | |
| 195 | if (info->max_index != ~0u) { |
| 196 | *min_index = info->min_index; |
| 197 | *max_index = info->max_index; |
| 198 | needs_indices = false; |
| 199 | } |
| 200 | |
| 201 | if (!info->has_user_indices) { |
| 202 | /* Only resources can be directly mapped */ |
| 203 | panfrost_batch_add_bo(batch, rsrc->bo, |
| 204 | PAN_BO_ACCESS_SHARED | |
| 205 | PAN_BO_ACCESS_READ | |
| 206 | PAN_BO_ACCESS_VERTEX_TILER); |
| 207 | out = rsrc->bo->gpu + offset; |
| 208 | |
| 209 | /* Check the cache */ |
| 210 | needs_indices = !panfrost_minmax_cache_get(rsrc->index_cache, |
| 211 | info->start, |
| 212 | info->count, |
| 213 | min_index, |
| 214 | max_index); |
| 215 | } else { |
| 216 | /* Otherwise, we need to upload to transient memory */ |
| 217 | const uint8_t *ibuf8 = (const uint8_t *) info->index.user; |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 218 | out = panfrost_pool_upload(&batch->pool, ibuf8 + offset, |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 219 | info->count * |
| 220 | info->index_size); |
| 221 | } |
| 222 | |
| 223 | if (needs_indices) { |
| 224 | /* Fallback */ |
| 225 | u_vbuf_get_minmax_index(&ctx->base, info, min_index, max_index); |
| 226 | |
| 227 | if (!info->has_user_indices) |
| 228 | panfrost_minmax_cache_add(rsrc->index_cache, |
| 229 | info->start, info->count, |
| 230 | *min_index, *max_index); |
| 231 | } |
| 232 | |
| 233 | return out; |
| 234 | } |
| 235 | |
| 236 | void |
| 237 | panfrost_vt_set_draw_info(struct panfrost_context *ctx, |
| 238 | const struct pipe_draw_info *info, |
| 239 | enum mali_draw_mode draw_mode, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 240 | struct mali_vertex_tiler_postfix *vertex_postfix, |
| 241 | struct mali_vertex_tiler_prefix *tiler_prefix, |
| 242 | struct mali_vertex_tiler_postfix *tiler_postfix, |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 243 | unsigned *vertex_count, |
| 244 | unsigned *padded_count) |
| 245 | { |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 246 | tiler_prefix->draw_mode = draw_mode; |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 247 | |
| 248 | unsigned draw_flags = 0; |
| 249 | |
| 250 | if (panfrost_writes_point_size(ctx)) |
| 251 | draw_flags |= MALI_DRAW_VARYING_SIZE; |
| 252 | |
| 253 | if (info->primitive_restart) |
| 254 | draw_flags |= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX; |
| 255 | |
| 256 | /* These doesn't make much sense */ |
| 257 | |
| 258 | draw_flags |= 0x3000; |
| 259 | |
| 260 | if (info->index_size) { |
| 261 | unsigned min_index = 0, max_index = 0; |
| 262 | |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 263 | tiler_prefix->indices = panfrost_get_index_buffer_bounded(ctx, |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 264 | info, |
| 265 | &min_index, |
| 266 | &max_index); |
| 267 | |
| 268 | /* Use the corresponding values */ |
| 269 | *vertex_count = max_index - min_index + 1; |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 270 | tiler_postfix->offset_start = vertex_postfix->offset_start = min_index + info->index_bias; |
| 271 | tiler_prefix->offset_bias_correction = -min_index; |
| 272 | tiler_prefix->index_count = MALI_POSITIVE(info->count); |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 273 | draw_flags |= panfrost_translate_index_size(info->index_size); |
| 274 | } else { |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 275 | tiler_prefix->indices = 0; |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 276 | *vertex_count = ctx->vertex_count; |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 277 | tiler_postfix->offset_start = vertex_postfix->offset_start = info->start; |
| 278 | tiler_prefix->offset_bias_correction = 0; |
| 279 | tiler_prefix->index_count = MALI_POSITIVE(ctx->vertex_count); |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 280 | } |
| 281 | |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 282 | tiler_prefix->unknown_draw = draw_flags; |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 283 | |
| 284 | /* Encode the padded vertex count */ |
| 285 | |
| 286 | if (info->instance_count > 1) { |
| 287 | *padded_count = panfrost_padded_vertex_count(*vertex_count); |
| 288 | |
| 289 | unsigned shift = __builtin_ctz(ctx->padded_count); |
| 290 | unsigned k = ctx->padded_count >> (shift + 1); |
| 291 | |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 292 | tiler_postfix->instance_shift = vertex_postfix->instance_shift = shift; |
| 293 | tiler_postfix->instance_odd = vertex_postfix->instance_odd = k; |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 294 | } else { |
| 295 | *padded_count = *vertex_count; |
| 296 | |
| 297 | /* Reset instancing state */ |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 298 | tiler_postfix->instance_shift = vertex_postfix->instance_shift = 0; |
| 299 | tiler_postfix->instance_odd = vertex_postfix->instance_odd = 0; |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 300 | } |
| 301 | } |
| 302 | |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 303 | static void |
| 304 | panfrost_shader_meta_init(struct panfrost_context *ctx, |
| 305 | enum pipe_shader_type st, |
| 306 | struct mali_shader_meta *meta) |
| 307 | { |
Alyssa Rosenzweig | dd09571 | 2020-04-06 17:50:38 -0400 | [diff] [blame] | 308 | const struct panfrost_device *dev = pan_device(ctx->base.screen); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 309 | struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st); |
| 310 | |
| 311 | memset(meta, 0, sizeof(*meta)); |
| 312 | meta->shader = (ss->bo ? ss->bo->gpu : 0) | ss->first_tag; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 313 | meta->attribute_count = ss->attribute_count; |
| 314 | meta->varying_count = ss->varying_count; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 315 | meta->texture_count = ctx->sampler_view_count[st]; |
| 316 | meta->sampler_count = ctx->sampler_count[st]; |
Alyssa Rosenzweig | dd09571 | 2020-04-06 17:50:38 -0400 | [diff] [blame] | 317 | |
| 318 | if (dev->quirks & IS_BIFROST) { |
Alyssa Rosenzweig | d6588b8 | 2020-04-30 10:32:11 +0200 | [diff] [blame] | 319 | if (st == PIPE_SHADER_VERTEX) |
| 320 | meta->bifrost1.unk1 = 0x800000; |
| 321 | else { |
| 322 | /* First clause ATEST |= 0x4000000. |
| 323 | * Less than 32 regs |= 0x200 */ |
Alyssa Rosenzweig | ee6a5a5 | 2020-05-26 19:48:25 -0400 | [diff] [blame] | 324 | meta->bifrost1.unk1 = 0x950020; |
Alyssa Rosenzweig | d6588b8 | 2020-04-30 10:32:11 +0200 | [diff] [blame] | 325 | } |
| 326 | |
Alyssa Rosenzweig | dd09571 | 2020-04-06 17:50:38 -0400 | [diff] [blame] | 327 | meta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, st); |
Alyssa Rosenzweig | d6588b8 | 2020-04-30 10:32:11 +0200 | [diff] [blame] | 328 | if (st == PIPE_SHADER_VERTEX) |
| 329 | meta->bifrost2.preload_regs = 0xC0; |
Alyssa Rosenzweig | 20f6c7a | 2020-05-29 16:06:39 -0400 | [diff] [blame] | 330 | else { |
Alyssa Rosenzweig | d6588b8 | 2020-04-30 10:32:11 +0200 | [diff] [blame] | 331 | meta->bifrost2.preload_regs = 0x1; |
Alyssa Rosenzweig | 20f6c7a | 2020-05-29 16:06:39 -0400 | [diff] [blame] | 332 | SET_BIT(meta->bifrost2.preload_regs, 0x10, ss->reads_frag_coord); |
| 333 | } |
| 334 | |
Alyssa Rosenzweig | dd09571 | 2020-04-06 17:50:38 -0400 | [diff] [blame] | 335 | meta->bifrost2.uniform_count = MIN2(ss->uniform_count, |
| 336 | ss->uniform_cutoff); |
| 337 | } else { |
| 338 | meta->midgard1.uniform_count = MIN2(ss->uniform_count, |
| 339 | ss->uniform_cutoff); |
| 340 | meta->midgard1.work_count = ss->work_reg_count; |
Alyssa Rosenzweig | 55e3305 | 2020-05-27 16:07:00 -0400 | [diff] [blame] | 341 | |
| 342 | /* TODO: This is not conformant on ES3 */ |
| 343 | meta->midgard1.flags_hi = MALI_SUPPRESS_INF_NAN; |
| 344 | |
Alyssa Rosenzweig | dce7722 | 2020-06-02 14:12:29 -0400 | [diff] [blame] | 345 | meta->midgard1.flags_lo = 0x20; |
Alyssa Rosenzweig | dd09571 | 2020-04-06 17:50:38 -0400 | [diff] [blame] | 346 | meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st); |
Alyssa Rosenzweig | dce7722 | 2020-06-02 14:12:29 -0400 | [diff] [blame] | 347 | |
| 348 | SET_BIT(meta->midgard1.flags_hi, MALI_WRITES_GLOBAL, ss->writes_global); |
Alyssa Rosenzweig | dd09571 | 2020-04-06 17:50:38 -0400 | [diff] [blame] | 349 | } |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 350 | } |
| 351 | |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 352 | static unsigned |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 353 | translate_tex_wrap(enum pipe_tex_wrap w) |
| 354 | { |
| 355 | switch (w) { |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 356 | case PIPE_TEX_WRAP_REPEAT: return MALI_WRAP_MODE_REPEAT; |
| 357 | case PIPE_TEX_WRAP_CLAMP: return MALI_WRAP_MODE_CLAMP; |
| 358 | case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return MALI_WRAP_MODE_CLAMP_TO_EDGE; |
| 359 | case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return MALI_WRAP_MODE_CLAMP_TO_BORDER; |
| 360 | case PIPE_TEX_WRAP_MIRROR_REPEAT: return MALI_WRAP_MODE_MIRRORED_REPEAT; |
| 361 | case PIPE_TEX_WRAP_MIRROR_CLAMP: return MALI_WRAP_MODE_MIRRORED_CLAMP; |
| 362 | case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE; |
| 363 | case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER; |
| 364 | default: unreachable("Invalid wrap"); |
| 365 | } |
| 366 | } |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 367 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 368 | /* The hardware compares in the wrong order order, so we have to flip before |
| 369 | * encoding. Yes, really. */ |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 370 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 371 | static enum mali_func |
| 372 | panfrost_sampler_compare_func(const struct pipe_sampler_state *cso) |
| 373 | { |
| 374 | if (!cso->compare_mode) |
| 375 | return MALI_FUNC_NEVER; |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 376 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 377 | enum mali_func f = panfrost_translate_compare_func(cso->compare_func); |
| 378 | return panfrost_flip_compare_func(f); |
| 379 | } |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 380 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 381 | static enum mali_mipmap_mode |
| 382 | pan_pipe_to_mipmode(enum pipe_tex_mipfilter f) |
| 383 | { |
| 384 | switch (f) { |
| 385 | case PIPE_TEX_MIPFILTER_NEAREST: return MALI_MIPMAP_MODE_NEAREST; |
| 386 | case PIPE_TEX_MIPFILTER_LINEAR: return MALI_MIPMAP_MODE_TRILINEAR; |
| 387 | case PIPE_TEX_MIPFILTER_NONE: return MALI_MIPMAP_MODE_NONE; |
| 388 | default: unreachable("Invalid"); |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 389 | } |
| 390 | } |
| 391 | |
| 392 | void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso, |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 393 | struct mali_midgard_sampler_packed *hw) |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 394 | { |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 395 | pan_pack(hw, MIDGARD_SAMPLER, cfg) { |
| 396 | cfg.magnify_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST; |
| 397 | cfg.minify_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST; |
| 398 | cfg.mipmap_mode = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR) ? |
| 399 | MALI_MIPMAP_MODE_TRILINEAR : MALI_MIPMAP_MODE_NEAREST; |
| 400 | cfg.normalized_coordinates = cso->normalized_coords; |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 401 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 402 | cfg.lod_bias = FIXED_16(cso->lod_bias, true); |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 403 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 404 | cfg.minimum_lod = FIXED_16(cso->min_lod, false); |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 405 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 406 | /* If necessary, we disable mipmapping in the sampler descriptor by |
| 407 | * clamping the LOD as tight as possible (from 0 to epsilon, |
| 408 | * essentially -- remember these are fixed point numbers, so |
| 409 | * epsilon=1/256) */ |
| 410 | |
| 411 | cfg.maximum_lod = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) ? |
| 412 | cfg.minimum_lod + 1 : |
| 413 | FIXED_16(cso->max_lod, false); |
| 414 | |
| 415 | cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s); |
| 416 | cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t); |
| 417 | cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r); |
| 418 | |
| 419 | cfg.compare_function = panfrost_sampler_compare_func(cso); |
| 420 | cfg.seamless_cube_map = cso->seamless_cube_map; |
| 421 | |
| 422 | cfg.border_color_r = cso->border_color.f[0]; |
Icecream95 | 8557b1a | 2020-08-13 19:35:00 +1200 | [diff] [blame] | 423 | cfg.border_color_g = cso->border_color.f[1]; |
| 424 | cfg.border_color_b = cso->border_color.f[2]; |
| 425 | cfg.border_color_a = cso->border_color.f[3]; |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 426 | } |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 427 | } |
| 428 | |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 429 | void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso, |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 430 | struct mali_bifrost_sampler_packed *hw) |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 431 | { |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 432 | pan_pack(hw, BIFROST_SAMPLER, cfg) { |
| 433 | cfg.magnify_linear = cso->mag_img_filter == PIPE_TEX_FILTER_LINEAR; |
| 434 | cfg.minify_linear = cso->min_img_filter == PIPE_TEX_FILTER_LINEAR; |
| 435 | cfg.mipmap_mode = pan_pipe_to_mipmode(cso->min_mip_filter); |
| 436 | cfg.normalized_coordinates = cso->normalized_coords; |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 437 | |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 438 | cfg.lod_bias = FIXED_16(cso->lod_bias, true); |
| 439 | cfg.minimum_lod = FIXED_16(cso->min_lod, false); |
| 440 | cfg.maximum_lod = FIXED_16(cso->max_lod, false); |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 441 | |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 442 | cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s); |
| 443 | cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t); |
| 444 | cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r); |
| 445 | |
| 446 | cfg.compare_function = panfrost_sampler_compare_func(cso); |
| 447 | cfg.seamless_cube_map = cso->seamless_cube_map; |
| 448 | } |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 449 | } |
| 450 | |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 451 | static void |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 452 | panfrost_frag_meta_rasterizer_update(struct panfrost_context *ctx, |
| 453 | struct mali_shader_meta *fragmeta) |
| 454 | { |
| 455 | if (!ctx->rasterizer) { |
| 456 | SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, true); |
| 457 | SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, false); |
| 458 | fragmeta->depth_units = 0.0f; |
| 459 | fragmeta->depth_factor = 0.0f; |
| 460 | SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, false); |
| 461 | SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, false); |
Icecream95 | ec628ab | 2020-05-14 15:58:04 +1200 | [diff] [blame] | 462 | SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, true); |
| 463 | SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, true); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 464 | return; |
| 465 | } |
| 466 | |
Icecream95 | fd92dc6 | 2020-05-14 15:54:09 +1200 | [diff] [blame] | 467 | struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; |
| 468 | |
| 469 | bool msaa = rast->multisample; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 470 | |
| 471 | /* TODO: Sample size */ |
| 472 | SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa); |
| 473 | SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa); |
Alyssa Rosenzweig | 8225604 | 2020-07-15 11:38:39 -0400 | [diff] [blame] | 474 | |
Icecream95 | 2a6db94 | 2020-07-16 14:22:38 +1200 | [diff] [blame] | 475 | struct panfrost_shader_state *fs; |
| 476 | fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); |
| 477 | |
| 478 | /* EXT_shader_framebuffer_fetch requires the shader to be run |
| 479 | * per-sample when outputs are read. */ |
| 480 | bool per_sample = ctx->min_samples > 1 || fs->outputs_read; |
| 481 | SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample); |
Alyssa Rosenzweig | 8225604 | 2020-07-15 11:38:39 -0400 | [diff] [blame] | 482 | |
Icecream95 | fd92dc6 | 2020-05-14 15:54:09 +1200 | [diff] [blame] | 483 | fragmeta->depth_units = rast->offset_units * 2.0f; |
| 484 | fragmeta->depth_factor = rast->offset_scale; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 485 | |
| 486 | /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */ |
| 487 | |
Icecream95 | fd92dc6 | 2020-05-14 15:54:09 +1200 | [diff] [blame] | 488 | SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri); |
| 489 | SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri); |
Icecream95 | ec628ab | 2020-05-14 15:58:04 +1200 | [diff] [blame] | 490 | |
| 491 | SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near); |
| 492 | SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 493 | } |
| 494 | |
| 495 | static void |
| 496 | panfrost_frag_meta_zsa_update(struct panfrost_context *ctx, |
| 497 | struct mali_shader_meta *fragmeta) |
| 498 | { |
Alyssa Rosenzweig | 6afd4ad | 2020-08-12 11:42:11 -0400 | [diff] [blame] | 499 | const struct panfrost_zsa_state *so = ctx->depth_stencil; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 500 | int zfunc = PIPE_FUNC_ALWAYS; |
| 501 | |
Alyssa Rosenzweig | 6afd4ad | 2020-08-12 11:42:11 -0400 | [diff] [blame] | 502 | if (!so) { |
Alyssa Rosenzweig | 1675d92 | 2020-08-06 10:02:35 -0400 | [diff] [blame] | 503 | /* If stenciling is disabled, the state is irrelevant */ |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 504 | SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, false); |
| 505 | SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, false); |
| 506 | } else { |
| 507 | SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, |
Alyssa Rosenzweig | 6afd4ad | 2020-08-12 11:42:11 -0400 | [diff] [blame] | 508 | so->base.stencil[0].enabled); |
Alyssa Rosenzweig | 931e7b4 | 2020-08-05 22:02:32 -0400 | [diff] [blame] | 509 | |
Alyssa Rosenzweig | 6afd4ad | 2020-08-12 11:42:11 -0400 | [diff] [blame] | 510 | fragmeta->stencil_mask_front = so->stencil_mask_front; |
| 511 | fragmeta->stencil_mask_back = so->stencil_mask_back; |
| 512 | |
| 513 | /* Bottom bits for stencil ref, exactly one word */ |
| 514 | fragmeta->stencil_front.opaque[0] = so->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0]; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 515 | |
| 516 | /* If back-stencil is not enabled, use the front values */ |
| 517 | |
Alyssa Rosenzweig | 6afd4ad | 2020-08-12 11:42:11 -0400 | [diff] [blame] | 518 | if (so->base.stencil[1].enabled) |
| 519 | fragmeta->stencil_back.opaque[0] = so->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1]; |
| 520 | else |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 521 | fragmeta->stencil_back = fragmeta->stencil_front; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 522 | |
Alyssa Rosenzweig | 6afd4ad | 2020-08-12 11:42:11 -0400 | [diff] [blame] | 523 | if (so->base.depth.enabled) |
| 524 | zfunc = so->base.depth.func; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 525 | |
| 526 | /* Depth state (TODO: Refactor) */ |
| 527 | |
| 528 | SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, |
Alyssa Rosenzweig | 6afd4ad | 2020-08-12 11:42:11 -0400 | [diff] [blame] | 529 | so->base.depth.writemask); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK; |
| 533 | fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(zfunc)); |
| 534 | } |
| 535 | |
Alyssa Rosenzweig | 1085f74 | 2020-05-21 15:49:30 -0400 | [diff] [blame] | 536 | static bool |
| 537 | panfrost_fs_required( |
| 538 | struct panfrost_shader_state *fs, |
| 539 | struct panfrost_blend_final *blend, |
| 540 | unsigned rt_count) |
| 541 | { |
| 542 | /* If we generally have side effects */ |
| 543 | if (fs->fs_sidefx) |
| 544 | return true; |
| 545 | |
| 546 | /* If colour is written we need to execute */ |
| 547 | for (unsigned i = 0; i < rt_count; ++i) { |
| 548 | if (!blend[i].no_colour) |
| 549 | return true; |
| 550 | } |
| 551 | |
| 552 | /* If depth is written and not implied we need to execute. |
| 553 | * TODO: Predicate on Z/S writes being enabled */ |
| 554 | return (fs->writes_depth || fs->writes_stencil); |
| 555 | } |
| 556 | |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 557 | static void |
| 558 | panfrost_frag_meta_blend_update(struct panfrost_context *ctx, |
| 559 | struct mali_shader_meta *fragmeta, |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 560 | void *rts) |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 561 | { |
Alyssa Rosenzweig | 5d0d8fa | 2020-07-15 17:35:58 -0400 | [diff] [blame] | 562 | struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); |
Alyssa Rosenzweig | ca8c625 | 2020-03-23 18:44:21 -0400 | [diff] [blame] | 563 | const struct panfrost_device *dev = pan_device(ctx->base.screen); |
Alyssa Rosenzweig | ef57325 | 2020-05-20 12:40:02 -0400 | [diff] [blame] | 564 | struct panfrost_shader_state *fs; |
| 565 | fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 566 | |
| 567 | SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, |
Alyssa Rosenzweig | ca8c625 | 2020-03-23 18:44:21 -0400 | [diff] [blame] | 568 | (dev->quirks & MIDGARD_SFBD) && ctx->blend && |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 569 | !ctx->blend->base.dither); |
| 570 | |
Alyssa Rosenzweig | 490fbce | 2020-07-02 11:17:37 -0400 | [diff] [blame] | 571 | SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE, |
| 572 | ctx->blend->base.alpha_to_coverage); |
| 573 | |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 574 | /* Get blending setup */ |
| 575 | unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); |
| 576 | |
| 577 | struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; |
| 578 | unsigned shader_offset = 0; |
| 579 | struct panfrost_bo *shader_bo = NULL; |
| 580 | |
| 581 | for (unsigned c = 0; c < rt_count; ++c) |
| 582 | blend[c] = panfrost_get_blend_for_context(ctx, c, &shader_bo, |
| 583 | &shader_offset); |
| 584 | |
Alyssa Rosenzweig | 1085f74 | 2020-05-21 15:49:30 -0400 | [diff] [blame] | 585 | /* Disable shader execution if we can */ |
| 586 | if (dev->quirks & MIDGARD_SHADERLESS |
| 587 | && !panfrost_fs_required(fs, blend, rt_count)) { |
| 588 | fragmeta->shader = 0; |
| 589 | fragmeta->attribute_count = 0; |
| 590 | fragmeta->varying_count = 0; |
| 591 | fragmeta->texture_count = 0; |
| 592 | fragmeta->sampler_count = 0; |
| 593 | |
| 594 | /* This feature is not known to work on Bifrost */ |
| 595 | fragmeta->midgard1.work_count = 1; |
| 596 | fragmeta->midgard1.uniform_count = 0; |
| 597 | fragmeta->midgard1.uniform_buffer_count = 0; |
| 598 | } |
| 599 | |
Alyssa Rosenzweig | 6dd11a6 | 2020-05-21 15:48:03 -0400 | [diff] [blame] | 600 | /* If there is a blend shader, work registers are shared. We impose 8 |
| 601 | * work registers as a limit for blend shaders. Should be lower XXX */ |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 602 | |
Tomeu Vizoso | 9c3e822 | 2020-05-07 14:56:17 +0200 | [diff] [blame] | 603 | if (!(dev->quirks & IS_BIFROST)) { |
| 604 | for (unsigned c = 0; c < rt_count; ++c) { |
Alyssa Rosenzweig | 6dd11a6 | 2020-05-21 15:48:03 -0400 | [diff] [blame] | 605 | if (blend[c].is_shader) { |
| 606 | fragmeta->midgard1.work_count = |
| 607 | MAX2(fragmeta->midgard1.work_count, 8); |
| 608 | } |
Tomeu Vizoso | 9c3e822 | 2020-05-07 14:56:17 +0200 | [diff] [blame] | 609 | } |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 610 | } |
| 611 | |
| 612 | /* Even on MFBD, the shader descriptor gets blend shaders. It's *also* |
| 613 | * copied to the blend_meta appended (by convention), but this is the |
| 614 | * field actually read by the hardware. (Or maybe both are read...?). |
| 615 | * Specify the last RTi with a blend shader. */ |
| 616 | |
| 617 | fragmeta->blend.shader = 0; |
| 618 | |
| 619 | for (signed rt = (rt_count - 1); rt >= 0; --rt) { |
| 620 | if (!blend[rt].is_shader) |
| 621 | continue; |
| 622 | |
| 623 | fragmeta->blend.shader = blend[rt].shader.gpu | |
| 624 | blend[rt].shader.first_tag; |
| 625 | break; |
| 626 | } |
| 627 | |
Alyssa Rosenzweig | ca8c625 | 2020-03-23 18:44:21 -0400 | [diff] [blame] | 628 | if (dev->quirks & MIDGARD_SFBD) { |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 629 | /* When only a single render target platform is used, the blend |
| 630 | * information is inside the shader meta itself. We additionally |
| 631 | * need to signal CAN_DISCARD for nontrivial blend modes (so |
| 632 | * we're able to read back the destination buffer) */ |
| 633 | |
| 634 | SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER, |
| 635 | blend[0].is_shader); |
| 636 | |
| 637 | if (!blend[0].is_shader) { |
| 638 | fragmeta->blend.equation = *blend[0].equation.equation; |
| 639 | fragmeta->blend.constant = blend[0].equation.constant; |
| 640 | } |
| 641 | |
| 642 | SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, |
Alyssa Rosenzweig | ef57325 | 2020-05-20 12:40:02 -0400 | [diff] [blame] | 643 | !blend[0].no_blending || fs->can_discard); |
Alyssa Rosenzweig | 5d0d8fa | 2020-07-15 17:35:58 -0400 | [diff] [blame] | 644 | |
| 645 | batch->draws |= PIPE_CLEAR_COLOR0; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 646 | return; |
| 647 | } |
| 648 | |
Alyssa Rosenzweig | ee6a5a5 | 2020-05-26 19:48:25 -0400 | [diff] [blame] | 649 | if (dev->quirks & IS_BIFROST) { |
| 650 | bool no_blend = true; |
| 651 | |
| 652 | for (unsigned i = 0; i < rt_count; ++i) |
| 653 | no_blend &= (blend[i].no_blending | blend[i].no_colour); |
| 654 | |
| 655 | SET_BIT(fragmeta->bifrost1.unk1, MALI_BIFROST_EARLY_Z, |
| 656 | !fs->can_discard && !fs->writes_depth && no_blend); |
| 657 | } |
| 658 | |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 659 | /* Additional blend descriptor tacked on for jobs using MFBD */ |
| 660 | |
| 661 | for (unsigned i = 0; i < rt_count; ++i) { |
Alyssa Rosenzweig | 3d6cc14 | 2020-05-26 18:48:04 -0400 | [diff] [blame] | 662 | unsigned flags = 0; |
| 663 | |
| 664 | if (ctx->pipe_framebuffer.nr_cbufs > i && !blend[i].no_colour) { |
| 665 | flags = 0x200; |
Alyssa Rosenzweig | 5d0d8fa | 2020-07-15 17:35:58 -0400 | [diff] [blame] | 666 | batch->draws |= (PIPE_CLEAR_COLOR0 << i); |
Alyssa Rosenzweig | 3d6cc14 | 2020-05-26 18:48:04 -0400 | [diff] [blame] | 667 | |
| 668 | bool is_srgb = (ctx->pipe_framebuffer.nr_cbufs > i) && |
| 669 | (ctx->pipe_framebuffer.cbufs[i]) && |
| 670 | util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format); |
| 671 | |
| 672 | SET_BIT(flags, MALI_BLEND_MRT_SHADER, blend[i].is_shader); |
| 673 | SET_BIT(flags, MALI_BLEND_LOAD_TIB, !blend[i].no_blending); |
| 674 | SET_BIT(flags, MALI_BLEND_SRGB, is_srgb); |
| 675 | SET_BIT(flags, MALI_BLEND_NO_DITHER, !ctx->blend->base.dither); |
| 676 | } |
| 677 | |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 678 | if (dev->quirks & IS_BIFROST) { |
| 679 | struct bifrost_blend_rt *brts = rts; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 680 | |
Alyssa Rosenzweig | 3d6cc14 | 2020-05-26 18:48:04 -0400 | [diff] [blame] | 681 | brts[i].flags = flags; |
| 682 | |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 683 | if (blend[i].is_shader) { |
| 684 | /* The blend shader's address needs to be at |
| 685 | * the same top 32 bit as the fragment shader. |
| 686 | * TODO: Ensure that's always the case. |
| 687 | */ |
| 688 | assert((blend[i].shader.gpu & (0xffffffffull << 32)) == |
| 689 | (fs->bo->gpu & (0xffffffffull << 32))); |
| 690 | brts[i].shader = blend[i].shader.gpu; |
| 691 | brts[i].unk2 = 0x0; |
Alyssa Rosenzweig | 83cd3f0 | 2020-05-04 12:48:50 -0400 | [diff] [blame] | 692 | } else if (ctx->pipe_framebuffer.nr_cbufs > i) { |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 693 | enum pipe_format format = ctx->pipe_framebuffer.cbufs[i]->format; |
| 694 | const struct util_format_description *format_desc; |
| 695 | format_desc = util_format_description(format); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 696 | |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 697 | brts[i].equation = *blend[i].equation.equation; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 698 | |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 699 | /* TODO: this is a bit more complicated */ |
| 700 | brts[i].constant = blend[i].equation.constant; |
| 701 | |
| 702 | brts[i].format = panfrost_format_to_bifrost_blend(format_desc); |
Alyssa Rosenzweig | e3692fd | 2020-05-26 18:50:29 -0400 | [diff] [blame] | 703 | |
| 704 | /* 0x19 disables blending and forces REPLACE |
| 705 | * mode (equivalent to rgb_mode = alpha_mode = |
| 706 | * x122, colour mask = 0xF). 0x1a allows |
| 707 | * blending. */ |
| 708 | brts[i].unk2 = blend[i].no_blending ? 0x19 : 0x1a; |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 709 | |
| 710 | brts[i].shader_type = fs->blend_types[i]; |
Alyssa Rosenzweig | 83cd3f0 | 2020-05-04 12:48:50 -0400 | [diff] [blame] | 711 | } else { |
| 712 | /* Dummy attachment for depth-only */ |
| 713 | brts[i].unk2 = 0x3; |
| 714 | brts[i].shader_type = fs->blend_types[i]; |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 715 | } |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 716 | } else { |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 717 | struct midgard_blend_rt *mrts = rts; |
Alyssa Rosenzweig | 3d6cc14 | 2020-05-26 18:48:04 -0400 | [diff] [blame] | 718 | mrts[i].flags = flags; |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 719 | |
| 720 | if (blend[i].is_shader) { |
| 721 | mrts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag; |
| 722 | } else { |
| 723 | mrts[i].blend.equation = *blend[i].equation.equation; |
| 724 | mrts[i].blend.constant = blend[i].equation.constant; |
| 725 | } |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 726 | } |
| 727 | } |
| 728 | } |
| 729 | |
| 730 | static void |
| 731 | panfrost_frag_shader_meta_init(struct panfrost_context *ctx, |
| 732 | struct mali_shader_meta *fragmeta, |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 733 | void *rts) |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 734 | { |
Alyssa Rosenzweig | ca8c625 | 2020-03-23 18:44:21 -0400 | [diff] [blame] | 735 | const struct panfrost_device *dev = pan_device(ctx->base.screen); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 736 | struct panfrost_shader_state *fs; |
| 737 | |
| 738 | fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); |
| 739 | |
Alyssa Rosenzweig | f23cdd4 | 2020-07-02 10:07:08 -0400 | [diff] [blame] | 740 | bool msaa = ctx->rasterizer && ctx->rasterizer->base.multisample; |
Alyssa Rosenzweig | c4c8c8e | 2020-08-06 10:31:28 -0400 | [diff] [blame] | 741 | fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0; |
Alyssa Rosenzweig | f23cdd4 | 2020-07-02 10:07:08 -0400 | [diff] [blame] | 742 | |
Icecream95 | ec628ab | 2020-05-14 15:58:04 +1200 | [diff] [blame] | 743 | fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 744 | fragmeta->unknown2_4 = 0x4e0; |
| 745 | |
| 746 | /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this |
| 747 | * is required (independent of 32-bit/64-bit descriptors), or why it's |
| 748 | * not used on later GPU revisions. Otherwise, all shader jobs fault on |
| 749 | * these earlier chips (perhaps this is a chicken bit of some kind). |
| 750 | * More investigation is needed. */ |
| 751 | |
Alyssa Rosenzweig | ca8c625 | 2020-03-23 18:44:21 -0400 | [diff] [blame] | 752 | SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 753 | |
Tomeu Vizoso | 9c3e822 | 2020-05-07 14:56:17 +0200 | [diff] [blame] | 754 | if (dev->quirks & IS_BIFROST) { |
| 755 | /* TODO */ |
| 756 | } else { |
| 757 | /* Depending on whether it's legal to in the given shader, we try to |
Alyssa Rosenzweig | dce7722 | 2020-06-02 14:12:29 -0400 | [diff] [blame] | 758 | * enable early-z testing. TODO: respect e-z force */ |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 759 | |
Tomeu Vizoso | 9c3e822 | 2020-05-07 14:56:17 +0200 | [diff] [blame] | 760 | SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z, |
Icecream95 | 3a1a40b | 2020-06-06 22:32:04 +1200 | [diff] [blame] | 761 | !fs->can_discard && !fs->writes_global && |
Alyssa Rosenzweig | 490fbce | 2020-07-02 11:17:37 -0400 | [diff] [blame] | 762 | !fs->writes_depth && !fs->writes_stencil && |
| 763 | !ctx->blend->base.alpha_to_coverage); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 764 | |
Tomeu Vizoso | 9c3e822 | 2020-05-07 14:56:17 +0200 | [diff] [blame] | 765 | /* Add the writes Z/S flags if needed. */ |
| 766 | SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth); |
| 767 | SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 768 | |
Tomeu Vizoso | 9c3e822 | 2020-05-07 14:56:17 +0200 | [diff] [blame] | 769 | /* Any time texturing is used, derivatives are implicitly calculated, |
| 770 | * so we need to enable helper invocations */ |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 771 | |
Tomeu Vizoso | 9c3e822 | 2020-05-07 14:56:17 +0200 | [diff] [blame] | 772 | SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS, |
| 773 | fs->helper_invocations); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 774 | |
Icecream95 | ca44c00 | 2020-07-17 21:23:03 +1200 | [diff] [blame] | 775 | /* If discard is enabled, which bit we set to convey this |
| 776 | * depends on if depth/stencil is used for the draw or not. |
| 777 | * Just one of depth OR stencil is enough to trigger this. */ |
Icecream95 | 0dd24b3 | 2020-05-12 14:08:09 +1200 | [diff] [blame] | 778 | |
Alyssa Rosenzweig | 6afd4ad | 2020-08-12 11:42:11 -0400 | [diff] [blame] | 779 | const struct pipe_depth_stencil_alpha_state *zsa = &ctx->depth_stencil->base; |
Icecream95 | ca44c00 | 2020-07-17 21:23:03 +1200 | [diff] [blame] | 780 | bool zs_enabled = fs->writes_depth || fs->writes_stencil; |
| 781 | |
| 782 | if (zsa) { |
| 783 | zs_enabled |= (zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS); |
| 784 | zs_enabled |= zsa->stencil[0].enabled; |
| 785 | } |
Icecream95 | 0dd24b3 | 2020-05-12 14:08:09 +1200 | [diff] [blame] | 786 | |
Icecream95 | e603248 | 2020-07-06 19:41:28 +1200 | [diff] [blame] | 787 | SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_TILEBUFFER, |
Icecream95 | ca44c00 | 2020-07-17 21:23:03 +1200 | [diff] [blame] | 788 | fs->outputs_read || (!zs_enabled && fs->can_discard)); |
| 789 | SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, zs_enabled && fs->can_discard); |
Tomeu Vizoso | 9c3e822 | 2020-05-07 14:56:17 +0200 | [diff] [blame] | 790 | } |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 791 | |
| 792 | panfrost_frag_meta_rasterizer_update(ctx, fragmeta); |
| 793 | panfrost_frag_meta_zsa_update(ctx, fragmeta); |
| 794 | panfrost_frag_meta_blend_update(ctx, fragmeta, rts); |
| 795 | } |
| 796 | |
Boris Brezillon | 56aeb92 | 2020-03-05 11:47:04 +0100 | [diff] [blame] | 797 | void |
Boris Brezillon | 5d33d42 | 2020-03-05 11:02:56 +0100 | [diff] [blame] | 798 | panfrost_emit_shader_meta(struct panfrost_batch *batch, |
| 799 | enum pipe_shader_type st, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 800 | struct mali_vertex_tiler_postfix *postfix) |
Boris Brezillon | 5d33d42 | 2020-03-05 11:02:56 +0100 | [diff] [blame] | 801 | { |
| 802 | struct panfrost_context *ctx = batch->ctx; |
| 803 | struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st); |
| 804 | |
| 805 | if (!ss) { |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 806 | postfix->shader = 0; |
Boris Brezillon | 5d33d42 | 2020-03-05 11:02:56 +0100 | [diff] [blame] | 807 | return; |
| 808 | } |
| 809 | |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 810 | struct mali_shader_meta meta; |
| 811 | |
| 812 | panfrost_shader_meta_init(ctx, st, &meta); |
| 813 | |
Boris Brezillon | 5d33d42 | 2020-03-05 11:02:56 +0100 | [diff] [blame] | 814 | /* Add the shader BO to the batch. */ |
| 815 | panfrost_batch_add_bo(batch, ss->bo, |
| 816 | PAN_BO_ACCESS_PRIVATE | |
| 817 | PAN_BO_ACCESS_READ | |
| 818 | panfrost_bo_access_for_stage(st)); |
| 819 | |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 820 | mali_ptr shader_ptr; |
| 821 | |
| 822 | if (st == PIPE_SHADER_FRAGMENT) { |
Alyssa Rosenzweig | ca8c625 | 2020-03-23 18:44:21 -0400 | [diff] [blame] | 823 | struct panfrost_device *dev = pan_device(ctx->base.screen); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 824 | unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); |
| 825 | size_t desc_size = sizeof(meta); |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 826 | void *rts = NULL; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 827 | struct panfrost_transfer xfer; |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 828 | unsigned rt_size; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 829 | |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 830 | if (dev->quirks & MIDGARD_SFBD) |
| 831 | rt_size = 0; |
| 832 | else if (dev->quirks & IS_BIFROST) |
| 833 | rt_size = sizeof(struct bifrost_blend_rt); |
| 834 | else |
| 835 | rt_size = sizeof(struct midgard_blend_rt); |
| 836 | |
| 837 | desc_size += rt_size * rt_count; |
| 838 | |
| 839 | if (rt_size) |
| 840 | rts = rzalloc_size(ctx, rt_size * rt_count); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 841 | |
| 842 | panfrost_frag_shader_meta_init(ctx, &meta, rts); |
| 843 | |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 844 | xfer = panfrost_pool_alloc(&batch->pool, desc_size); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 845 | |
| 846 | memcpy(xfer.cpu, &meta, sizeof(meta)); |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 847 | memcpy(xfer.cpu + sizeof(meta), rts, rt_size * rt_count); |
| 848 | |
| 849 | if (rt_size) |
| 850 | ralloc_free(rts); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 851 | |
| 852 | shader_ptr = xfer.gpu; |
| 853 | } else { |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 854 | shader_ptr = panfrost_pool_upload(&batch->pool, &meta, |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 855 | sizeof(meta)); |
| 856 | } |
| 857 | |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 858 | postfix->shader = shader_ptr; |
Boris Brezillon | 5d33d42 | 2020-03-05 11:02:56 +0100 | [diff] [blame] | 859 | } |
| 860 | |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 861 | void |
| 862 | panfrost_emit_viewport(struct panfrost_batch *batch, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 863 | struct mali_vertex_tiler_postfix *tiler_postfix) |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 864 | { |
| 865 | struct panfrost_context *ctx = batch->ctx; |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 866 | const struct pipe_viewport_state *vp = &ctx->pipe_viewport; |
| 867 | const struct pipe_scissor_state *ss = &ctx->scissor; |
| 868 | const struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; |
| 869 | const struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer; |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 870 | |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 871 | /* Derive min/max from translate/scale. Note since |x| >= 0 by |
| 872 | * definition, we have that -|x| <= |x| hence translate - |scale| <= |
| 873 | * translate + |scale|, so the ordering is correct here. */ |
| 874 | float vp_minx = (int) (vp->translate[0] - fabsf(vp->scale[0])); |
| 875 | float vp_maxx = (int) (vp->translate[0] + fabsf(vp->scale[0])); |
| 876 | float vp_miny = (int) (vp->translate[1] - fabsf(vp->scale[1])); |
| 877 | float vp_maxy = (int) (vp->translate[1] + fabsf(vp->scale[1])); |
| 878 | float minz = (vp->translate[2] - fabsf(vp->scale[2])); |
| 879 | float maxz = (vp->translate[2] + fabsf(vp->scale[2])); |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 880 | |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 881 | /* Scissor to the intersection of viewport and to the scissor, clamped |
| 882 | * to the framebuffer */ |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 883 | |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 884 | unsigned minx = MIN2(fb->width, vp_minx); |
| 885 | unsigned maxx = MIN2(fb->width, vp_maxx); |
| 886 | unsigned miny = MIN2(fb->height, vp_miny); |
| 887 | unsigned maxy = MIN2(fb->height, vp_maxy); |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 888 | |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 889 | if (ss && rast && rast->scissor) { |
| 890 | minx = MAX2(ss->minx, minx); |
| 891 | miny = MAX2(ss->miny, miny); |
| 892 | maxx = MIN2(ss->maxx, maxx); |
| 893 | maxy = MIN2(ss->maxy, maxy); |
| 894 | } |
| 895 | |
| 896 | struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, MALI_VIEWPORT_LENGTH); |
| 897 | |
| 898 | pan_pack(T.cpu, VIEWPORT, cfg) { |
| 899 | cfg.scissor_minimum_x = minx; |
| 900 | cfg.scissor_minimum_y = miny; |
| 901 | cfg.scissor_maximum_x = maxx - 1; |
| 902 | cfg.scissor_maximum_y = maxy - 1; |
| 903 | |
| 904 | cfg.minimum_z = rast->depth_clip_near ? minz : -INFINITY; |
| 905 | cfg.maximum_z = rast->depth_clip_far ? maxz : INFINITY; |
| 906 | } |
| 907 | |
| 908 | tiler_postfix->viewport = T.gpu; |
| 909 | panfrost_batch_union_scissor(batch, minx, miny, maxx, maxy); |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 910 | } |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 911 | |
| 912 | static mali_ptr |
| 913 | panfrost_map_constant_buffer_gpu(struct panfrost_batch *batch, |
| 914 | enum pipe_shader_type st, |
| 915 | struct panfrost_constant_buffer *buf, |
| 916 | unsigned index) |
| 917 | { |
| 918 | struct pipe_constant_buffer *cb = &buf->cb[index]; |
| 919 | struct panfrost_resource *rsrc = pan_resource(cb->buffer); |
| 920 | |
| 921 | if (rsrc) { |
| 922 | panfrost_batch_add_bo(batch, rsrc->bo, |
| 923 | PAN_BO_ACCESS_SHARED | |
| 924 | PAN_BO_ACCESS_READ | |
| 925 | panfrost_bo_access_for_stage(st)); |
| 926 | |
| 927 | /* Alignment gauranteed by |
| 928 | * PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */ |
| 929 | return rsrc->bo->gpu + cb->buffer_offset; |
| 930 | } else if (cb->user_buffer) { |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 931 | return panfrost_pool_upload(&batch->pool, |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 932 | cb->user_buffer + |
| 933 | cb->buffer_offset, |
| 934 | cb->buffer_size); |
| 935 | } else { |
| 936 | unreachable("No constant buffer"); |
| 937 | } |
| 938 | } |
| 939 | |
| 940 | struct sysval_uniform { |
| 941 | union { |
| 942 | float f[4]; |
| 943 | int32_t i[4]; |
| 944 | uint32_t u[4]; |
| 945 | uint64_t du[2]; |
| 946 | }; |
| 947 | }; |
| 948 | |
| 949 | static void |
| 950 | panfrost_upload_viewport_scale_sysval(struct panfrost_batch *batch, |
| 951 | struct sysval_uniform *uniform) |
| 952 | { |
| 953 | struct panfrost_context *ctx = batch->ctx; |
| 954 | const struct pipe_viewport_state *vp = &ctx->pipe_viewport; |
| 955 | |
| 956 | uniform->f[0] = vp->scale[0]; |
| 957 | uniform->f[1] = vp->scale[1]; |
| 958 | uniform->f[2] = vp->scale[2]; |
| 959 | } |
| 960 | |
| 961 | static void |
| 962 | panfrost_upload_viewport_offset_sysval(struct panfrost_batch *batch, |
| 963 | struct sysval_uniform *uniform) |
| 964 | { |
| 965 | struct panfrost_context *ctx = batch->ctx; |
| 966 | const struct pipe_viewport_state *vp = &ctx->pipe_viewport; |
| 967 | |
| 968 | uniform->f[0] = vp->translate[0]; |
| 969 | uniform->f[1] = vp->translate[1]; |
| 970 | uniform->f[2] = vp->translate[2]; |
| 971 | } |
| 972 | |
| 973 | static void panfrost_upload_txs_sysval(struct panfrost_batch *batch, |
| 974 | enum pipe_shader_type st, |
| 975 | unsigned int sysvalid, |
| 976 | struct sysval_uniform *uniform) |
| 977 | { |
| 978 | struct panfrost_context *ctx = batch->ctx; |
| 979 | unsigned texidx = PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid); |
| 980 | unsigned dim = PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid); |
| 981 | bool is_array = PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid); |
| 982 | struct pipe_sampler_view *tex = &ctx->sampler_views[st][texidx]->base; |
| 983 | |
| 984 | assert(dim); |
| 985 | uniform->i[0] = u_minify(tex->texture->width0, tex->u.tex.first_level); |
| 986 | |
| 987 | if (dim > 1) |
| 988 | uniform->i[1] = u_minify(tex->texture->height0, |
| 989 | tex->u.tex.first_level); |
| 990 | |
| 991 | if (dim > 2) |
| 992 | uniform->i[2] = u_minify(tex->texture->depth0, |
| 993 | tex->u.tex.first_level); |
| 994 | |
| 995 | if (is_array) |
| 996 | uniform->i[dim] = tex->texture->array_size; |
| 997 | } |
| 998 | |
| 999 | static void |
| 1000 | panfrost_upload_ssbo_sysval(struct panfrost_batch *batch, |
| 1001 | enum pipe_shader_type st, |
| 1002 | unsigned ssbo_id, |
| 1003 | struct sysval_uniform *uniform) |
| 1004 | { |
| 1005 | struct panfrost_context *ctx = batch->ctx; |
| 1006 | |
| 1007 | assert(ctx->ssbo_mask[st] & (1 << ssbo_id)); |
| 1008 | struct pipe_shader_buffer sb = ctx->ssbo[st][ssbo_id]; |
| 1009 | |
| 1010 | /* Compute address */ |
| 1011 | struct panfrost_bo *bo = pan_resource(sb.buffer)->bo; |
| 1012 | |
| 1013 | panfrost_batch_add_bo(batch, bo, |
| 1014 | PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_RW | |
| 1015 | panfrost_bo_access_for_stage(st)); |
| 1016 | |
| 1017 | /* Upload address and size as sysval */ |
| 1018 | uniform->du[0] = bo->gpu + sb.buffer_offset; |
| 1019 | uniform->u[2] = sb.buffer_size; |
| 1020 | } |
| 1021 | |
| 1022 | static void |
| 1023 | panfrost_upload_sampler_sysval(struct panfrost_batch *batch, |
| 1024 | enum pipe_shader_type st, |
| 1025 | unsigned samp_idx, |
| 1026 | struct sysval_uniform *uniform) |
| 1027 | { |
| 1028 | struct panfrost_context *ctx = batch->ctx; |
| 1029 | struct pipe_sampler_state *sampl = &ctx->samplers[st][samp_idx]->base; |
| 1030 | |
| 1031 | uniform->f[0] = sampl->min_lod; |
| 1032 | uniform->f[1] = sampl->max_lod; |
| 1033 | uniform->f[2] = sampl->lod_bias; |
| 1034 | |
| 1035 | /* Even without any errata, Midgard represents "no mipmapping" as |
| 1036 | * fixing the LOD with the clamps; keep behaviour consistent. c.f. |
| 1037 | * panfrost_create_sampler_state which also explains our choice of |
| 1038 | * epsilon value (again to keep behaviour consistent) */ |
| 1039 | |
| 1040 | if (sampl->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) |
| 1041 | uniform->f[1] = uniform->f[0] + (1.0/256.0); |
| 1042 | } |
| 1043 | |
| 1044 | static void |
| 1045 | panfrost_upload_num_work_groups_sysval(struct panfrost_batch *batch, |
| 1046 | struct sysval_uniform *uniform) |
| 1047 | { |
| 1048 | struct panfrost_context *ctx = batch->ctx; |
| 1049 | |
| 1050 | uniform->u[0] = ctx->compute_grid->grid[0]; |
| 1051 | uniform->u[1] = ctx->compute_grid->grid[1]; |
| 1052 | uniform->u[2] = ctx->compute_grid->grid[2]; |
| 1053 | } |
| 1054 | |
| 1055 | static void |
| 1056 | panfrost_upload_sysvals(struct panfrost_batch *batch, void *buf, |
| 1057 | struct panfrost_shader_state *ss, |
| 1058 | enum pipe_shader_type st) |
| 1059 | { |
| 1060 | struct sysval_uniform *uniforms = (void *)buf; |
| 1061 | |
| 1062 | for (unsigned i = 0; i < ss->sysval_count; ++i) { |
| 1063 | int sysval = ss->sysval[i]; |
| 1064 | |
| 1065 | switch (PAN_SYSVAL_TYPE(sysval)) { |
| 1066 | case PAN_SYSVAL_VIEWPORT_SCALE: |
| 1067 | panfrost_upload_viewport_scale_sysval(batch, |
| 1068 | &uniforms[i]); |
| 1069 | break; |
| 1070 | case PAN_SYSVAL_VIEWPORT_OFFSET: |
| 1071 | panfrost_upload_viewport_offset_sysval(batch, |
| 1072 | &uniforms[i]); |
| 1073 | break; |
| 1074 | case PAN_SYSVAL_TEXTURE_SIZE: |
| 1075 | panfrost_upload_txs_sysval(batch, st, |
| 1076 | PAN_SYSVAL_ID(sysval), |
| 1077 | &uniforms[i]); |
| 1078 | break; |
| 1079 | case PAN_SYSVAL_SSBO: |
| 1080 | panfrost_upload_ssbo_sysval(batch, st, |
| 1081 | PAN_SYSVAL_ID(sysval), |
| 1082 | &uniforms[i]); |
| 1083 | break; |
| 1084 | case PAN_SYSVAL_NUM_WORK_GROUPS: |
| 1085 | panfrost_upload_num_work_groups_sysval(batch, |
| 1086 | &uniforms[i]); |
| 1087 | break; |
| 1088 | case PAN_SYSVAL_SAMPLER: |
| 1089 | panfrost_upload_sampler_sysval(batch, st, |
| 1090 | PAN_SYSVAL_ID(sysval), |
| 1091 | &uniforms[i]); |
| 1092 | break; |
| 1093 | default: |
| 1094 | assert(0); |
| 1095 | } |
| 1096 | } |
| 1097 | } |
| 1098 | |
| 1099 | static const void * |
| 1100 | panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer *buf, |
| 1101 | unsigned index) |
| 1102 | { |
| 1103 | struct pipe_constant_buffer *cb = &buf->cb[index]; |
| 1104 | struct panfrost_resource *rsrc = pan_resource(cb->buffer); |
| 1105 | |
| 1106 | if (rsrc) |
| 1107 | return rsrc->bo->cpu; |
| 1108 | else if (cb->user_buffer) |
| 1109 | return cb->user_buffer; |
| 1110 | else |
| 1111 | unreachable("No constant buffer"); |
| 1112 | } |
| 1113 | |
| 1114 | void |
| 1115 | panfrost_emit_const_buf(struct panfrost_batch *batch, |
| 1116 | enum pipe_shader_type stage, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 1117 | struct mali_vertex_tiler_postfix *postfix) |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 1118 | { |
| 1119 | struct panfrost_context *ctx = batch->ctx; |
| 1120 | struct panfrost_shader_variants *all = ctx->shader[stage]; |
| 1121 | |
| 1122 | if (!all) |
| 1123 | return; |
| 1124 | |
| 1125 | struct panfrost_constant_buffer *buf = &ctx->constant_buffer[stage]; |
| 1126 | |
| 1127 | struct panfrost_shader_state *ss = &all->variants[all->active_variant]; |
| 1128 | |
| 1129 | /* Uniforms are implicitly UBO #0 */ |
| 1130 | bool has_uniforms = buf->enabled_mask & (1 << 0); |
| 1131 | |
| 1132 | /* Allocate room for the sysval and the uniforms */ |
| 1133 | size_t sys_size = sizeof(float) * 4 * ss->sysval_count; |
| 1134 | size_t uniform_size = has_uniforms ? (buf->cb[0].buffer_size) : 0; |
| 1135 | size_t size = sys_size + uniform_size; |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 1136 | struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool, |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 1137 | size); |
| 1138 | |
| 1139 | /* Upload sysvals requested by the shader */ |
| 1140 | panfrost_upload_sysvals(batch, transfer.cpu, ss, stage); |
| 1141 | |
| 1142 | /* Upload uniforms */ |
| 1143 | if (has_uniforms && uniform_size) { |
| 1144 | const void *cpu = panfrost_map_constant_buffer_cpu(buf, 0); |
| 1145 | memcpy(transfer.cpu + sys_size, cpu, uniform_size); |
| 1146 | } |
| 1147 | |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 1148 | /* Next up, attach UBOs. UBO #0 is the uniforms we just |
| 1149 | * uploaded */ |
| 1150 | |
| 1151 | unsigned ubo_count = panfrost_ubo_count(ctx, stage); |
| 1152 | assert(ubo_count >= 1); |
| 1153 | |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 1154 | size_t sz = MALI_UNIFORM_BUFFER_LENGTH * ubo_count; |
| 1155 | struct panfrost_transfer ubos = panfrost_pool_alloc(&batch->pool, sz); |
| 1156 | uint64_t *ubo_ptr = (uint64_t *) ubos.cpu; |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 1157 | |
| 1158 | /* Upload uniforms as a UBO */ |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 1159 | |
| 1160 | if (ss->uniform_count) { |
| 1161 | pan_pack(ubo_ptr, UNIFORM_BUFFER, cfg) { |
| 1162 | cfg.entries = ss->uniform_count; |
| 1163 | cfg.pointer = transfer.gpu; |
| 1164 | } |
| 1165 | } else { |
| 1166 | *ubo_ptr = 0; |
| 1167 | } |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 1168 | |
| 1169 | /* The rest are honest-to-goodness UBOs */ |
| 1170 | |
| 1171 | for (unsigned ubo = 1; ubo < ubo_count; ++ubo) { |
| 1172 | size_t usz = buf->cb[ubo].buffer_size; |
| 1173 | bool enabled = buf->enabled_mask & (1 << ubo); |
| 1174 | bool empty = usz == 0; |
| 1175 | |
| 1176 | if (!enabled || empty) { |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 1177 | ubo_ptr[ubo] = 0; |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 1178 | continue; |
| 1179 | } |
| 1180 | |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 1181 | pan_pack(ubo_ptr + ubo, UNIFORM_BUFFER, cfg) { |
| 1182 | cfg.entries = DIV_ROUND_UP(usz, 16); |
| 1183 | cfg.pointer = panfrost_map_constant_buffer_gpu(batch, |
| 1184 | stage, buf, ubo); |
| 1185 | } |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 1186 | } |
| 1187 | |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 1188 | postfix->uniforms = transfer.gpu; |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 1189 | postfix->uniform_buffers = ubos.gpu; |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 1190 | |
| 1191 | buf->dirty_mask = 0; |
| 1192 | } |
Boris Brezillon | 36725be | 2020-03-05 09:57:44 +0100 | [diff] [blame] | 1193 | |
| 1194 | void |
| 1195 | panfrost_emit_shared_memory(struct panfrost_batch *batch, |
| 1196 | const struct pipe_grid_info *info, |
| 1197 | struct midgard_payload_vertex_tiler *vtp) |
| 1198 | { |
| 1199 | struct panfrost_context *ctx = batch->ctx; |
| 1200 | struct panfrost_shader_variants *all = ctx->shader[PIPE_SHADER_COMPUTE]; |
| 1201 | struct panfrost_shader_state *ss = &all->variants[all->active_variant]; |
| 1202 | unsigned single_size = util_next_power_of_two(MAX2(ss->shared_size, |
| 1203 | 128)); |
| 1204 | unsigned shared_size = single_size * info->grid[0] * info->grid[1] * |
| 1205 | info->grid[2] * 4; |
| 1206 | struct panfrost_bo *bo = panfrost_batch_get_shared_memory(batch, |
| 1207 | shared_size, |
| 1208 | 1); |
| 1209 | |
| 1210 | struct mali_shared_memory shared = { |
| 1211 | .shared_memory = bo->gpu, |
| 1212 | .shared_workgroup_count = |
| 1213 | util_logbase2_ceil(info->grid[0]) + |
| 1214 | util_logbase2_ceil(info->grid[1]) + |
| 1215 | util_logbase2_ceil(info->grid[2]), |
| 1216 | .shared_unk1 = 0x2, |
| 1217 | .shared_shift = util_logbase2(single_size) - 1 |
| 1218 | }; |
| 1219 | |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 1220 | vtp->postfix.shared_memory = panfrost_pool_upload(&batch->pool, &shared, |
Boris Brezillon | 36725be | 2020-03-05 09:57:44 +0100 | [diff] [blame] | 1221 | sizeof(shared)); |
| 1222 | } |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1223 | |
| 1224 | static mali_ptr |
| 1225 | panfrost_get_tex_desc(struct panfrost_batch *batch, |
| 1226 | enum pipe_shader_type st, |
| 1227 | struct panfrost_sampler_view *view) |
| 1228 | { |
| 1229 | if (!view) |
| 1230 | return (mali_ptr) 0; |
| 1231 | |
| 1232 | struct pipe_sampler_view *pview = &view->base; |
| 1233 | struct panfrost_resource *rsrc = pan_resource(pview->texture); |
| 1234 | |
| 1235 | /* Add the BO to the job so it's retained until the job is done. */ |
| 1236 | |
| 1237 | panfrost_batch_add_bo(batch, rsrc->bo, |
| 1238 | PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | |
| 1239 | panfrost_bo_access_for_stage(st)); |
| 1240 | |
Alyssa Rosenzweig | 32b171d | 2020-06-15 09:20:39 -0400 | [diff] [blame] | 1241 | panfrost_batch_add_bo(batch, view->bo, |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1242 | PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | |
| 1243 | panfrost_bo_access_for_stage(st)); |
| 1244 | |
Alyssa Rosenzweig | 32b171d | 2020-06-15 09:20:39 -0400 | [diff] [blame] | 1245 | return view->bo->gpu; |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1246 | } |
| 1247 | |
Icecream95 | fafc305 | 2020-06-12 20:14:02 +1200 | [diff] [blame] | 1248 | static void |
| 1249 | panfrost_update_sampler_view(struct panfrost_sampler_view *view, |
| 1250 | struct pipe_context *pctx) |
| 1251 | { |
| 1252 | struct panfrost_resource *rsrc = pan_resource(view->base.texture); |
Icecream95 | 65b3b08 | 2020-06-20 19:09:03 +1200 | [diff] [blame] | 1253 | if (view->texture_bo != rsrc->bo->gpu || |
Alyssa Rosenzweig | 965537df | 2020-07-22 10:23:50 -0400 | [diff] [blame] | 1254 | view->modifier != rsrc->modifier) { |
Alyssa Rosenzweig | 32b171d | 2020-06-15 09:20:39 -0400 | [diff] [blame] | 1255 | panfrost_bo_unreference(view->bo); |
Icecream95 | fafc305 | 2020-06-12 20:14:02 +1200 | [diff] [blame] | 1256 | panfrost_create_sampler_view_bo(view, pctx, &rsrc->base); |
| 1257 | } |
| 1258 | } |
| 1259 | |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1260 | void |
| 1261 | panfrost_emit_texture_descriptors(struct panfrost_batch *batch, |
| 1262 | enum pipe_shader_type stage, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 1263 | struct mali_vertex_tiler_postfix *postfix) |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1264 | { |
| 1265 | struct panfrost_context *ctx = batch->ctx; |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1266 | struct panfrost_device *device = pan_device(ctx->base.screen); |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1267 | |
| 1268 | if (!ctx->sampler_view_count[stage]) |
| 1269 | return; |
| 1270 | |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1271 | if (device->quirks & IS_BIFROST) { |
Alyssa Rosenzweig | ad0b32c | 2020-08-06 18:12:28 -0400 | [diff] [blame] | 1272 | struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, |
| 1273 | MALI_BIFROST_TEXTURE_LENGTH * |
| 1274 | ctx->sampler_view_count[stage]); |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1275 | |
Alyssa Rosenzweig | ad0b32c | 2020-08-06 18:12:28 -0400 | [diff] [blame] | 1276 | struct mali_bifrost_texture_packed *out = |
| 1277 | (struct mali_bifrost_texture_packed *) T.cpu; |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1278 | |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1279 | for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) { |
| 1280 | struct panfrost_sampler_view *view = ctx->sampler_views[stage][i]; |
| 1281 | struct pipe_sampler_view *pview = &view->base; |
| 1282 | struct panfrost_resource *rsrc = pan_resource(pview->texture); |
Alyssa Rosenzweig | ad0b32c | 2020-08-06 18:12:28 -0400 | [diff] [blame] | 1283 | |
Alyssa Rosenzweig | 65e0e89 | 2020-06-15 09:23:27 -0400 | [diff] [blame] | 1284 | panfrost_update_sampler_view(view, &ctx->base); |
Alyssa Rosenzweig | ad0b32c | 2020-08-06 18:12:28 -0400 | [diff] [blame] | 1285 | out[i] = view->bifrost_descriptor; |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1286 | |
Tomeu Vizoso | 3a81abf | 2020-05-01 11:37:56 +0200 | [diff] [blame] | 1287 | /* Add the BOs to the job so they are retained until the job is done. */ |
| 1288 | |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1289 | panfrost_batch_add_bo(batch, rsrc->bo, |
| 1290 | PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | |
| 1291 | panfrost_bo_access_for_stage(stage)); |
| 1292 | |
Alyssa Rosenzweig | 32b171d | 2020-06-15 09:20:39 -0400 | [diff] [blame] | 1293 | panfrost_batch_add_bo(batch, view->bo, |
Tomeu Vizoso | 3a81abf | 2020-05-01 11:37:56 +0200 | [diff] [blame] | 1294 | PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | |
| 1295 | panfrost_bo_access_for_stage(stage)); |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1296 | } |
| 1297 | |
Alyssa Rosenzweig | ad0b32c | 2020-08-06 18:12:28 -0400 | [diff] [blame] | 1298 | postfix->textures = T.gpu; |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1299 | } else { |
| 1300 | uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS]; |
| 1301 | |
Icecream95 | fafc305 | 2020-06-12 20:14:02 +1200 | [diff] [blame] | 1302 | for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) { |
| 1303 | struct panfrost_sampler_view *view = ctx->sampler_views[stage][i]; |
| 1304 | |
| 1305 | panfrost_update_sampler_view(view, &ctx->base); |
| 1306 | |
| 1307 | trampolines[i] = panfrost_get_tex_desc(batch, stage, view); |
| 1308 | } |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1309 | |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 1310 | postfix->textures = panfrost_pool_upload(&batch->pool, |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1311 | trampolines, |
| 1312 | sizeof(uint64_t) * |
| 1313 | ctx->sampler_view_count[stage]); |
| 1314 | } |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1315 | } |
| 1316 | |
| 1317 | void |
| 1318 | panfrost_emit_sampler_descriptors(struct panfrost_batch *batch, |
| 1319 | enum pipe_shader_type stage, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 1320 | struct mali_vertex_tiler_postfix *postfix) |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1321 | { |
| 1322 | struct panfrost_context *ctx = batch->ctx; |
| 1323 | |
| 1324 | if (!ctx->sampler_count[stage]) |
| 1325 | return; |
| 1326 | |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 1327 | size_t desc_size = MALI_BIFROST_SAMPLER_LENGTH; |
| 1328 | assert(MALI_BIFROST_SAMPLER_LENGTH == MALI_MIDGARD_SAMPLER_LENGTH); |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1329 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 1330 | size_t sz = desc_size * ctx->sampler_count[stage]; |
| 1331 | struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, sz); |
| 1332 | struct mali_midgard_sampler_packed *out = (struct mali_midgard_sampler_packed *) T.cpu; |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1333 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 1334 | for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i) |
| 1335 | out[i] = ctx->samplers[stage][i]->hw; |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 1336 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 1337 | postfix->sampler_descriptor = T.gpu; |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1338 | } |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 1339 | |
| 1340 | void |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1341 | panfrost_emit_vertex_data(struct panfrost_batch *batch, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 1342 | struct mali_vertex_tiler_postfix *vertex_postfix) |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1343 | { |
| 1344 | struct panfrost_context *ctx = batch->ctx; |
| 1345 | struct panfrost_vertex_state *so = ctx->vertex; |
| 1346 | |
Alyssa Rosenzweig | e9dc225 | 2020-08-14 12:25:18 -0400 | [diff] [blame] | 1347 | unsigned instance_shift = vertex_postfix->instance_shift; |
| 1348 | unsigned instance_odd = vertex_postfix->instance_odd; |
| 1349 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1350 | /* Worst case: everything is NPOT */ |
| 1351 | |
| 1352 | struct panfrost_transfer S = panfrost_pool_alloc(&batch->pool, |
| 1353 | MALI_ATTRIBUTE_LENGTH * PIPE_MAX_ATTRIBS * 2); |
| 1354 | |
| 1355 | struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, |
| 1356 | MALI_ATTRIBUTE_LENGTH * (PAN_INSTANCE_ID + 1)); |
| 1357 | |
| 1358 | struct mali_attribute_buffer_packed *bufs = |
| 1359 | (struct mali_attribute_buffer_packed *) S.cpu; |
| 1360 | |
| 1361 | struct mali_attribute_packed *out = |
| 1362 | (struct mali_attribute_packed *) T.cpu; |
| 1363 | |
Alyssa Rosenzweig | 8236fa3 | 2020-08-14 12:09:05 -0400 | [diff] [blame] | 1364 | unsigned attrib_to_buffer[PIPE_MAX_ATTRIBS] = { 0 }; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1365 | unsigned k = 0; |
| 1366 | |
| 1367 | for (unsigned i = 0; i < so->num_elements; ++i) { |
| 1368 | /* We map a mali_attr to be 1:1 with the mali_attr_meta, which |
| 1369 | * means duplicating some vertex buffers (who cares? aside from |
| 1370 | * maybe some caching implications but I somehow doubt that |
| 1371 | * matters) */ |
| 1372 | |
| 1373 | struct pipe_vertex_element *elem = &so->pipe[i]; |
| 1374 | unsigned vbi = elem->vertex_buffer_index; |
Alyssa Rosenzweig | 8236fa3 | 2020-08-14 12:09:05 -0400 | [diff] [blame] | 1375 | attrib_to_buffer[i] = k; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1376 | |
| 1377 | if (!(ctx->vb_mask & (1 << vbi))) |
| 1378 | continue; |
| 1379 | |
| 1380 | struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi]; |
| 1381 | struct panfrost_resource *rsrc; |
| 1382 | |
| 1383 | rsrc = pan_resource(buf->buffer.resource); |
| 1384 | if (!rsrc) |
| 1385 | continue; |
| 1386 | |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1387 | /* Add a dependency of the batch on the vertex buffer */ |
| 1388 | panfrost_batch_add_bo(batch, rsrc->bo, |
| 1389 | PAN_BO_ACCESS_SHARED | |
| 1390 | PAN_BO_ACCESS_READ | |
| 1391 | PAN_BO_ACCESS_VERTEX_TILER); |
| 1392 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1393 | /* Mask off lower bits, see offset fixup below */ |
| 1394 | mali_ptr raw_addr = rsrc->bo->gpu + buf->buffer_offset; |
| 1395 | mali_ptr addr = raw_addr & ~63; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1396 | |
| 1397 | /* Since we advanced the base pointer, we shrink the buffer |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1398 | * size, but add the offset we subtracted */ |
| 1399 | unsigned size = rsrc->base.width0 + (raw_addr - addr) |
| 1400 | - buf->buffer_offset; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1401 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1402 | /* When there is a divisor, the hardware-level divisor is |
| 1403 | * the product of the instance divisor and the padded count */ |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1404 | unsigned divisor = elem->instance_divisor; |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1405 | unsigned hw_divisor = ctx->padded_count * divisor; |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1406 | unsigned stride = buf->stride; |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1407 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1408 | /* If there's a divisor(=1) but no instancing, we want every |
| 1409 | * attribute to be the same */ |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1410 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1411 | if (divisor && ctx->instance_count == 1) |
| 1412 | stride = 0; |
| 1413 | |
| 1414 | if (!divisor || ctx->instance_count <= 1) { |
| 1415 | pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { |
| 1416 | if (ctx->instance_count > 1) |
| 1417 | cfg.type = MALI_ATTRIBUTE_TYPE_1D_MODULUS; |
| 1418 | |
| 1419 | cfg.pointer = addr; |
| 1420 | cfg.stride = stride; |
| 1421 | cfg.size = size; |
| 1422 | cfg.divisor_r = instance_shift; |
| 1423 | cfg.divisor_p = instance_odd; |
| 1424 | } |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1425 | } else if (util_is_power_of_two_or_zero(hw_divisor)) { |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1426 | pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { |
| 1427 | cfg.type = MALI_ATTRIBUTE_TYPE_1D_POT_DIVISOR; |
| 1428 | cfg.pointer = addr; |
| 1429 | cfg.stride = stride; |
| 1430 | cfg.size = size; |
| 1431 | cfg.divisor_r = __builtin_ctz(hw_divisor); |
| 1432 | } |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1433 | |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1434 | } else { |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1435 | unsigned shift = 0, extra_flags = 0; |
| 1436 | |
| 1437 | unsigned magic_divisor = |
| 1438 | panfrost_compute_magic_divisor(hw_divisor, &shift, &extra_flags); |
| 1439 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1440 | pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { |
| 1441 | cfg.type = MALI_ATTRIBUTE_TYPE_1D_NPOT_DIVISOR; |
| 1442 | cfg.pointer = addr; |
| 1443 | cfg.stride = stride; |
| 1444 | cfg.size = size; |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1445 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1446 | cfg.divisor_r = shift; |
| 1447 | cfg.divisor_e = extra_flags; |
| 1448 | } |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1449 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1450 | pan_pack(bufs + k + 1, ATTRIBUTE_BUFFER_CONTINUATION_NPOT, cfg) { |
| 1451 | cfg.divisor_numerator = magic_divisor; |
| 1452 | cfg.divisor = divisor; |
| 1453 | } |
| 1454 | |
| 1455 | ++k; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1456 | } |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1457 | |
| 1458 | ++k; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1459 | } |
| 1460 | |
| 1461 | /* Add special gl_VertexID/gl_InstanceID buffers */ |
| 1462 | |
Alyssa Rosenzweig | 44397c5 | 2020-08-14 13:27:51 -0400 | [diff] [blame^] | 1463 | panfrost_vertex_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); |
Alyssa Rosenzweig | 27f8b87 | 2020-08-14 12:19:10 -0400 | [diff] [blame] | 1464 | |
| 1465 | pan_pack(out + PAN_VERTEX_ID, ATTRIBUTE, cfg) { |
| 1466 | cfg.buffer_index = k++; |
| 1467 | cfg.format = so->formats[PAN_VERTEX_ID]; |
| 1468 | } |
Alyssa Rosenzweig | 6caf789 | 2020-08-14 12:14:20 -0400 | [diff] [blame] | 1469 | |
Alyssa Rosenzweig | 44397c5 | 2020-08-14 13:27:51 -0400 | [diff] [blame^] | 1470 | panfrost_instance_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); |
Alyssa Rosenzweig | 27f8b87 | 2020-08-14 12:19:10 -0400 | [diff] [blame] | 1471 | |
| 1472 | pan_pack(out + PAN_INSTANCE_ID, ATTRIBUTE, cfg) { |
| 1473 | cfg.buffer_index = k++; |
| 1474 | cfg.format = so->formats[PAN_INSTANCE_ID]; |
| 1475 | } |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1476 | |
Alyssa Rosenzweig | 9cc81ea | 2020-08-14 12:01:55 -0400 | [diff] [blame] | 1477 | /* Attribute addresses require 64-byte alignment, so let: |
Alyssa Rosenzweig | 76de3e6 | 2020-08-13 14:32:23 -0400 | [diff] [blame] | 1478 | * |
| 1479 | * base' = base & ~63 = base - (base & 63) |
Alyssa Rosenzweig | 9cc81ea | 2020-08-14 12:01:55 -0400 | [diff] [blame] | 1480 | * offset' = offset + (base & 63) |
Alyssa Rosenzweig | 76de3e6 | 2020-08-13 14:32:23 -0400 | [diff] [blame] | 1481 | * |
Alyssa Rosenzweig | 9cc81ea | 2020-08-14 12:01:55 -0400 | [diff] [blame] | 1482 | * Since base' + offset' = base + offset, these are equivalent |
| 1483 | * addressing modes and now base is 64 aligned. |
Alyssa Rosenzweig | 76de3e6 | 2020-08-13 14:32:23 -0400 | [diff] [blame] | 1484 | */ |
| 1485 | |
| 1486 | unsigned start = vertex_postfix->offset_start; |
| 1487 | |
| 1488 | for (unsigned i = 0; i < so->num_elements; ++i) { |
| 1489 | unsigned vbi = so->pipe[i].vertex_buffer_index; |
| 1490 | struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi]; |
| 1491 | |
| 1492 | /* Adjust by the masked off bits of the offset. Make sure we |
| 1493 | * read src_offset from so->hw (which is not GPU visible) |
| 1494 | * rather than target (which is) due to caching effects */ |
| 1495 | |
| 1496 | unsigned src_offset = so->pipe[i].src_offset; |
| 1497 | |
| 1498 | /* BOs aligned to 4k so guaranteed aligned to 64 */ |
| 1499 | src_offset += (buf->buffer_offset & 63); |
| 1500 | |
| 1501 | /* Also, somewhat obscurely per-instance data needs to be |
| 1502 | * offset in response to a delayed start in an indexed draw */ |
| 1503 | |
| 1504 | if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start) |
| 1505 | src_offset -= buf->stride * start; |
| 1506 | |
Alyssa Rosenzweig | 27f8b87 | 2020-08-14 12:19:10 -0400 | [diff] [blame] | 1507 | pan_pack(out + i, ATTRIBUTE, cfg) { |
| 1508 | cfg.buffer_index = attrib_to_buffer[i]; |
| 1509 | cfg.format = so->formats[i]; |
| 1510 | cfg.offset = src_offset; |
| 1511 | } |
Alyssa Rosenzweig | 76de3e6 | 2020-08-13 14:32:23 -0400 | [diff] [blame] | 1512 | } |
| 1513 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1514 | vertex_postfix->attributes = S.gpu; |
Alyssa Rosenzweig | 27f8b87 | 2020-08-14 12:19:10 -0400 | [diff] [blame] | 1515 | vertex_postfix->attribute_meta = T.gpu; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1516 | } |
| 1517 | |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1518 | static mali_ptr |
| 1519 | panfrost_emit_varyings(struct panfrost_batch *batch, union mali_attr *slot, |
| 1520 | unsigned stride, unsigned count) |
| 1521 | { |
| 1522 | /* Fill out the descriptor */ |
| 1523 | slot->stride = stride; |
| 1524 | slot->size = stride * count; |
| 1525 | slot->shift = slot->extra_flags = 0; |
| 1526 | |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 1527 | struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool, |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1528 | slot->size); |
| 1529 | |
| 1530 | slot->elements = transfer.gpu | MALI_ATTR_LINEAR; |
| 1531 | |
| 1532 | return transfer.gpu; |
| 1533 | } |
| 1534 | |
Alyssa Rosenzweig | e26ac2e | 2020-06-10 19:28:28 -0400 | [diff] [blame] | 1535 | static unsigned |
| 1536 | panfrost_streamout_offset(unsigned stride, unsigned offset, |
| 1537 | struct pipe_stream_output_target *target) |
| 1538 | { |
| 1539 | return (target->buffer_offset + (offset * stride * 4)) & 63; |
| 1540 | } |
| 1541 | |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1542 | static void |
| 1543 | panfrost_emit_streamout(struct panfrost_batch *batch, union mali_attr *slot, |
| 1544 | unsigned stride, unsigned offset, unsigned count, |
| 1545 | struct pipe_stream_output_target *target) |
| 1546 | { |
| 1547 | /* Fill out the descriptor */ |
| 1548 | slot->stride = stride * 4; |
| 1549 | slot->shift = slot->extra_flags = 0; |
| 1550 | |
| 1551 | unsigned max_size = target->buffer_size; |
| 1552 | unsigned expected_size = slot->stride * count; |
| 1553 | |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1554 | /* Grab the BO and bind it to the batch */ |
| 1555 | struct panfrost_bo *bo = pan_resource(target->buffer)->bo; |
| 1556 | |
| 1557 | /* Varyings are WRITE from the perspective of the VERTEX but READ from |
| 1558 | * the perspective of the TILER and FRAGMENT. |
| 1559 | */ |
| 1560 | panfrost_batch_add_bo(batch, bo, |
| 1561 | PAN_BO_ACCESS_SHARED | |
| 1562 | PAN_BO_ACCESS_RW | |
| 1563 | PAN_BO_ACCESS_VERTEX_TILER | |
| 1564 | PAN_BO_ACCESS_FRAGMENT); |
| 1565 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1566 | /* We will have an offset applied to get alignment */ |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1567 | mali_ptr addr = bo->gpu + target->buffer_offset + (offset * slot->stride); |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1568 | slot->elements = (addr & ~63) | MALI_ATTR_LINEAR; |
| 1569 | slot->size = MIN2(max_size, expected_size) + (addr & 63); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1570 | } |
| 1571 | |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1572 | static bool |
| 1573 | has_point_coord(unsigned mask, gl_varying_slot loc) |
| 1574 | { |
| 1575 | if ((loc >= VARYING_SLOT_TEX0) && (loc <= VARYING_SLOT_TEX7)) |
| 1576 | return (mask & (1 << (loc - VARYING_SLOT_TEX0))); |
| 1577 | else if (loc == VARYING_SLOT_PNTC) |
| 1578 | return (mask & (1 << 8)); |
| 1579 | else |
| 1580 | return false; |
| 1581 | } |
| 1582 | |
| 1583 | /* Helpers for manipulating stream out information so we can pack varyings |
| 1584 | * accordingly. Compute the src_offset for a given captured varying */ |
| 1585 | |
| 1586 | static struct pipe_stream_output * |
| 1587 | pan_get_so(struct pipe_stream_output_info *info, gl_varying_slot loc) |
| 1588 | { |
| 1589 | for (unsigned i = 0; i < info->num_outputs; ++i) { |
| 1590 | if (info->output[i].register_index == loc) |
| 1591 | return &info->output[i]; |
| 1592 | } |
| 1593 | |
| 1594 | unreachable("Varying not captured"); |
| 1595 | } |
| 1596 | |
Alyssa Rosenzweig | 24c3b95 | 2020-06-10 15:35:41 -0400 | [diff] [blame] | 1597 | static unsigned |
| 1598 | pan_varying_size(enum mali_format fmt) |
| 1599 | { |
| 1600 | unsigned type = MALI_EXTRACT_TYPE(fmt); |
| 1601 | unsigned chan = MALI_EXTRACT_CHANNELS(fmt); |
| 1602 | unsigned bits = MALI_EXTRACT_BITS(fmt); |
| 1603 | unsigned bpc = 0; |
| 1604 | |
| 1605 | if (bits == MALI_CHANNEL_FLOAT) { |
| 1606 | /* No doubles */ |
| 1607 | bool fp16 = (type == MALI_FORMAT_SINT); |
| 1608 | assert(fp16 || (type == MALI_FORMAT_UNORM)); |
| 1609 | |
| 1610 | bpc = fp16 ? 2 : 4; |
| 1611 | } else { |
| 1612 | assert(type >= MALI_FORMAT_SNORM && type <= MALI_FORMAT_SINT); |
| 1613 | |
| 1614 | /* See the enums */ |
| 1615 | bits = 1 << bits; |
| 1616 | assert(bits >= 8); |
| 1617 | bpc = bits / 8; |
| 1618 | } |
| 1619 | |
| 1620 | return bpc * chan; |
| 1621 | } |
| 1622 | |
Alyssa Rosenzweig | 258b80b | 2020-06-08 12:56:33 -0400 | [diff] [blame] | 1623 | /* Indices for named (non-XFB) varyings that are present. These are packed |
| 1624 | * tightly so they correspond to a bitfield present (P) indexed by (1 << |
| 1625 | * PAN_VARY_*). This has the nice property that you can lookup the buffer index |
| 1626 | * of a given special field given a shift S by: |
| 1627 | * |
| 1628 | * idx = popcount(P & ((1 << S) - 1)) |
| 1629 | * |
| 1630 | * That is... look at all of the varyings that come earlier and count them, the |
| 1631 | * count is the new index since plus one. Likewise, the total number of special |
| 1632 | * buffers required is simply popcount(P) |
| 1633 | */ |
| 1634 | |
| 1635 | enum pan_special_varying { |
| 1636 | PAN_VARY_GENERAL = 0, |
| 1637 | PAN_VARY_POSITION = 1, |
| 1638 | PAN_VARY_PSIZ = 2, |
| 1639 | PAN_VARY_PNTCOORD = 3, |
| 1640 | PAN_VARY_FACE = 4, |
| 1641 | PAN_VARY_FRAGCOORD = 5, |
| 1642 | |
| 1643 | /* Keep last */ |
| 1644 | PAN_VARY_MAX, |
| 1645 | }; |
| 1646 | |
| 1647 | /* Given a varying, figure out which index it correpsonds to */ |
| 1648 | |
| 1649 | static inline unsigned |
| 1650 | pan_varying_index(unsigned present, enum pan_special_varying v) |
| 1651 | { |
| 1652 | unsigned mask = (1 << v) - 1; |
| 1653 | return util_bitcount(present & mask); |
| 1654 | } |
| 1655 | |
| 1656 | /* Get the base offset for XFB buffers, which by convention come after |
| 1657 | * everything else. Wrapper function for semantic reasons; by construction this |
| 1658 | * is just popcount. */ |
| 1659 | |
| 1660 | static inline unsigned |
| 1661 | pan_xfb_base(unsigned present) |
| 1662 | { |
| 1663 | return util_bitcount(present); |
| 1664 | } |
| 1665 | |
Alyssa Rosenzweig | 3d04ebf | 2020-06-08 13:32:38 -0400 | [diff] [blame] | 1666 | /* Computes the present mask for varyings so we can start emitting varying records */ |
| 1667 | |
| 1668 | static inline unsigned |
| 1669 | pan_varying_present( |
| 1670 | struct panfrost_shader_state *vs, |
| 1671 | struct panfrost_shader_state *fs, |
| 1672 | unsigned quirks) |
| 1673 | { |
| 1674 | /* At the moment we always emit general and position buffers. Not |
| 1675 | * strictly necessary but usually harmless */ |
| 1676 | |
| 1677 | unsigned present = (1 << PAN_VARY_GENERAL) | (1 << PAN_VARY_POSITION); |
| 1678 | |
| 1679 | /* Enable special buffers by the shader info */ |
| 1680 | |
| 1681 | if (vs->writes_point_size) |
| 1682 | present |= (1 << PAN_VARY_PSIZ); |
| 1683 | |
| 1684 | if (fs->reads_point_coord) |
| 1685 | present |= (1 << PAN_VARY_PNTCOORD); |
| 1686 | |
| 1687 | if (fs->reads_face) |
| 1688 | present |= (1 << PAN_VARY_FACE); |
| 1689 | |
| 1690 | if (fs->reads_frag_coord && !(quirks & IS_BIFROST)) |
| 1691 | present |= (1 << PAN_VARY_FRAGCOORD); |
| 1692 | |
| 1693 | /* Also, if we have a point sprite, we need a point coord buffer */ |
| 1694 | |
| 1695 | for (unsigned i = 0; i < fs->varying_count; i++) { |
| 1696 | gl_varying_slot loc = fs->varyings_loc[i]; |
| 1697 | |
| 1698 | if (has_point_coord(fs->point_sprite_mask, loc)) |
| 1699 | present |= (1 << PAN_VARY_PNTCOORD); |
| 1700 | } |
| 1701 | |
| 1702 | return present; |
| 1703 | } |
| 1704 | |
Alyssa Rosenzweig | 0c0217d | 2020-06-08 13:45:17 -0400 | [diff] [blame] | 1705 | /* Emitters for varying records */ |
| 1706 | |
| 1707 | static struct mali_attr_meta |
| 1708 | pan_emit_vary(unsigned present, enum pan_special_varying buf, |
| 1709 | unsigned quirks, enum mali_format format, |
| 1710 | unsigned offset) |
| 1711 | { |
| 1712 | unsigned nr_channels = MALI_EXTRACT_CHANNELS(format); |
Alyssa Rosenzweig | 668ec24 | 2020-08-11 22:26:03 -0400 | [diff] [blame] | 1713 | unsigned swizzle = quirks & HAS_SWIZZLES ? |
| 1714 | panfrost_get_default_swizzle(nr_channels) : |
| 1715 | panfrost_bifrost_swizzle(nr_channels); |
Alyssa Rosenzweig | 0c0217d | 2020-06-08 13:45:17 -0400 | [diff] [blame] | 1716 | |
| 1717 | struct mali_attr_meta meta = { |
| 1718 | .index = pan_varying_index(present, buf), |
| 1719 | .unknown1 = quirks & IS_BIFROST ? 0x0 : 0x2, |
Alyssa Rosenzweig | 668ec24 | 2020-08-11 22:26:03 -0400 | [diff] [blame] | 1720 | .format = (format << 12) | swizzle, |
Alyssa Rosenzweig | 0c0217d | 2020-06-08 13:45:17 -0400 | [diff] [blame] | 1721 | .src_offset = offset |
| 1722 | }; |
| 1723 | |
| 1724 | return meta; |
| 1725 | } |
| 1726 | |
| 1727 | /* General varying that is unused */ |
| 1728 | |
| 1729 | static struct mali_attr_meta |
| 1730 | pan_emit_vary_only(unsigned present, unsigned quirks) |
| 1731 | { |
| 1732 | return pan_emit_vary(present, 0, quirks, MALI_VARYING_DISCARD, 0); |
| 1733 | } |
| 1734 | |
Alyssa Rosenzweig | df24209 | 2020-06-08 13:52:38 -0400 | [diff] [blame] | 1735 | /* Special records */ |
| 1736 | |
| 1737 | static const enum mali_format pan_varying_formats[PAN_VARY_MAX] = { |
| 1738 | [PAN_VARY_POSITION] = MALI_VARYING_POS, |
| 1739 | [PAN_VARY_PSIZ] = MALI_R16F, |
| 1740 | [PAN_VARY_PNTCOORD] = MALI_R16F, |
| 1741 | [PAN_VARY_FACE] = MALI_R32I, |
| 1742 | [PAN_VARY_FRAGCOORD] = MALI_RGBA32F |
| 1743 | }; |
| 1744 | |
| 1745 | static struct mali_attr_meta |
| 1746 | pan_emit_vary_special(unsigned present, enum pan_special_varying buf, |
| 1747 | unsigned quirks) |
| 1748 | { |
| 1749 | assert(buf < PAN_VARY_MAX); |
| 1750 | return pan_emit_vary(present, buf, quirks, pan_varying_formats[buf], 0); |
| 1751 | } |
| 1752 | |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1753 | static enum mali_format |
| 1754 | pan_xfb_format(enum mali_format format, unsigned nr) |
| 1755 | { |
| 1756 | if (MALI_EXTRACT_BITS(format) == MALI_CHANNEL_FLOAT) |
| 1757 | return MALI_R32F | MALI_NR_CHANNELS(nr); |
| 1758 | else |
| 1759 | return MALI_EXTRACT_TYPE(format) | MALI_NR_CHANNELS(nr) | MALI_CHANNEL_32; |
| 1760 | } |
| 1761 | |
| 1762 | /* Transform feedback records. Note struct pipe_stream_output is (if packed as |
| 1763 | * a bitfield) 32-bit, smaller than a 64-bit pointer, so may as well pass by |
| 1764 | * value. */ |
| 1765 | |
| 1766 | static struct mali_attr_meta |
| 1767 | pan_emit_vary_xfb(unsigned present, |
| 1768 | unsigned max_xfb, |
| 1769 | unsigned *streamout_offsets, |
| 1770 | unsigned quirks, |
| 1771 | enum mali_format format, |
| 1772 | struct pipe_stream_output o) |
| 1773 | { |
Alyssa Rosenzweig | 668ec24 | 2020-08-11 22:26:03 -0400 | [diff] [blame] | 1774 | unsigned swizzle = quirks & HAS_SWIZZLES ? |
| 1775 | panfrost_get_default_swizzle(o.num_components) : |
| 1776 | panfrost_bifrost_swizzle(o.num_components); |
| 1777 | |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1778 | /* Otherwise construct a record for it */ |
| 1779 | struct mali_attr_meta meta = { |
| 1780 | /* XFB buffers come after everything else */ |
| 1781 | .index = pan_xfb_base(present) + o.output_buffer, |
| 1782 | |
| 1783 | /* As usual unknown bit */ |
| 1784 | .unknown1 = quirks & IS_BIFROST ? 0x0 : 0x2, |
| 1785 | |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1786 | /* Override number of channels and precision to highp */ |
Alyssa Rosenzweig | 668ec24 | 2020-08-11 22:26:03 -0400 | [diff] [blame] | 1787 | .format = (pan_xfb_format(format, o.num_components) << 12) | swizzle, |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1788 | |
| 1789 | /* Apply given offsets together */ |
| 1790 | .src_offset = (o.dst_offset * 4) /* dwords */ |
| 1791 | + streamout_offsets[o.output_buffer] |
| 1792 | }; |
| 1793 | |
| 1794 | return meta; |
| 1795 | } |
| 1796 | |
Alyssa Rosenzweig | e9e9b2b | 2020-06-10 15:13:12 -0400 | [diff] [blame] | 1797 | /* Determine if we should capture a varying for XFB. This requires actually |
| 1798 | * having a buffer for it. If we don't capture it, we'll fallback to a general |
| 1799 | * varying path (linked or unlinked, possibly discarding the write) */ |
| 1800 | |
| 1801 | static bool |
| 1802 | panfrost_xfb_captured(struct panfrost_shader_state *xfb, |
| 1803 | unsigned loc, unsigned max_xfb) |
| 1804 | { |
| 1805 | if (!(xfb->so_mask & (1ll << loc))) |
| 1806 | return false; |
| 1807 | |
| 1808 | struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); |
| 1809 | return o->output_buffer < max_xfb; |
| 1810 | } |
| 1811 | |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1812 | /* Higher-level wrapper around all of the above, classifying a varying into one |
| 1813 | * of the above types */ |
| 1814 | |
| 1815 | static struct mali_attr_meta |
| 1816 | panfrost_emit_varying( |
| 1817 | struct panfrost_shader_state *stage, |
| 1818 | struct panfrost_shader_state *other, |
| 1819 | struct panfrost_shader_state *xfb, |
| 1820 | unsigned present, |
| 1821 | unsigned max_xfb, |
| 1822 | unsigned *streamout_offsets, |
| 1823 | unsigned quirks, |
| 1824 | unsigned *gen_offsets, |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1825 | enum mali_format *gen_formats, |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1826 | unsigned *gen_stride, |
| 1827 | unsigned idx, |
| 1828 | bool should_alloc, |
| 1829 | bool is_fragment) |
| 1830 | { |
| 1831 | gl_varying_slot loc = stage->varyings_loc[idx]; |
Alyssa Rosenzweig | 3cc425e | 2020-06-10 15:48:33 -0400 | [diff] [blame] | 1832 | enum mali_format format = stage->varyings[idx]; |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1833 | |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1834 | /* Override format to match linkage */ |
| 1835 | if (!should_alloc && gen_formats[idx]) |
| 1836 | format = gen_formats[idx]; |
| 1837 | |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1838 | if (has_point_coord(stage->point_sprite_mask, loc)) { |
| 1839 | return pan_emit_vary_special(present, PAN_VARY_PNTCOORD, quirks); |
| 1840 | } else if (panfrost_xfb_captured(xfb, loc, max_xfb)) { |
| 1841 | struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); |
| 1842 | return pan_emit_vary_xfb(present, max_xfb, streamout_offsets, quirks, format, *o); |
| 1843 | } else if (loc == VARYING_SLOT_POS) { |
| 1844 | if (is_fragment) |
| 1845 | return pan_emit_vary_special(present, PAN_VARY_FRAGCOORD, quirks); |
| 1846 | else |
| 1847 | return pan_emit_vary_special(present, PAN_VARY_POSITION, quirks); |
| 1848 | } else if (loc == VARYING_SLOT_PSIZ) { |
| 1849 | return pan_emit_vary_special(present, PAN_VARY_PSIZ, quirks); |
| 1850 | } else if (loc == VARYING_SLOT_PNTC) { |
| 1851 | return pan_emit_vary_special(present, PAN_VARY_PNTCOORD, quirks); |
| 1852 | } else if (loc == VARYING_SLOT_FACE) { |
| 1853 | return pan_emit_vary_special(present, PAN_VARY_FACE, quirks); |
| 1854 | } |
| 1855 | |
| 1856 | /* We've exhausted special cases, so it's otherwise a general varying. Check if we're linked */ |
| 1857 | signed other_idx = -1; |
| 1858 | |
| 1859 | for (unsigned j = 0; j < other->varying_count; ++j) { |
| 1860 | if (other->varyings_loc[j] == loc) { |
| 1861 | other_idx = j; |
| 1862 | break; |
| 1863 | } |
| 1864 | } |
| 1865 | |
| 1866 | if (other_idx < 0) |
| 1867 | return pan_emit_vary_only(present, quirks); |
| 1868 | |
| 1869 | unsigned offset = gen_offsets[other_idx]; |
| 1870 | |
| 1871 | if (should_alloc) { |
| 1872 | /* We're linked, so allocate a space via a watermark allocation */ |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1873 | enum mali_format alt = other->varyings[other_idx]; |
| 1874 | |
| 1875 | /* Do interpolation at minimum precision */ |
| 1876 | unsigned size_main = pan_varying_size(format); |
| 1877 | unsigned size_alt = pan_varying_size(alt); |
| 1878 | unsigned size = MIN2(size_main, size_alt); |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1879 | |
| 1880 | /* If a varying is marked for XFB but not actually captured, we |
| 1881 | * should match the format to the format that would otherwise |
| 1882 | * be used for XFB, since dEQP checks for invariance here. It's |
| 1883 | * unclear if this is required by the spec. */ |
| 1884 | |
| 1885 | if (xfb->so_mask & (1ull << loc)) { |
| 1886 | struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); |
| 1887 | format = pan_xfb_format(format, o->num_components); |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1888 | size = pan_varying_size(format); |
| 1889 | } else if (size == size_alt) { |
| 1890 | format = alt; |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1891 | } |
| 1892 | |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1893 | gen_offsets[idx] = *gen_stride; |
| 1894 | gen_formats[other_idx] = format; |
| 1895 | offset = *gen_stride; |
| 1896 | *gen_stride += size; |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1897 | } |
| 1898 | |
| 1899 | return pan_emit_vary(present, PAN_VARY_GENERAL, |
| 1900 | quirks, format, offset); |
| 1901 | } |
| 1902 | |
| 1903 | static void |
| 1904 | pan_emit_special_input(union mali_attr *varyings, |
| 1905 | unsigned present, |
| 1906 | enum pan_special_varying v, |
| 1907 | mali_ptr addr) |
| 1908 | { |
| 1909 | if (present & (1 << v)) { |
| 1910 | /* Ensure we write exactly once for performance and with fields |
| 1911 | * zeroed appropriately to avoid flakes */ |
| 1912 | |
| 1913 | union mali_attr s = { |
| 1914 | .elements = addr |
| 1915 | }; |
| 1916 | |
| 1917 | varyings[pan_varying_index(present, v)] = s; |
| 1918 | } |
| 1919 | } |
| 1920 | |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1921 | void |
| 1922 | panfrost_emit_varying_descriptor(struct panfrost_batch *batch, |
| 1923 | unsigned vertex_count, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 1924 | struct mali_vertex_tiler_postfix *vertex_postfix, |
| 1925 | struct mali_vertex_tiler_postfix *tiler_postfix, |
| 1926 | union midgard_primitive_size *primitive_size) |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1927 | { |
| 1928 | /* Load the shaders */ |
| 1929 | struct panfrost_context *ctx = batch->ctx; |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1930 | struct panfrost_device *dev = pan_device(ctx->base.screen); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1931 | struct panfrost_shader_state *vs, *fs; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1932 | size_t vs_size, fs_size; |
| 1933 | |
| 1934 | /* Allocate the varying descriptor */ |
| 1935 | |
| 1936 | vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX); |
| 1937 | fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); |
| 1938 | vs_size = sizeof(struct mali_attr_meta) * vs->varying_count; |
| 1939 | fs_size = sizeof(struct mali_attr_meta) * fs->varying_count; |
| 1940 | |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 1941 | struct panfrost_transfer trans = panfrost_pool_alloc(&batch->pool, |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1942 | vs_size + |
| 1943 | fs_size); |
| 1944 | |
| 1945 | struct pipe_stream_output_info *so = &vs->stream_output; |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1946 | unsigned present = pan_varying_present(vs, fs, dev->quirks); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1947 | |
| 1948 | /* Check if this varying is linked by us. This is the case for |
| 1949 | * general-purpose, non-captured varyings. If it is, link it. If it's |
| 1950 | * not, use the provided stream out information to determine the |
| 1951 | * offset, since it was already linked for us. */ |
| 1952 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1953 | unsigned gen_offsets[32]; |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1954 | enum mali_format gen_formats[32]; |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1955 | memset(gen_offsets, 0, sizeof(gen_offsets)); |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1956 | memset(gen_formats, 0, sizeof(gen_formats)); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1957 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1958 | unsigned gen_stride = 0; |
| 1959 | assert(vs->varying_count < ARRAY_SIZE(gen_offsets)); |
| 1960 | assert(fs->varying_count < ARRAY_SIZE(gen_offsets)); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1961 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1962 | unsigned streamout_offsets[32]; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1963 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1964 | for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) { |
| 1965 | streamout_offsets[i] = panfrost_streamout_offset( |
| 1966 | so->stride[i], |
| 1967 | ctx->streamout.offsets[i], |
| 1968 | ctx->streamout.targets[i]); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1969 | } |
| 1970 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1971 | struct mali_attr_meta *ovs = (struct mali_attr_meta *)trans.cpu; |
| 1972 | struct mali_attr_meta *ofs = ovs + vs->varying_count; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1973 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1974 | for (unsigned i = 0; i < vs->varying_count; i++) { |
| 1975 | ovs[i] = panfrost_emit_varying(vs, fs, vs, present, |
| 1976 | ctx->streamout.num_targets, streamout_offsets, |
| 1977 | dev->quirks, |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1978 | gen_offsets, gen_formats, &gen_stride, i, true, false); |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1979 | } |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1980 | |
| 1981 | for (unsigned i = 0; i < fs->varying_count; i++) { |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1982 | ofs[i] = panfrost_emit_varying(fs, vs, vs, present, |
| 1983 | ctx->streamout.num_targets, streamout_offsets, |
| 1984 | dev->quirks, |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1985 | gen_offsets, gen_formats, &gen_stride, i, false, true); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1986 | } |
| 1987 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1988 | unsigned xfb_base = pan_xfb_base(present); |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 1989 | struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1990 | sizeof(union mali_attr) * (xfb_base + ctx->streamout.num_targets)); |
| 1991 | union mali_attr *varyings = (union mali_attr *) T.cpu; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1992 | |
| 1993 | /* Emit the stream out buffers */ |
| 1994 | |
| 1995 | unsigned out_count = u_stream_outputs_for_vertices(ctx->active_prim, |
| 1996 | ctx->vertex_count); |
| 1997 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1998 | for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) { |
| 1999 | panfrost_emit_streamout(batch, &varyings[xfb_base + i], |
| 2000 | so->stride[i], |
| 2001 | ctx->streamout.offsets[i], |
| 2002 | out_count, |
| 2003 | ctx->streamout.targets[i]); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 2004 | } |
| 2005 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 2006 | panfrost_emit_varyings(batch, |
| 2007 | &varyings[pan_varying_index(present, PAN_VARY_GENERAL)], |
| 2008 | gen_stride, vertex_count); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 2009 | |
| 2010 | /* fp32 vec4 gl_Position */ |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 2011 | tiler_postfix->position_varying = panfrost_emit_varyings(batch, |
| 2012 | &varyings[pan_varying_index(present, PAN_VARY_POSITION)], |
| 2013 | sizeof(float) * 4, vertex_count); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 2014 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 2015 | if (present & (1 << PAN_VARY_PSIZ)) { |
| 2016 | primitive_size->pointer = panfrost_emit_varyings(batch, |
| 2017 | &varyings[pan_varying_index(present, PAN_VARY_PSIZ)], |
| 2018 | 2, vertex_count); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 2019 | } |
| 2020 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 2021 | pan_emit_special_input(varyings, present, PAN_VARY_PNTCOORD, MALI_VARYING_POINT_COORD); |
| 2022 | pan_emit_special_input(varyings, present, PAN_VARY_FACE, MALI_VARYING_FRONT_FACING); |
| 2023 | pan_emit_special_input(varyings, present, PAN_VARY_FRAGCOORD, MALI_VARYING_FRAG_COORD); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 2024 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 2025 | vertex_postfix->varyings = T.gpu; |
| 2026 | tiler_postfix->varyings = T.gpu; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 2027 | |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 2028 | vertex_postfix->varying_meta = trans.gpu; |
| 2029 | tiler_postfix->varying_meta = trans.gpu + vs_size; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 2030 | } |
| 2031 | |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 2032 | void |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 2033 | panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 2034 | struct mali_vertex_tiler_prefix *vertex_prefix, |
| 2035 | struct mali_vertex_tiler_postfix *vertex_postfix, |
| 2036 | struct mali_vertex_tiler_prefix *tiler_prefix, |
| 2037 | struct mali_vertex_tiler_postfix *tiler_postfix, |
| 2038 | union midgard_primitive_size *primitive_size) |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 2039 | { |
| 2040 | struct panfrost_context *ctx = batch->ctx; |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 2041 | struct panfrost_device *device = pan_device(ctx->base.screen); |
Alyssa Rosenzweig | 31197c2 | 2020-07-07 17:07:34 -0400 | [diff] [blame] | 2042 | bool wallpapering = ctx->wallpaper_batch && batch->scoreboard.tiler_dep; |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 2043 | struct bifrost_payload_vertex bifrost_vertex = {0,}; |
| 2044 | struct bifrost_payload_tiler bifrost_tiler = {0,}; |
| 2045 | struct midgard_payload_vertex_tiler midgard_vertex = {0,}; |
| 2046 | struct midgard_payload_vertex_tiler midgard_tiler = {0,}; |
| 2047 | void *vp, *tp; |
| 2048 | size_t vp_size, tp_size; |
| 2049 | |
| 2050 | if (device->quirks & IS_BIFROST) { |
| 2051 | bifrost_vertex.prefix = *vertex_prefix; |
| 2052 | bifrost_vertex.postfix = *vertex_postfix; |
| 2053 | vp = &bifrost_vertex; |
| 2054 | vp_size = sizeof(bifrost_vertex); |
| 2055 | |
| 2056 | bifrost_tiler.prefix = *tiler_prefix; |
| 2057 | bifrost_tiler.tiler.primitive_size = *primitive_size; |
Tomeu Vizoso | 46e4246 | 2020-04-08 15:58:42 +0200 | [diff] [blame] | 2058 | bifrost_tiler.tiler.tiler_meta = panfrost_batch_get_tiler_meta(batch, ~0); |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 2059 | bifrost_tiler.postfix = *tiler_postfix; |
| 2060 | tp = &bifrost_tiler; |
| 2061 | tp_size = sizeof(bifrost_tiler); |
| 2062 | } else { |
| 2063 | midgard_vertex.prefix = *vertex_prefix; |
| 2064 | midgard_vertex.postfix = *vertex_postfix; |
| 2065 | vp = &midgard_vertex; |
| 2066 | vp_size = sizeof(midgard_vertex); |
| 2067 | |
| 2068 | midgard_tiler.prefix = *tiler_prefix; |
| 2069 | midgard_tiler.postfix = *tiler_postfix; |
| 2070 | midgard_tiler.primitive_size = *primitive_size; |
| 2071 | tp = &midgard_tiler; |
| 2072 | tp_size = sizeof(midgard_tiler); |
| 2073 | } |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 2074 | |
| 2075 | if (wallpapering) { |
| 2076 | /* Inject in reverse order, with "predicted" job indices. |
| 2077 | * THIS IS A HACK XXX */ |
Alyssa Rosenzweig | 4b7056b | 2020-08-05 18:40:44 -0400 | [diff] [blame] | 2078 | panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false, |
Alyssa Rosenzweig | 31197c2 | 2020-07-07 17:07:34 -0400 | [diff] [blame] | 2079 | batch->scoreboard.job_index + 2, tp, tp_size, true); |
Alyssa Rosenzweig | 4b7056b | 2020-08-05 18:40:44 -0400 | [diff] [blame] | 2080 | panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 2081 | vp, vp_size, true); |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 2082 | return; |
| 2083 | } |
| 2084 | |
| 2085 | /* If rasterizer discard is enable, only submit the vertex */ |
| 2086 | |
| 2087 | bool rasterizer_discard = ctx->rasterizer && |
| 2088 | ctx->rasterizer->base.rasterizer_discard; |
| 2089 | |
Alyssa Rosenzweig | 4b7056b | 2020-08-05 18:40:44 -0400 | [diff] [blame] | 2090 | unsigned vertex = panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0, |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 2091 | vp, vp_size, false); |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 2092 | |
| 2093 | if (rasterizer_discard) |
| 2094 | return; |
| 2095 | |
Alyssa Rosenzweig | 4b7056b | 2020-08-05 18:40:44 -0400 | [diff] [blame] | 2096 | panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false, vertex, tp, tp_size, |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 2097 | false); |
| 2098 | } |
Alyssa Rosenzweig | 0a9fa4b | 2020-04-06 19:44:58 -0400 | [diff] [blame] | 2099 | |
| 2100 | /* TODO: stop hardcoding this */ |
| 2101 | mali_ptr |
| 2102 | panfrost_emit_sample_locations(struct panfrost_batch *batch) |
| 2103 | { |
| 2104 | uint16_t locations[] = { |
| 2105 | 128, 128, |
| 2106 | 0, 256, |
| 2107 | 0, 256, |
| 2108 | 0, 256, |
| 2109 | 0, 256, |
| 2110 | 0, 256, |
| 2111 | 0, 256, |
| 2112 | 0, 256, |
| 2113 | 0, 256, |
| 2114 | 0, 256, |
| 2115 | 0, 256, |
| 2116 | 0, 256, |
| 2117 | 0, 256, |
| 2118 | 0, 256, |
| 2119 | 0, 256, |
| 2120 | 0, 256, |
| 2121 | 0, 256, |
| 2122 | 0, 256, |
| 2123 | 0, 256, |
| 2124 | 0, 256, |
| 2125 | 0, 256, |
| 2126 | 0, 256, |
| 2127 | 0, 256, |
| 2128 | 0, 256, |
| 2129 | 0, 256, |
| 2130 | 0, 256, |
| 2131 | 0, 256, |
| 2132 | 0, 256, |
| 2133 | 0, 256, |
| 2134 | 0, 256, |
| 2135 | 0, 256, |
| 2136 | 0, 256, |
| 2137 | 128, 128, |
| 2138 | 0, 0, |
| 2139 | 0, 0, |
| 2140 | 0, 0, |
| 2141 | 0, 0, |
| 2142 | 0, 0, |
| 2143 | 0, 0, |
| 2144 | 0, 0, |
| 2145 | 0, 0, |
| 2146 | 0, 0, |
| 2147 | 0, 0, |
| 2148 | 0, 0, |
| 2149 | 0, 0, |
| 2150 | 0, 0, |
| 2151 | 0, 0, |
| 2152 | 0, 0, |
| 2153 | }; |
| 2154 | |
Alyssa Rosenzweig | 8958fbd | 2020-07-07 15:20:35 -0400 | [diff] [blame] | 2155 | return panfrost_pool_upload(&batch->pool, locations, 96 * sizeof(uint16_t)); |
Alyssa Rosenzweig | 0a9fa4b | 2020-04-06 19:44:58 -0400 | [diff] [blame] | 2156 | } |