Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Alyssa Rosenzweig |
| 3 | * Copyright (C) 2020 Collabora Ltd. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | |
Boris Brezillon | 0d75eb0 | 2020-03-06 09:59:56 +0100 | [diff] [blame] | 25 | #include "util/macros.h" |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 26 | #include "util/u_prim.h" |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 27 | #include "util/u_vbuf.h" |
Alyssa Rosenzweig | b17b6cc | 2020-08-26 11:22:47 -0400 | [diff] [blame] | 28 | #include "util/u_helpers.h" |
Boris Brezillon | 0d75eb0 | 2020-03-06 09:59:56 +0100 | [diff] [blame] | 29 | |
| 30 | #include "panfrost-quirks.h" |
| 31 | |
Alyssa Rosenzweig | c8d848b | 2020-07-07 16:24:41 -0400 | [diff] [blame] | 32 | #include "pan_pool.h" |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 33 | #include "pan_bo.h" |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 34 | #include "pan_cmdstream.h" |
| 35 | #include "pan_context.h" |
| 36 | #include "pan_job.h" |
| 37 | |
Alyssa Rosenzweig | 02a638c | 2020-03-23 19:10:06 -0400 | [diff] [blame] | 38 | /* If a BO is accessed for a particular shader stage, will it be in the primary |
| 39 | * batch (vertex/tiler) or the secondary batch (fragment)? Anything but |
| 40 | * fragment will be primary, e.g. compute jobs will be considered |
| 41 | * "vertex/tiler" by analogy */ |
| 42 | |
| 43 | static inline uint32_t |
| 44 | panfrost_bo_access_for_stage(enum pipe_shader_type stage) |
| 45 | { |
| 46 | assert(stage == PIPE_SHADER_FRAGMENT || |
| 47 | stage == PIPE_SHADER_VERTEX || |
| 48 | stage == PIPE_SHADER_COMPUTE); |
| 49 | |
| 50 | return stage == PIPE_SHADER_FRAGMENT ? |
| 51 | PAN_BO_ACCESS_FRAGMENT : |
| 52 | PAN_BO_ACCESS_VERTEX_TILER; |
| 53 | } |
| 54 | |
Alyssa Rosenzweig | 136fd5c | 2020-08-25 12:52:45 -0400 | [diff] [blame] | 55 | mali_ptr |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 56 | panfrost_vt_emit_shared_memory(struct panfrost_batch *batch) |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 57 | { |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 58 | struct panfrost_device *dev = pan_device(batch->ctx->base.screen); |
Tomeu Vizoso | 7b10d4e | 2020-04-08 10:55:28 +0200 | [diff] [blame] | 59 | |
Boris Brezillon | 3a06fc3 | 2020-09-03 09:18:09 +0200 | [diff] [blame] | 60 | struct panfrost_transfer t = |
| 61 | panfrost_pool_alloc_aligned(&batch->pool, |
| 62 | MALI_LOCAL_STORAGE_LENGTH, |
| 63 | 64); |
Alyssa Rosenzweig | b41692c | 2020-08-17 12:30:49 -0400 | [diff] [blame] | 64 | |
Boris Brezillon | 3a06fc3 | 2020-09-03 09:18:09 +0200 | [diff] [blame] | 65 | pan_pack(t.cpu, LOCAL_STORAGE, ls) { |
| 66 | ls.wls_instances = MALI_LOCAL_STORAGE_NO_WORKGROUP_MEM; |
| 67 | if (batch->stack_size) { |
| 68 | struct panfrost_bo *stack = |
| 69 | panfrost_batch_get_scratchpad(batch, batch->stack_size, |
| 70 | dev->thread_tls_alloc, |
| 71 | dev->core_count); |
Alyssa Rosenzweig | b41692c | 2020-08-17 12:30:49 -0400 | [diff] [blame] | 72 | |
Boris Brezillon | 3a06fc3 | 2020-09-03 09:18:09 +0200 | [diff] [blame] | 73 | ls.tls_size = panfrost_get_stack_shift(batch->stack_size); |
| 74 | ls.tls_base_pointer = stack->gpu; |
| 75 | } |
Alyssa Rosenzweig | b41692c | 2020-08-17 12:30:49 -0400 | [diff] [blame] | 76 | } |
| 77 | |
Boris Brezillon | 3a06fc3 | 2020-09-03 09:18:09 +0200 | [diff] [blame] | 78 | return t.gpu; |
Boris Brezillon | 0d75eb0 | 2020-03-06 09:59:56 +0100 | [diff] [blame] | 79 | } |
| 80 | |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 81 | /* Gets a GPU address for the associated index buffer. Only gauranteed to be |
| 82 | * good for the duration of the draw (transient), could last longer. Also get |
| 83 | * the bounds on the index buffer for the range accessed by the draw. We do |
| 84 | * these operations together because there are natural optimizations which |
| 85 | * require them to be together. */ |
| 86 | |
Alyssa Rosenzweig | 3a4d930 | 2020-08-25 13:25:29 -0400 | [diff] [blame] | 87 | mali_ptr |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 88 | panfrost_get_index_buffer_bounded(struct panfrost_context *ctx, |
| 89 | const struct pipe_draw_info *info, |
| 90 | unsigned *min_index, unsigned *max_index) |
| 91 | { |
| 92 | struct panfrost_resource *rsrc = pan_resource(info->index.resource); |
| 93 | struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); |
| 94 | off_t offset = info->start * info->index_size; |
| 95 | bool needs_indices = true; |
| 96 | mali_ptr out = 0; |
| 97 | |
| 98 | if (info->max_index != ~0u) { |
| 99 | *min_index = info->min_index; |
| 100 | *max_index = info->max_index; |
| 101 | needs_indices = false; |
| 102 | } |
| 103 | |
| 104 | if (!info->has_user_indices) { |
| 105 | /* Only resources can be directly mapped */ |
| 106 | panfrost_batch_add_bo(batch, rsrc->bo, |
| 107 | PAN_BO_ACCESS_SHARED | |
| 108 | PAN_BO_ACCESS_READ | |
| 109 | PAN_BO_ACCESS_VERTEX_TILER); |
| 110 | out = rsrc->bo->gpu + offset; |
| 111 | |
| 112 | /* Check the cache */ |
| 113 | needs_indices = !panfrost_minmax_cache_get(rsrc->index_cache, |
| 114 | info->start, |
| 115 | info->count, |
| 116 | min_index, |
| 117 | max_index); |
| 118 | } else { |
| 119 | /* Otherwise, we need to upload to transient memory */ |
| 120 | const uint8_t *ibuf8 = (const uint8_t *) info->index.user; |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 121 | struct panfrost_transfer T = |
| 122 | panfrost_pool_alloc_aligned(&batch->pool, |
| 123 | info->count * info->index_size, |
| 124 | info->index_size); |
| 125 | |
| 126 | memcpy(T.cpu, ibuf8 + offset, info->count * info->index_size); |
| 127 | out = T.gpu; |
Boris Brezillon | 5d9995e | 2020-03-06 08:02:14 +0100 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | if (needs_indices) { |
| 131 | /* Fallback */ |
| 132 | u_vbuf_get_minmax_index(&ctx->base, info, min_index, max_index); |
| 133 | |
| 134 | if (!info->has_user_indices) |
| 135 | panfrost_minmax_cache_add(rsrc->index_cache, |
| 136 | info->start, info->count, |
| 137 | *min_index, *max_index); |
| 138 | } |
| 139 | |
| 140 | return out; |
| 141 | } |
| 142 | |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 143 | static unsigned |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 144 | translate_tex_wrap(enum pipe_tex_wrap w) |
| 145 | { |
| 146 | switch (w) { |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 147 | case PIPE_TEX_WRAP_REPEAT: return MALI_WRAP_MODE_REPEAT; |
| 148 | case PIPE_TEX_WRAP_CLAMP: return MALI_WRAP_MODE_CLAMP; |
| 149 | case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return MALI_WRAP_MODE_CLAMP_TO_EDGE; |
| 150 | case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return MALI_WRAP_MODE_CLAMP_TO_BORDER; |
| 151 | case PIPE_TEX_WRAP_MIRROR_REPEAT: return MALI_WRAP_MODE_MIRRORED_REPEAT; |
| 152 | case PIPE_TEX_WRAP_MIRROR_CLAMP: return MALI_WRAP_MODE_MIRRORED_CLAMP; |
| 153 | case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE; |
| 154 | case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER; |
| 155 | default: unreachable("Invalid wrap"); |
| 156 | } |
| 157 | } |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 158 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 159 | /* The hardware compares in the wrong order order, so we have to flip before |
| 160 | * encoding. Yes, really. */ |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 161 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 162 | static enum mali_func |
| 163 | panfrost_sampler_compare_func(const struct pipe_sampler_state *cso) |
| 164 | { |
| 165 | if (!cso->compare_mode) |
| 166 | return MALI_FUNC_NEVER; |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 167 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 168 | enum mali_func f = panfrost_translate_compare_func(cso->compare_func); |
| 169 | return panfrost_flip_compare_func(f); |
| 170 | } |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 171 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 172 | static enum mali_mipmap_mode |
| 173 | pan_pipe_to_mipmode(enum pipe_tex_mipfilter f) |
| 174 | { |
| 175 | switch (f) { |
| 176 | case PIPE_TEX_MIPFILTER_NEAREST: return MALI_MIPMAP_MODE_NEAREST; |
| 177 | case PIPE_TEX_MIPFILTER_LINEAR: return MALI_MIPMAP_MODE_TRILINEAR; |
| 178 | case PIPE_TEX_MIPFILTER_NONE: return MALI_MIPMAP_MODE_NONE; |
| 179 | default: unreachable("Invalid"); |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 180 | } |
| 181 | } |
| 182 | |
| 183 | void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso, |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 184 | struct mali_midgard_sampler_packed *hw) |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 185 | { |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 186 | pan_pack(hw, MIDGARD_SAMPLER, cfg) { |
| 187 | cfg.magnify_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST; |
| 188 | cfg.minify_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST; |
| 189 | cfg.mipmap_mode = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR) ? |
| 190 | MALI_MIPMAP_MODE_TRILINEAR : MALI_MIPMAP_MODE_NEAREST; |
| 191 | cfg.normalized_coordinates = cso->normalized_coords; |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 192 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 193 | cfg.lod_bias = FIXED_16(cso->lod_bias, true); |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 194 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 195 | cfg.minimum_lod = FIXED_16(cso->min_lod, false); |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 196 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 197 | /* If necessary, we disable mipmapping in the sampler descriptor by |
| 198 | * clamping the LOD as tight as possible (from 0 to epsilon, |
| 199 | * essentially -- remember these are fixed point numbers, so |
| 200 | * epsilon=1/256) */ |
| 201 | |
| 202 | cfg.maximum_lod = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) ? |
| 203 | cfg.minimum_lod + 1 : |
| 204 | FIXED_16(cso->max_lod, false); |
| 205 | |
| 206 | cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s); |
| 207 | cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t); |
| 208 | cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r); |
| 209 | |
| 210 | cfg.compare_function = panfrost_sampler_compare_func(cso); |
| 211 | cfg.seamless_cube_map = cso->seamless_cube_map; |
| 212 | |
| 213 | cfg.border_color_r = cso->border_color.f[0]; |
Icecream95 | 8557b1a | 2020-08-13 19:35:00 +1200 | [diff] [blame] | 214 | cfg.border_color_g = cso->border_color.f[1]; |
| 215 | cfg.border_color_b = cso->border_color.f[2]; |
| 216 | cfg.border_color_a = cso->border_color.f[3]; |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 217 | } |
Boris Brezillon | 2b946a1 | 2020-03-05 16:26:56 +0100 | [diff] [blame] | 218 | } |
| 219 | |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 220 | void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso, |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 221 | struct mali_bifrost_sampler_packed *hw) |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 222 | { |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 223 | pan_pack(hw, BIFROST_SAMPLER, cfg) { |
Alyssa Rosenzweig | 3943bce | 2020-10-06 21:31:18 -0400 | [diff] [blame] | 224 | cfg.point_sample_magnify = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST; |
| 225 | cfg.point_sample_minify = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST; |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 226 | cfg.mipmap_mode = pan_pipe_to_mipmode(cso->min_mip_filter); |
| 227 | cfg.normalized_coordinates = cso->normalized_coords; |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 228 | |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 229 | cfg.lod_bias = FIXED_16(cso->lod_bias, true); |
| 230 | cfg.minimum_lod = FIXED_16(cso->min_lod, false); |
| 231 | cfg.maximum_lod = FIXED_16(cso->max_lod, false); |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 232 | |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 233 | cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s); |
| 234 | cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t); |
| 235 | cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r); |
| 236 | |
| 237 | cfg.compare_function = panfrost_sampler_compare_func(cso); |
| 238 | cfg.seamless_cube_map = cso->seamless_cube_map; |
| 239 | } |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 240 | } |
| 241 | |
Alyssa Rosenzweig | 1085f74 | 2020-05-21 15:49:30 -0400 | [diff] [blame] | 242 | static bool |
| 243 | panfrost_fs_required( |
| 244 | struct panfrost_shader_state *fs, |
| 245 | struct panfrost_blend_final *blend, |
| 246 | unsigned rt_count) |
| 247 | { |
| 248 | /* If we generally have side effects */ |
| 249 | if (fs->fs_sidefx) |
| 250 | return true; |
| 251 | |
| 252 | /* If colour is written we need to execute */ |
| 253 | for (unsigned i = 0; i < rt_count; ++i) { |
| 254 | if (!blend[i].no_colour) |
| 255 | return true; |
| 256 | } |
| 257 | |
| 258 | /* If depth is written and not implied we need to execute. |
| 259 | * TODO: Predicate on Z/S writes being enabled */ |
| 260 | return (fs->writes_depth || fs->writes_stencil); |
| 261 | } |
| 262 | |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 263 | static void |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 264 | panfrost_emit_bifrost_blend(struct panfrost_batch *batch, |
| 265 | struct panfrost_blend_final *blend, |
| 266 | void *rts) |
Alyssa Rosenzweig | bbec4ff | 2020-08-18 16:50:38 -0400 | [diff] [blame] | 267 | { |
Alyssa Rosenzweig | bbec4ff | 2020-08-18 16:50:38 -0400 | [diff] [blame] | 268 | unsigned rt_count = batch->key.nr_cbufs; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 269 | |
Alyssa Rosenzweig | 87e3510 | 2020-08-26 09:44:12 -0400 | [diff] [blame] | 270 | if (rt_count == 0) { |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 271 | /* Disable blending for depth-only */ |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 272 | pan_pack(rts, BLEND, cfg) { |
| 273 | cfg.enable = false; |
Boris Brezillon | 8d707cd | 2020-10-12 14:16:53 +0200 | [diff] [blame] | 274 | cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OFF; |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 275 | } |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 276 | return; |
Alyssa Rosenzweig | 87e3510 | 2020-08-26 09:44:12 -0400 | [diff] [blame] | 277 | } |
Alyssa Rosenzweig | 8249e2b | 2020-08-17 19:41:48 -0400 | [diff] [blame] | 278 | |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 279 | const struct panfrost_device *dev = pan_device(batch->ctx->base.screen); |
| 280 | struct panfrost_shader_state *fs = panfrost_get_shader_state(batch->ctx, PIPE_SHADER_FRAGMENT); |
| 281 | |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 282 | for (unsigned i = 0; i < rt_count; ++i) { |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 283 | pan_pack(rts + i * MALI_BLEND_LENGTH, BLEND, cfg) { |
Alyssa Rosenzweig | 6beac11 | 2020-08-18 17:51:22 -0400 | [diff] [blame] | 284 | if (blend[i].no_colour) { |
| 285 | cfg.enable = false; |
Alyssa Rosenzweig | 8249e2b | 2020-08-17 19:41:48 -0400 | [diff] [blame] | 286 | } else { |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 287 | cfg.srgb = util_format_is_srgb(batch->key.cbufs[i]->format); |
| 288 | cfg.load_destination = blend[i].load_dest; |
| 289 | cfg.round_to_fb_precision = !batch->ctx->blend->base.dither; |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 290 | } |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 291 | |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 292 | if (blend[i].is_shader) { |
| 293 | /* The blend shader's address needs to be at |
| 294 | * the same top 32 bit as the fragment shader. |
| 295 | * TODO: Ensure that's always the case. |
| 296 | */ |
| 297 | assert((blend[i].shader.gpu & (0xffffffffull << 32)) == |
| 298 | (fs->bo->gpu & (0xffffffffull << 32))); |
Boris Brezillon | 8d707cd | 2020-10-12 14:16:53 +0200 | [diff] [blame] | 299 | cfg.bifrost.internal.shader.pc = (u32)blend[i].shader.gpu; |
Boris Brezillon | 91d9c55 | 2020-10-12 15:18:35 +0200 | [diff] [blame] | 300 | assert(!(fs->blend_ret_addrs[i] & 0x7)); |
| 301 | cfg.bifrost.internal.shader.return_value = fs->blend_ret_addrs[i]; |
Boris Brezillon | 8d707cd | 2020-10-12 14:16:53 +0200 | [diff] [blame] | 302 | cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_SHADER; |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 303 | } else { |
| 304 | enum pipe_format format = batch->key.cbufs[i]->format; |
| 305 | const struct util_format_description *format_desc; |
| 306 | unsigned chan_size = 0; |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 307 | |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 308 | format_desc = util_format_description(format); |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 309 | |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 310 | for (unsigned i = 0; i < format_desc->nr_channels; i++) |
| 311 | chan_size = MAX2(format_desc->channel[0].size, chan_size); |
| 312 | |
| 313 | cfg.bifrost.equation = blend[i].equation.equation; |
| 314 | |
| 315 | /* Fixed point constant */ |
Boris Brezillon | d8326ce | 2020-10-09 14:00:28 +0200 | [diff] [blame] | 316 | u16 constant = blend[i].equation.constant * ((1 << chan_size) - 1); |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 317 | constant <<= 16 - chan_size; |
| 318 | cfg.bifrost.constant = constant; |
| 319 | |
| 320 | if (blend[i].opaque) |
Boris Brezillon | 8d707cd | 2020-10-12 14:16:53 +0200 | [diff] [blame] | 321 | cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OPAQUE; |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 322 | else |
Boris Brezillon | 8d707cd | 2020-10-12 14:16:53 +0200 | [diff] [blame] | 323 | cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_FIXED_FUNCTION; |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 324 | |
Boris Brezillon | 8d707cd | 2020-10-12 14:16:53 +0200 | [diff] [blame] | 325 | cfg.bifrost.internal.fixed_function.num_comps = format_desc->nr_channels; |
| 326 | cfg.bifrost.internal.fixed_function.conversion.memory_format.format = |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 327 | panfrost_format_to_bifrost_blend(format_desc); |
| 328 | if (dev->quirks & HAS_SWIZZLES) { |
Boris Brezillon | 8d707cd | 2020-10-12 14:16:53 +0200 | [diff] [blame] | 329 | cfg.bifrost.internal.fixed_function.conversion.memory_format.swizzle = |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 330 | panfrost_get_default_swizzle(4); |
| 331 | } |
Boris Brezillon | 8d707cd | 2020-10-12 14:16:53 +0200 | [diff] [blame] | 332 | cfg.bifrost.internal.fixed_function.conversion.register_format = |
| 333 | fs->blend_types[i]; |
Boris Brezillon | 713419e | 2020-09-16 10:26:06 +0200 | [diff] [blame] | 334 | } |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 335 | } |
| 336 | } |
| 337 | } |
| 338 | |
| 339 | static void |
| 340 | panfrost_emit_midgard_blend(struct panfrost_batch *batch, |
| 341 | struct panfrost_blend_final *blend, |
| 342 | void *rts) |
| 343 | { |
| 344 | unsigned rt_count = batch->key.nr_cbufs; |
| 345 | |
| 346 | if (rt_count == 0) { |
| 347 | /* Disable blending for depth-only */ |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 348 | pan_pack(rts, BLEND, cfg) { |
| 349 | cfg.midgard.equation.color_mask = 0xf; |
| 350 | cfg.midgard.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC; |
| 351 | cfg.midgard.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC; |
| 352 | cfg.midgard.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO; |
| 353 | cfg.midgard.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC; |
| 354 | cfg.midgard.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC; |
| 355 | cfg.midgard.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO; |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 356 | } |
| 357 | return; |
| 358 | } |
| 359 | |
| 360 | for (unsigned i = 0; i < rt_count; ++i) { |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 361 | pan_pack(rts + i * MALI_BLEND_LENGTH, BLEND, cfg) { |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 362 | if (blend[i].no_colour) { |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 363 | cfg.enable = false; |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 364 | continue; |
| 365 | } |
| 366 | |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 367 | cfg.srgb = util_format_is_srgb(batch->key.cbufs[i]->format); |
| 368 | cfg.load_destination = blend[i].load_dest; |
| 369 | cfg.round_to_fb_precision = !batch->ctx->blend->base.dither; |
| 370 | cfg.midgard.blend_shader = blend[i].is_shader; |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 371 | if (blend[i].is_shader) { |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 372 | cfg.midgard.shader_pc = blend[i].shader.gpu | blend[i].shader.first_tag; |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 373 | } else { |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 374 | cfg.midgard.equation = blend[i].equation.equation; |
| 375 | cfg.midgard.constant = blend[i].equation.constant; |
Boris Brezillon | 01121c7 | 2020-09-15 18:07:42 +0200 | [diff] [blame] | 376 | } |
| 377 | } |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | static void |
| 382 | panfrost_emit_blend(struct panfrost_batch *batch, void *rts, |
| 383 | struct panfrost_blend_final *blend) |
| 384 | { |
| 385 | const struct panfrost_device *dev = pan_device(batch->ctx->base.screen); |
| 386 | |
| 387 | if (dev->quirks & IS_BIFROST) |
| 388 | panfrost_emit_bifrost_blend(batch, blend, rts); |
| 389 | else |
| 390 | panfrost_emit_midgard_blend(batch, blend, rts); |
| 391 | |
| 392 | for (unsigned i = 0; i < batch->key.nr_cbufs; ++i) { |
| 393 | if (!blend[i].no_colour) |
| 394 | batch->draws |= (PIPE_CLEAR_COLOR0 << i); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 395 | } |
| 396 | } |
| 397 | |
| 398 | static void |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 399 | panfrost_prepare_bifrost_fs_state(struct panfrost_context *ctx, |
| 400 | struct panfrost_blend_final *blend, |
| 401 | struct MALI_RENDERER_STATE *state) |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 402 | { |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 403 | struct panfrost_shader_state *fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); |
Alyssa Rosenzweig | 96a9153 | 2020-08-20 15:52:32 -0400 | [diff] [blame] | 404 | unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs; |
Alyssa Rosenzweig | 9a2df30 | 2020-08-19 10:25:32 -0400 | [diff] [blame] | 405 | |
Alyssa Rosenzweig | e0a6af9 | 2020-08-21 13:22:11 -0400 | [diff] [blame] | 406 | if (!panfrost_fs_required(fs, blend, rt_count)) { |
Boris Brezillon | 519643b | 2020-10-13 18:32:14 +0200 | [diff] [blame^] | 407 | state->properties.uniform_buffer_count = 32; |
| 408 | state->properties.bifrost.shader_modifies_coverage = true; |
| 409 | state->properties.bifrost.allow_forward_pixel_to_kill = true; |
| 410 | state->properties.bifrost.allow_forward_pixel_to_be_killed = true; |
| 411 | state->properties.bifrost.zs_update_operation = MALI_PIXEL_KILL_STRONG_EARLY; |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 412 | } else { |
Alyssa Rosenzweig | acf77cb | 2020-08-20 16:41:41 -0400 | [diff] [blame] | 413 | bool no_blend = true; |
| 414 | |
| 415 | for (unsigned i = 0; i < rt_count; ++i) |
| 416 | no_blend &= (!blend[i].load_dest | blend[i].no_colour); |
| 417 | |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 418 | state->properties = fs->properties; |
Boris Brezillon | 519643b | 2020-10-13 18:32:14 +0200 | [diff] [blame^] | 419 | state->properties.bifrost.allow_forward_pixel_to_kill = |
| 420 | !fs->can_discard && !fs->writes_depth && no_blend; |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 421 | state->shader = fs->shader; |
| 422 | state->preload = fs->preload; |
| 423 | } |
| 424 | } |
Alyssa Rosenzweig | acf77cb | 2020-08-20 16:41:41 -0400 | [diff] [blame] | 425 | |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 426 | static void |
| 427 | panfrost_prepare_midgard_fs_state(struct panfrost_context *ctx, |
| 428 | struct panfrost_blend_final *blend, |
| 429 | struct MALI_RENDERER_STATE *state) |
| 430 | { |
| 431 | const struct panfrost_device *dev = pan_device(ctx->base.screen); |
| 432 | struct panfrost_shader_state *fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); |
| 433 | const struct panfrost_zsa_state *zsa = ctx->depth_stencil; |
| 434 | unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs; |
| 435 | bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage; |
| 436 | |
| 437 | if (!panfrost_fs_required(fs, blend, rt_count)) { |
| 438 | state->shader.shader = 0x1; |
Boris Brezillon | 519643b | 2020-10-13 18:32:14 +0200 | [diff] [blame^] | 439 | state->properties.midgard.work_register_count = 1; |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 440 | state->properties.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION; |
Boris Brezillon | 519643b | 2020-10-13 18:32:14 +0200 | [diff] [blame^] | 441 | state->properties.midgard.force_early_z = true; |
Alyssa Rosenzweig | 9a2df30 | 2020-08-19 10:25:32 -0400 | [diff] [blame] | 442 | } else { |
Alyssa Rosenzweig | 19ded1e | 2020-08-20 08:06:39 -0400 | [diff] [blame] | 443 | /* Reasons to disable early-Z from a shader perspective */ |
| 444 | bool late_z = fs->can_discard || fs->writes_global || |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 445 | fs->writes_depth || fs->writes_stencil; |
Alyssa Rosenzweig | 9a2df30 | 2020-08-19 10:25:32 -0400 | [diff] [blame] | 446 | |
Alyssa Rosenzweig | 19ded1e | 2020-08-20 08:06:39 -0400 | [diff] [blame] | 447 | /* If either depth or stencil is enabled, discard matters */ |
| 448 | bool zs_enabled = |
| 449 | (zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) || |
| 450 | zsa->base.stencil[0].enabled; |
| 451 | |
Alyssa Rosenzweig | 96a9153 | 2020-08-20 15:52:32 -0400 | [diff] [blame] | 452 | bool has_blend_shader = false; |
| 453 | |
| 454 | for (unsigned c = 0; c < rt_count; ++c) |
| 455 | has_blend_shader |= blend[c].is_shader; |
| 456 | |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 457 | /* TODO: Reduce this limit? */ |
| 458 | state->properties = fs->properties; |
| 459 | if (has_blend_shader) |
Boris Brezillon | 519643b | 2020-10-13 18:32:14 +0200 | [diff] [blame^] | 460 | state->properties.midgard.work_register_count = MAX2(fs->work_reg_count, 8); |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 461 | else |
Boris Brezillon | 519643b | 2020-10-13 18:32:14 +0200 | [diff] [blame^] | 462 | state->properties.midgard.work_register_count = fs->work_reg_count; |
Alyssa Rosenzweig | 96a9153 | 2020-08-20 15:52:32 -0400 | [diff] [blame] | 463 | |
Boris Brezillon | 519643b | 2020-10-13 18:32:14 +0200 | [diff] [blame^] | 464 | state->properties.midgard.force_early_z = !(late_z || alpha_to_coverage); |
| 465 | |
| 466 | /* Workaround a hardware errata where early-z cannot be enabled |
| 467 | * when discarding even when the depth buffer is read-only, by |
| 468 | * lying to the hardware about the discard and setting the |
| 469 | * reads tilebuffer? flag to compensate */ |
| 470 | state->properties.midgard.shader_reads_tilebuffer = |
| 471 | fs->outputs_read || (!zs_enabled && fs->can_discard); |
| 472 | state->properties.midgard.shader_contains_discard = zs_enabled && fs->can_discard; |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 473 | state->shader = fs->shader; |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 474 | } |
| 475 | |
| 476 | if (dev->quirks & MIDGARD_SFBD) { |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 477 | state->multisample_misc.sfbd_load_destination = blend[0].load_dest; |
| 478 | state->multisample_misc.sfbd_blend_shader = blend[0].is_shader; |
| 479 | state->stencil_mask_misc.sfbd_write_enable = !blend[0].no_colour; |
| 480 | state->stencil_mask_misc.sfbd_srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format); |
| 481 | state->stencil_mask_misc.sfbd_dither_disable = !ctx->blend->base.dither; |
| 482 | |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 483 | if (blend[0].is_shader) { |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 484 | state->sfbd_blend_shader = blend[0].shader.gpu | |
| 485 | blend[0].shader.first_tag; |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 486 | } else { |
Boris Brezillon | 713419e | 2020-09-16 10:26:06 +0200 | [diff] [blame] | 487 | state->sfbd_blend_equation = blend[0].equation.equation; |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 488 | state->sfbd_blend_constant = blend[0].equation.constant; |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 489 | } |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 490 | } else { |
Alyssa Rosenzweig | 58ae50f | 2020-08-19 15:50:25 -0400 | [diff] [blame] | 491 | /* Bug where MRT-capable hw apparently reads the last blend |
| 492 | * shader from here instead of the usual location? */ |
| 493 | |
| 494 | for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) { |
| 495 | if (!blend[rt].is_shader) |
| 496 | continue; |
| 497 | |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 498 | state->sfbd_blend_shader = blend[rt].shader.gpu | |
| 499 | blend[rt].shader.first_tag; |
Alyssa Rosenzweig | 58ae50f | 2020-08-19 15:50:25 -0400 | [diff] [blame] | 500 | break; |
| 501 | } |
Alyssa Rosenzweig | e5689a5 | 2020-08-19 09:27:42 -0400 | [diff] [blame] | 502 | } |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 503 | } |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 504 | |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 505 | static void |
| 506 | panfrost_prepare_fs_state(struct panfrost_context *ctx, |
| 507 | struct panfrost_blend_final *blend, |
| 508 | struct MALI_RENDERER_STATE *state) |
| 509 | { |
| 510 | const struct panfrost_device *dev = pan_device(ctx->base.screen); |
| 511 | struct panfrost_shader_state *fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); |
| 512 | struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; |
| 513 | const struct panfrost_zsa_state *zsa = ctx->depth_stencil; |
| 514 | bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage; |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 515 | |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 516 | if (dev->quirks & IS_BIFROST) |
| 517 | panfrost_prepare_bifrost_fs_state(ctx, blend, state); |
| 518 | else |
| 519 | panfrost_prepare_midgard_fs_state(ctx, blend, state); |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 520 | |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 521 | bool msaa = rast->multisample; |
| 522 | state->multisample_misc.multisample_enable = msaa; |
| 523 | state->multisample_misc.sample_mask = (msaa ? ctx->sample_mask : ~0) & 0xFFFF; |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 524 | |
Boris Brezillon | 7bb85ea | 2020-09-15 17:03:28 +0200 | [diff] [blame] | 525 | /* EXT_shader_framebuffer_fetch requires per-sample */ |
| 526 | bool per_sample = ctx->min_samples > 1 || fs->outputs_read; |
| 527 | state->multisample_misc.evaluate_per_sample = msaa && per_sample; |
| 528 | state->multisample_misc.depth_function = zsa->base.depth.enabled ? |
| 529 | panfrost_translate_compare_func(zsa->base.depth.func) : |
| 530 | MALI_FUNC_ALWAYS; |
| 531 | |
| 532 | state->multisample_misc.depth_write_mask = zsa->base.depth.writemask; |
| 533 | state->multisample_misc.fixed_function_near_discard = rast->depth_clip_near; |
| 534 | state->multisample_misc.fixed_function_far_discard = rast->depth_clip_far; |
| 535 | state->multisample_misc.unknown_2 = true; |
| 536 | |
| 537 | state->stencil_mask_misc.stencil_mask_front = zsa->stencil_mask_front; |
| 538 | state->stencil_mask_misc.stencil_mask_back = zsa->stencil_mask_back; |
| 539 | state->stencil_mask_misc.stencil_enable = zsa->base.stencil[0].enabled; |
| 540 | state->stencil_mask_misc.alpha_to_coverage = alpha_to_coverage; |
| 541 | state->stencil_mask_misc.unknown_1 = 0x7; |
| 542 | state->stencil_mask_misc.depth_range_1 = rast->offset_tri; |
| 543 | state->stencil_mask_misc.depth_range_2 = rast->offset_tri; |
| 544 | state->stencil_mask_misc.single_sampled_lines = !rast->multisample; |
| 545 | state->depth_units = rast->offset_units * 2.0f; |
| 546 | state->depth_factor = rast->offset_scale; |
| 547 | |
| 548 | bool back_enab = zsa->base.stencil[1].enabled; |
| 549 | state->stencil_front = zsa->stencil_front; |
| 550 | state->stencil_back = zsa->stencil_back; |
| 551 | state->stencil_front.reference_value = ctx->stencil_ref.ref_value[0]; |
| 552 | state->stencil_back.reference_value = ctx->stencil_ref.ref_value[back_enab ? 1 : 0]; |
| 553 | } |
| 554 | |
| 555 | |
| 556 | static void |
| 557 | panfrost_emit_frag_shader(struct panfrost_context *ctx, |
| 558 | struct mali_renderer_state_packed *fragmeta, |
| 559 | struct panfrost_blend_final *blend) |
| 560 | { |
| 561 | pan_pack(fragmeta, RENDERER_STATE, cfg) { |
| 562 | panfrost_prepare_fs_state(ctx, blend, &cfg); |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 563 | } |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 564 | } |
| 565 | |
Alyssa Rosenzweig | 80f1d61 | 2020-08-21 14:35:35 -0400 | [diff] [blame] | 566 | mali_ptr |
| 567 | panfrost_emit_compute_shader_meta(struct panfrost_batch *batch, enum pipe_shader_type stage) |
| 568 | { |
| 569 | struct panfrost_shader_state *ss = panfrost_get_shader_state(batch->ctx, stage); |
| 570 | |
| 571 | panfrost_batch_add_bo(batch, ss->bo, |
| 572 | PAN_BO_ACCESS_PRIVATE | |
| 573 | PAN_BO_ACCESS_READ | |
| 574 | PAN_BO_ACCESS_VERTEX_TILER); |
| 575 | |
| 576 | panfrost_batch_add_bo(batch, pan_resource(ss->upload.rsrc)->bo, |
| 577 | PAN_BO_ACCESS_PRIVATE | |
| 578 | PAN_BO_ACCESS_READ | |
| 579 | PAN_BO_ACCESS_VERTEX_TILER); |
| 580 | |
| 581 | return pan_resource(ss->upload.rsrc)->bo->gpu + ss->upload.offset; |
| 582 | } |
| 583 | |
| 584 | mali_ptr |
| 585 | panfrost_emit_frag_shader_meta(struct panfrost_batch *batch) |
Boris Brezillon | 5d33d42 | 2020-03-05 11:02:56 +0100 | [diff] [blame] | 586 | { |
| 587 | struct panfrost_context *ctx = batch->ctx; |
Alyssa Rosenzweig | 80f1d61 | 2020-08-21 14:35:35 -0400 | [diff] [blame] | 588 | struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 589 | |
Boris Brezillon | 5d33d42 | 2020-03-05 11:02:56 +0100 | [diff] [blame] | 590 | /* Add the shader BO to the batch. */ |
| 591 | panfrost_batch_add_bo(batch, ss->bo, |
| 592 | PAN_BO_ACCESS_PRIVATE | |
| 593 | PAN_BO_ACCESS_READ | |
Alyssa Rosenzweig | 80f1d61 | 2020-08-21 14:35:35 -0400 | [diff] [blame] | 594 | PAN_BO_ACCESS_FRAGMENT); |
Boris Brezillon | 5d33d42 | 2020-03-05 11:02:56 +0100 | [diff] [blame] | 595 | |
Alyssa Rosenzweig | 80f1d61 | 2020-08-21 14:35:35 -0400 | [diff] [blame] | 596 | struct panfrost_device *dev = pan_device(ctx->base.screen); |
| 597 | unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); |
Alyssa Rosenzweig | 80f1d61 | 2020-08-21 14:35:35 -0400 | [diff] [blame] | 598 | struct panfrost_transfer xfer; |
| 599 | unsigned rt_size; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 600 | |
Alyssa Rosenzweig | 80f1d61 | 2020-08-21 14:35:35 -0400 | [diff] [blame] | 601 | if (dev->quirks & MIDGARD_SFBD) |
| 602 | rt_size = 0; |
Alyssa Rosenzweig | 80f1d61 | 2020-08-21 14:35:35 -0400 | [diff] [blame] | 603 | else |
Boris Brezillon | 8389976 | 2020-09-16 13:31:37 +0200 | [diff] [blame] | 604 | rt_size = MALI_BLEND_LENGTH; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 605 | |
Boris Brezillon | f734e67 | 2020-09-29 15:47:04 +0200 | [diff] [blame] | 606 | unsigned desc_size = MALI_RENDERER_STATE_LENGTH + rt_size * rt_count; |
| 607 | xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, MALI_RENDERER_STATE_LENGTH); |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 608 | |
Alyssa Rosenzweig | 80f1d61 | 2020-08-21 14:35:35 -0400 | [diff] [blame] | 609 | struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; |
Icecream95 | 2aa5838 | 2020-09-19 20:33:14 +1200 | [diff] [blame] | 610 | unsigned shader_offset = 0; |
| 611 | struct panfrost_bo *shader_bo = NULL; |
Boris Brezillon | b02f97c | 2020-03-05 16:20:18 +0100 | [diff] [blame] | 612 | |
Alyssa Rosenzweig | 80f1d61 | 2020-08-21 14:35:35 -0400 | [diff] [blame] | 613 | for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c) |
Icecream95 | 2aa5838 | 2020-09-19 20:33:14 +1200 | [diff] [blame] | 614 | blend[c] = panfrost_get_blend_for_context(ctx, c, &shader_bo, |
| 615 | &shader_offset); |
Boris Brezillon | f734e67 | 2020-09-29 15:47:04 +0200 | [diff] [blame] | 616 | panfrost_emit_frag_shader(ctx, (struct mali_renderer_state_packed *) xfer.cpu, blend); |
Alyssa Rosenzweig | 1b377c2 | 2020-08-21 19:27:40 -0400 | [diff] [blame] | 617 | |
Alyssa Rosenzweig | 45c59db | 2020-08-24 12:07:59 -0400 | [diff] [blame] | 618 | if (!(dev->quirks & MIDGARD_SFBD)) |
Boris Brezillon | f734e67 | 2020-09-29 15:47:04 +0200 | [diff] [blame] | 619 | panfrost_emit_blend(batch, xfer.cpu + MALI_RENDERER_STATE_LENGTH, blend); |
Alyssa Rosenzweig | 45c59db | 2020-08-24 12:07:59 -0400 | [diff] [blame] | 620 | else |
| 621 | batch->draws |= PIPE_CLEAR_COLOR0; |
Tomeu Vizoso | 3c98c45 | 2020-04-24 08:40:51 +0200 | [diff] [blame] | 622 | |
Alyssa Rosenzweig | 80f1d61 | 2020-08-21 14:35:35 -0400 | [diff] [blame] | 623 | return xfer.gpu; |
Boris Brezillon | 5d33d42 | 2020-03-05 11:02:56 +0100 | [diff] [blame] | 624 | } |
| 625 | |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 626 | mali_ptr |
| 627 | panfrost_emit_viewport(struct panfrost_batch *batch) |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 628 | { |
| 629 | struct panfrost_context *ctx = batch->ctx; |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 630 | const struct pipe_viewport_state *vp = &ctx->pipe_viewport; |
| 631 | const struct pipe_scissor_state *ss = &ctx->scissor; |
| 632 | const struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; |
| 633 | const struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer; |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 634 | |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 635 | /* Derive min/max from translate/scale. Note since |x| >= 0 by |
| 636 | * definition, we have that -|x| <= |x| hence translate - |scale| <= |
| 637 | * translate + |scale|, so the ordering is correct here. */ |
Icecream95 | e560028c8 | 2020-09-23 19:09:23 +1200 | [diff] [blame] | 638 | float vp_minx = vp->translate[0] - fabsf(vp->scale[0]); |
| 639 | float vp_maxx = vp->translate[0] + fabsf(vp->scale[0]); |
| 640 | float vp_miny = vp->translate[1] - fabsf(vp->scale[1]); |
| 641 | float vp_maxy = vp->translate[1] + fabsf(vp->scale[1]); |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 642 | float minz = (vp->translate[2] - fabsf(vp->scale[2])); |
| 643 | float maxz = (vp->translate[2] + fabsf(vp->scale[2])); |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 644 | |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 645 | /* Scissor to the intersection of viewport and to the scissor, clamped |
| 646 | * to the framebuffer */ |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 647 | |
Icecream95 | 3d0ae7a | 2020-09-23 21:35:03 +1200 | [diff] [blame] | 648 | unsigned minx = MIN2(fb->width, MAX2((int) vp_minx, 0)); |
| 649 | unsigned maxx = MIN2(fb->width, MAX2((int) vp_maxx, 0)); |
| 650 | unsigned miny = MIN2(fb->height, MAX2((int) vp_miny, 0)); |
| 651 | unsigned maxy = MIN2(fb->height, MAX2((int) vp_maxy, 0)); |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 652 | |
Alyssa Rosenzweig | ec35159 | 2020-08-14 17:50:44 -0400 | [diff] [blame] | 653 | if (ss && rast->scissor) { |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 654 | minx = MAX2(ss->minx, minx); |
| 655 | miny = MAX2(ss->miny, miny); |
| 656 | maxx = MIN2(ss->maxx, maxx); |
| 657 | maxy = MIN2(ss->maxy, maxy); |
| 658 | } |
| 659 | |
Icecream95 | 3d0ae7a | 2020-09-23 21:35:03 +1200 | [diff] [blame] | 660 | /* Set the range to [1, 1) so max values don't wrap round */ |
| 661 | if (maxx == 0 || maxy == 0) |
| 662 | maxx = maxy = minx = miny = 1; |
| 663 | |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 664 | struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, MALI_VIEWPORT_LENGTH); |
| 665 | |
| 666 | pan_pack(T.cpu, VIEWPORT, cfg) { |
Icecream95 | 3d0ae7a | 2020-09-23 21:35:03 +1200 | [diff] [blame] | 667 | /* [minx, maxx) and [miny, maxy) are exclusive ranges, but |
| 668 | * these are inclusive */ |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 669 | cfg.scissor_minimum_x = minx; |
| 670 | cfg.scissor_minimum_y = miny; |
| 671 | cfg.scissor_maximum_x = maxx - 1; |
| 672 | cfg.scissor_maximum_y = maxy - 1; |
| 673 | |
| 674 | cfg.minimum_z = rast->depth_clip_near ? minz : -INFINITY; |
| 675 | cfg.maximum_z = rast->depth_clip_far ? maxz : INFINITY; |
| 676 | } |
| 677 | |
Alyssa Rosenzweig | 7f487e0 | 2020-08-05 19:33:20 -0400 | [diff] [blame] | 678 | panfrost_batch_union_scissor(batch, minx, miny, maxx, maxy); |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 679 | return T.gpu; |
Boris Brezillon | a72bab1 | 2020-03-05 09:30:58 +0100 | [diff] [blame] | 680 | } |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 681 | |
| 682 | static mali_ptr |
| 683 | panfrost_map_constant_buffer_gpu(struct panfrost_batch *batch, |
| 684 | enum pipe_shader_type st, |
| 685 | struct panfrost_constant_buffer *buf, |
| 686 | unsigned index) |
| 687 | { |
| 688 | struct pipe_constant_buffer *cb = &buf->cb[index]; |
| 689 | struct panfrost_resource *rsrc = pan_resource(cb->buffer); |
| 690 | |
| 691 | if (rsrc) { |
| 692 | panfrost_batch_add_bo(batch, rsrc->bo, |
| 693 | PAN_BO_ACCESS_SHARED | |
| 694 | PAN_BO_ACCESS_READ | |
| 695 | panfrost_bo_access_for_stage(st)); |
| 696 | |
| 697 | /* Alignment gauranteed by |
| 698 | * PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */ |
| 699 | return rsrc->bo->gpu + cb->buffer_offset; |
| 700 | } else if (cb->user_buffer) { |
Alyssa Rosenzweig | 1cfbc5c | 2020-08-20 13:36:46 -0400 | [diff] [blame] | 701 | return panfrost_pool_upload_aligned(&batch->pool, |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 702 | cb->user_buffer + |
| 703 | cb->buffer_offset, |
Alyssa Rosenzweig | 1cfbc5c | 2020-08-20 13:36:46 -0400 | [diff] [blame] | 704 | cb->buffer_size, 16); |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 705 | } else { |
| 706 | unreachable("No constant buffer"); |
| 707 | } |
| 708 | } |
| 709 | |
| 710 | struct sysval_uniform { |
| 711 | union { |
| 712 | float f[4]; |
| 713 | int32_t i[4]; |
| 714 | uint32_t u[4]; |
| 715 | uint64_t du[2]; |
| 716 | }; |
| 717 | }; |
| 718 | |
| 719 | static void |
| 720 | panfrost_upload_viewport_scale_sysval(struct panfrost_batch *batch, |
| 721 | struct sysval_uniform *uniform) |
| 722 | { |
| 723 | struct panfrost_context *ctx = batch->ctx; |
| 724 | const struct pipe_viewport_state *vp = &ctx->pipe_viewport; |
| 725 | |
| 726 | uniform->f[0] = vp->scale[0]; |
| 727 | uniform->f[1] = vp->scale[1]; |
| 728 | uniform->f[2] = vp->scale[2]; |
| 729 | } |
| 730 | |
| 731 | static void |
| 732 | panfrost_upload_viewport_offset_sysval(struct panfrost_batch *batch, |
| 733 | struct sysval_uniform *uniform) |
| 734 | { |
| 735 | struct panfrost_context *ctx = batch->ctx; |
| 736 | const struct pipe_viewport_state *vp = &ctx->pipe_viewport; |
| 737 | |
| 738 | uniform->f[0] = vp->translate[0]; |
| 739 | uniform->f[1] = vp->translate[1]; |
| 740 | uniform->f[2] = vp->translate[2]; |
| 741 | } |
| 742 | |
| 743 | static void panfrost_upload_txs_sysval(struct panfrost_batch *batch, |
| 744 | enum pipe_shader_type st, |
| 745 | unsigned int sysvalid, |
| 746 | struct sysval_uniform *uniform) |
| 747 | { |
| 748 | struct panfrost_context *ctx = batch->ctx; |
| 749 | unsigned texidx = PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid); |
| 750 | unsigned dim = PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid); |
| 751 | bool is_array = PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid); |
| 752 | struct pipe_sampler_view *tex = &ctx->sampler_views[st][texidx]->base; |
| 753 | |
| 754 | assert(dim); |
| 755 | uniform->i[0] = u_minify(tex->texture->width0, tex->u.tex.first_level); |
| 756 | |
| 757 | if (dim > 1) |
| 758 | uniform->i[1] = u_minify(tex->texture->height0, |
| 759 | tex->u.tex.first_level); |
| 760 | |
| 761 | if (dim > 2) |
| 762 | uniform->i[2] = u_minify(tex->texture->depth0, |
| 763 | tex->u.tex.first_level); |
| 764 | |
| 765 | if (is_array) |
| 766 | uniform->i[dim] = tex->texture->array_size; |
| 767 | } |
| 768 | |
| 769 | static void |
| 770 | panfrost_upload_ssbo_sysval(struct panfrost_batch *batch, |
| 771 | enum pipe_shader_type st, |
| 772 | unsigned ssbo_id, |
| 773 | struct sysval_uniform *uniform) |
| 774 | { |
| 775 | struct panfrost_context *ctx = batch->ctx; |
| 776 | |
| 777 | assert(ctx->ssbo_mask[st] & (1 << ssbo_id)); |
| 778 | struct pipe_shader_buffer sb = ctx->ssbo[st][ssbo_id]; |
| 779 | |
| 780 | /* Compute address */ |
| 781 | struct panfrost_bo *bo = pan_resource(sb.buffer)->bo; |
| 782 | |
| 783 | panfrost_batch_add_bo(batch, bo, |
| 784 | PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_RW | |
| 785 | panfrost_bo_access_for_stage(st)); |
| 786 | |
| 787 | /* Upload address and size as sysval */ |
| 788 | uniform->du[0] = bo->gpu + sb.buffer_offset; |
| 789 | uniform->u[2] = sb.buffer_size; |
| 790 | } |
| 791 | |
| 792 | static void |
| 793 | panfrost_upload_sampler_sysval(struct panfrost_batch *batch, |
| 794 | enum pipe_shader_type st, |
| 795 | unsigned samp_idx, |
| 796 | struct sysval_uniform *uniform) |
| 797 | { |
| 798 | struct panfrost_context *ctx = batch->ctx; |
| 799 | struct pipe_sampler_state *sampl = &ctx->samplers[st][samp_idx]->base; |
| 800 | |
| 801 | uniform->f[0] = sampl->min_lod; |
| 802 | uniform->f[1] = sampl->max_lod; |
| 803 | uniform->f[2] = sampl->lod_bias; |
| 804 | |
| 805 | /* Even without any errata, Midgard represents "no mipmapping" as |
| 806 | * fixing the LOD with the clamps; keep behaviour consistent. c.f. |
| 807 | * panfrost_create_sampler_state which also explains our choice of |
| 808 | * epsilon value (again to keep behaviour consistent) */ |
| 809 | |
| 810 | if (sampl->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) |
| 811 | uniform->f[1] = uniform->f[0] + (1.0/256.0); |
| 812 | } |
| 813 | |
| 814 | static void |
| 815 | panfrost_upload_num_work_groups_sysval(struct panfrost_batch *batch, |
| 816 | struct sysval_uniform *uniform) |
| 817 | { |
| 818 | struct panfrost_context *ctx = batch->ctx; |
| 819 | |
| 820 | uniform->u[0] = ctx->compute_grid->grid[0]; |
| 821 | uniform->u[1] = ctx->compute_grid->grid[1]; |
| 822 | uniform->u[2] = ctx->compute_grid->grid[2]; |
| 823 | } |
| 824 | |
| 825 | static void |
| 826 | panfrost_upload_sysvals(struct panfrost_batch *batch, void *buf, |
| 827 | struct panfrost_shader_state *ss, |
| 828 | enum pipe_shader_type st) |
| 829 | { |
| 830 | struct sysval_uniform *uniforms = (void *)buf; |
| 831 | |
| 832 | for (unsigned i = 0; i < ss->sysval_count; ++i) { |
| 833 | int sysval = ss->sysval[i]; |
| 834 | |
| 835 | switch (PAN_SYSVAL_TYPE(sysval)) { |
| 836 | case PAN_SYSVAL_VIEWPORT_SCALE: |
| 837 | panfrost_upload_viewport_scale_sysval(batch, |
| 838 | &uniforms[i]); |
| 839 | break; |
| 840 | case PAN_SYSVAL_VIEWPORT_OFFSET: |
| 841 | panfrost_upload_viewport_offset_sysval(batch, |
| 842 | &uniforms[i]); |
| 843 | break; |
| 844 | case PAN_SYSVAL_TEXTURE_SIZE: |
| 845 | panfrost_upload_txs_sysval(batch, st, |
| 846 | PAN_SYSVAL_ID(sysval), |
| 847 | &uniforms[i]); |
| 848 | break; |
| 849 | case PAN_SYSVAL_SSBO: |
| 850 | panfrost_upload_ssbo_sysval(batch, st, |
| 851 | PAN_SYSVAL_ID(sysval), |
| 852 | &uniforms[i]); |
| 853 | break; |
| 854 | case PAN_SYSVAL_NUM_WORK_GROUPS: |
| 855 | panfrost_upload_num_work_groups_sysval(batch, |
| 856 | &uniforms[i]); |
| 857 | break; |
| 858 | case PAN_SYSVAL_SAMPLER: |
| 859 | panfrost_upload_sampler_sysval(batch, st, |
| 860 | PAN_SYSVAL_ID(sysval), |
| 861 | &uniforms[i]); |
| 862 | break; |
| 863 | default: |
| 864 | assert(0); |
| 865 | } |
| 866 | } |
| 867 | } |
| 868 | |
| 869 | static const void * |
| 870 | panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer *buf, |
| 871 | unsigned index) |
| 872 | { |
| 873 | struct pipe_constant_buffer *cb = &buf->cb[index]; |
| 874 | struct panfrost_resource *rsrc = pan_resource(cb->buffer); |
| 875 | |
| 876 | if (rsrc) |
| 877 | return rsrc->bo->cpu; |
| 878 | else if (cb->user_buffer) |
| 879 | return cb->user_buffer; |
| 880 | else |
| 881 | unreachable("No constant buffer"); |
| 882 | } |
| 883 | |
Alyssa Rosenzweig | 8b5f9fc | 2020-08-25 12:03:17 -0400 | [diff] [blame] | 884 | mali_ptr |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 885 | panfrost_emit_const_buf(struct panfrost_batch *batch, |
| 886 | enum pipe_shader_type stage, |
Alyssa Rosenzweig | 8b5f9fc | 2020-08-25 12:03:17 -0400 | [diff] [blame] | 887 | mali_ptr *push_constants) |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 888 | { |
| 889 | struct panfrost_context *ctx = batch->ctx; |
| 890 | struct panfrost_shader_variants *all = ctx->shader[stage]; |
| 891 | |
| 892 | if (!all) |
Alyssa Rosenzweig | 8b5f9fc | 2020-08-25 12:03:17 -0400 | [diff] [blame] | 893 | return 0; |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 894 | |
| 895 | struct panfrost_constant_buffer *buf = &ctx->constant_buffer[stage]; |
| 896 | |
| 897 | struct panfrost_shader_state *ss = &all->variants[all->active_variant]; |
| 898 | |
| 899 | /* Uniforms are implicitly UBO #0 */ |
| 900 | bool has_uniforms = buf->enabled_mask & (1 << 0); |
| 901 | |
| 902 | /* Allocate room for the sysval and the uniforms */ |
| 903 | size_t sys_size = sizeof(float) * 4 * ss->sysval_count; |
| 904 | size_t uniform_size = has_uniforms ? (buf->cb[0].buffer_size) : 0; |
| 905 | size_t size = sys_size + uniform_size; |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 906 | struct panfrost_transfer transfer = |
| 907 | panfrost_pool_alloc_aligned(&batch->pool, size, 16); |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 908 | |
| 909 | /* Upload sysvals requested by the shader */ |
| 910 | panfrost_upload_sysvals(batch, transfer.cpu, ss, stage); |
| 911 | |
| 912 | /* Upload uniforms */ |
| 913 | if (has_uniforms && uniform_size) { |
| 914 | const void *cpu = panfrost_map_constant_buffer_cpu(buf, 0); |
| 915 | memcpy(transfer.cpu + sys_size, cpu, uniform_size); |
| 916 | } |
| 917 | |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 918 | /* Next up, attach UBOs. UBO #0 is the uniforms we just |
Alyssa Rosenzweig | 5393d73 | 2020-08-21 10:42:59 -0400 | [diff] [blame] | 919 | * uploaded, so it's always included. The count is the highest UBO |
| 920 | * addressable -- gaps are included. */ |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 921 | |
Alyssa Rosenzweig | 5393d73 | 2020-08-21 10:42:59 -0400 | [diff] [blame] | 922 | unsigned ubo_count = 32 - __builtin_clz(buf->enabled_mask | 1); |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 923 | |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 924 | size_t sz = MALI_UNIFORM_BUFFER_LENGTH * ubo_count; |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 925 | struct panfrost_transfer ubos = |
| 926 | panfrost_pool_alloc_aligned(&batch->pool, sz, |
| 927 | MALI_UNIFORM_BUFFER_LENGTH); |
| 928 | |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 929 | uint64_t *ubo_ptr = (uint64_t *) ubos.cpu; |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 930 | |
| 931 | /* Upload uniforms as a UBO */ |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 932 | |
Alyssa Rosenzweig | e451421 | 2020-08-19 09:48:40 -0400 | [diff] [blame] | 933 | if (size) { |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 934 | pan_pack(ubo_ptr, UNIFORM_BUFFER, cfg) { |
Alyssa Rosenzweig | e451421 | 2020-08-19 09:48:40 -0400 | [diff] [blame] | 935 | cfg.entries = DIV_ROUND_UP(size, 16); |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 936 | cfg.pointer = transfer.gpu; |
| 937 | } |
| 938 | } else { |
| 939 | *ubo_ptr = 0; |
| 940 | } |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 941 | |
| 942 | /* The rest are honest-to-goodness UBOs */ |
| 943 | |
| 944 | for (unsigned ubo = 1; ubo < ubo_count; ++ubo) { |
| 945 | size_t usz = buf->cb[ubo].buffer_size; |
| 946 | bool enabled = buf->enabled_mask & (1 << ubo); |
| 947 | bool empty = usz == 0; |
| 948 | |
| 949 | if (!enabled || empty) { |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 950 | ubo_ptr[ubo] = 0; |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 951 | continue; |
| 952 | } |
| 953 | |
Icecream95 | 2aa48bb | 2020-09-20 15:30:45 +1200 | [diff] [blame] | 954 | /* Issue (57) for the ARB_uniform_buffer_object spec says that |
| 955 | * the buffer can be larger than the uniform data inside it, |
| 956 | * so clamp ubo size to what hardware supports. */ |
| 957 | |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 958 | pan_pack(ubo_ptr + ubo, UNIFORM_BUFFER, cfg) { |
Icecream95 | 2aa48bb | 2020-09-20 15:30:45 +1200 | [diff] [blame] | 959 | cfg.entries = MIN2(DIV_ROUND_UP(usz, 16), 1 << 12); |
Alyssa Rosenzweig | fa94967 | 2020-08-05 21:39:25 -0400 | [diff] [blame] | 960 | cfg.pointer = panfrost_map_constant_buffer_gpu(batch, |
| 961 | stage, buf, ubo); |
| 962 | } |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 963 | } |
| 964 | |
Alyssa Rosenzweig | 8b5f9fc | 2020-08-25 12:03:17 -0400 | [diff] [blame] | 965 | *push_constants = transfer.gpu; |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 966 | |
| 967 | buf->dirty_mask = 0; |
Alyssa Rosenzweig | 8b5f9fc | 2020-08-25 12:03:17 -0400 | [diff] [blame] | 968 | return ubos.gpu; |
Boris Brezillon | 0b735a2 | 2020-03-05 09:46:42 +0100 | [diff] [blame] | 969 | } |
Boris Brezillon | 36725be | 2020-03-05 09:57:44 +0100 | [diff] [blame] | 970 | |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 971 | mali_ptr |
Boris Brezillon | 36725be | 2020-03-05 09:57:44 +0100 | [diff] [blame] | 972 | panfrost_emit_shared_memory(struct panfrost_batch *batch, |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 973 | const struct pipe_grid_info *info) |
Boris Brezillon | 36725be | 2020-03-05 09:57:44 +0100 | [diff] [blame] | 974 | { |
| 975 | struct panfrost_context *ctx = batch->ctx; |
Alyssa Rosenzweig | 415eb43 | 2020-08-13 18:11:12 -0400 | [diff] [blame] | 976 | struct panfrost_device *dev = pan_device(ctx->base.screen); |
Boris Brezillon | 36725be | 2020-03-05 09:57:44 +0100 | [diff] [blame] | 977 | struct panfrost_shader_variants *all = ctx->shader[PIPE_SHADER_COMPUTE]; |
| 978 | struct panfrost_shader_state *ss = &all->variants[all->active_variant]; |
| 979 | unsigned single_size = util_next_power_of_two(MAX2(ss->shared_size, |
| 980 | 128)); |
Alyssa Rosenzweig | 415eb43 | 2020-08-13 18:11:12 -0400 | [diff] [blame] | 981 | |
| 982 | unsigned log2_instances = |
| 983 | util_logbase2_ceil(info->grid[0]) + |
| 984 | util_logbase2_ceil(info->grid[1]) + |
| 985 | util_logbase2_ceil(info->grid[2]); |
| 986 | |
| 987 | unsigned shared_size = single_size * (1 << log2_instances) * dev->core_count; |
Boris Brezillon | 36725be | 2020-03-05 09:57:44 +0100 | [diff] [blame] | 988 | struct panfrost_bo *bo = panfrost_batch_get_shared_memory(batch, |
| 989 | shared_size, |
| 990 | 1); |
Boris Brezillon | 3a06fc3 | 2020-09-03 09:18:09 +0200 | [diff] [blame] | 991 | struct panfrost_transfer t = |
| 992 | panfrost_pool_alloc_aligned(&batch->pool, |
| 993 | MALI_LOCAL_STORAGE_LENGTH, |
| 994 | 64); |
Boris Brezillon | 36725be | 2020-03-05 09:57:44 +0100 | [diff] [blame] | 995 | |
Boris Brezillon | 3a06fc3 | 2020-09-03 09:18:09 +0200 | [diff] [blame] | 996 | pan_pack(t.cpu, LOCAL_STORAGE, ls) { |
| 997 | ls.wls_base_pointer = bo->gpu; |
| 998 | ls.wls_instances = log2_instances; |
| 999 | ls.wls_size_scale = util_logbase2(single_size) + 1; |
Boris Brezillon | 36725be | 2020-03-05 09:57:44 +0100 | [diff] [blame] | 1000 | }; |
| 1001 | |
Boris Brezillon | 3a06fc3 | 2020-09-03 09:18:09 +0200 | [diff] [blame] | 1002 | return t.gpu; |
Boris Brezillon | 36725be | 2020-03-05 09:57:44 +0100 | [diff] [blame] | 1003 | } |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1004 | |
| 1005 | static mali_ptr |
| 1006 | panfrost_get_tex_desc(struct panfrost_batch *batch, |
| 1007 | enum pipe_shader_type st, |
| 1008 | struct panfrost_sampler_view *view) |
| 1009 | { |
| 1010 | if (!view) |
| 1011 | return (mali_ptr) 0; |
| 1012 | |
| 1013 | struct pipe_sampler_view *pview = &view->base; |
| 1014 | struct panfrost_resource *rsrc = pan_resource(pview->texture); |
| 1015 | |
| 1016 | /* Add the BO to the job so it's retained until the job is done. */ |
| 1017 | |
| 1018 | panfrost_batch_add_bo(batch, rsrc->bo, |
| 1019 | PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | |
| 1020 | panfrost_bo_access_for_stage(st)); |
| 1021 | |
Alyssa Rosenzweig | 32b171d | 2020-06-15 09:20:39 -0400 | [diff] [blame] | 1022 | panfrost_batch_add_bo(batch, view->bo, |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1023 | PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | |
| 1024 | panfrost_bo_access_for_stage(st)); |
| 1025 | |
Alyssa Rosenzweig | 32b171d | 2020-06-15 09:20:39 -0400 | [diff] [blame] | 1026 | return view->bo->gpu; |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1027 | } |
| 1028 | |
Icecream95 | fafc305 | 2020-06-12 20:14:02 +1200 | [diff] [blame] | 1029 | static void |
| 1030 | panfrost_update_sampler_view(struct panfrost_sampler_view *view, |
| 1031 | struct pipe_context *pctx) |
| 1032 | { |
| 1033 | struct panfrost_resource *rsrc = pan_resource(view->base.texture); |
Icecream95 | 65b3b08 | 2020-06-20 19:09:03 +1200 | [diff] [blame] | 1034 | if (view->texture_bo != rsrc->bo->gpu || |
Alyssa Rosenzweig | 965537df | 2020-07-22 10:23:50 -0400 | [diff] [blame] | 1035 | view->modifier != rsrc->modifier) { |
Alyssa Rosenzweig | 32b171d | 2020-06-15 09:20:39 -0400 | [diff] [blame] | 1036 | panfrost_bo_unreference(view->bo); |
Icecream95 | fafc305 | 2020-06-12 20:14:02 +1200 | [diff] [blame] | 1037 | panfrost_create_sampler_view_bo(view, pctx, &rsrc->base); |
| 1038 | } |
| 1039 | } |
| 1040 | |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 1041 | mali_ptr |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1042 | panfrost_emit_texture_descriptors(struct panfrost_batch *batch, |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 1043 | enum pipe_shader_type stage) |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1044 | { |
| 1045 | struct panfrost_context *ctx = batch->ctx; |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1046 | struct panfrost_device *device = pan_device(ctx->base.screen); |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1047 | |
| 1048 | if (!ctx->sampler_view_count[stage]) |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 1049 | return 0; |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1050 | |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1051 | if (device->quirks & IS_BIFROST) { |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 1052 | struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, |
Alyssa Rosenzweig | ad0b32c | 2020-08-06 18:12:28 -0400 | [diff] [blame] | 1053 | MALI_BIFROST_TEXTURE_LENGTH * |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 1054 | ctx->sampler_view_count[stage], |
| 1055 | MALI_BIFROST_TEXTURE_LENGTH); |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1056 | |
Alyssa Rosenzweig | ad0b32c | 2020-08-06 18:12:28 -0400 | [diff] [blame] | 1057 | struct mali_bifrost_texture_packed *out = |
| 1058 | (struct mali_bifrost_texture_packed *) T.cpu; |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1059 | |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1060 | for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) { |
| 1061 | struct panfrost_sampler_view *view = ctx->sampler_views[stage][i]; |
| 1062 | struct pipe_sampler_view *pview = &view->base; |
| 1063 | struct panfrost_resource *rsrc = pan_resource(pview->texture); |
Alyssa Rosenzweig | ad0b32c | 2020-08-06 18:12:28 -0400 | [diff] [blame] | 1064 | |
Alyssa Rosenzweig | 65e0e89 | 2020-06-15 09:23:27 -0400 | [diff] [blame] | 1065 | panfrost_update_sampler_view(view, &ctx->base); |
Alyssa Rosenzweig | ad0b32c | 2020-08-06 18:12:28 -0400 | [diff] [blame] | 1066 | out[i] = view->bifrost_descriptor; |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1067 | |
Tomeu Vizoso | 3a81abf | 2020-05-01 11:37:56 +0200 | [diff] [blame] | 1068 | /* Add the BOs to the job so they are retained until the job is done. */ |
| 1069 | |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1070 | panfrost_batch_add_bo(batch, rsrc->bo, |
| 1071 | PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | |
| 1072 | panfrost_bo_access_for_stage(stage)); |
| 1073 | |
Alyssa Rosenzweig | 32b171d | 2020-06-15 09:20:39 -0400 | [diff] [blame] | 1074 | panfrost_batch_add_bo(batch, view->bo, |
Tomeu Vizoso | 3a81abf | 2020-05-01 11:37:56 +0200 | [diff] [blame] | 1075 | PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | |
| 1076 | panfrost_bo_access_for_stage(stage)); |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1077 | } |
| 1078 | |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 1079 | return T.gpu; |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1080 | } else { |
| 1081 | uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS]; |
| 1082 | |
Icecream95 | fafc305 | 2020-06-12 20:14:02 +1200 | [diff] [blame] | 1083 | for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) { |
| 1084 | struct panfrost_sampler_view *view = ctx->sampler_views[stage][i]; |
| 1085 | |
| 1086 | panfrost_update_sampler_view(view, &ctx->base); |
| 1087 | |
| 1088 | trampolines[i] = panfrost_get_tex_desc(batch, stage, view); |
| 1089 | } |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1090 | |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 1091 | return panfrost_pool_upload_aligned(&batch->pool, trampolines, |
| 1092 | sizeof(uint64_t) * |
| 1093 | ctx->sampler_view_count[stage], |
| 1094 | sizeof(uint64_t)); |
Tomeu Vizoso | e41894b | 2020-04-17 14:23:49 +0200 | [diff] [blame] | 1095 | } |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1096 | } |
| 1097 | |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 1098 | mali_ptr |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1099 | panfrost_emit_sampler_descriptors(struct panfrost_batch *batch, |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 1100 | enum pipe_shader_type stage) |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1101 | { |
| 1102 | struct panfrost_context *ctx = batch->ctx; |
| 1103 | |
| 1104 | if (!ctx->sampler_count[stage]) |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 1105 | return 0; |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1106 | |
Alyssa Rosenzweig | b10c3c8 | 2020-08-11 18:25:03 -0400 | [diff] [blame] | 1107 | size_t desc_size = MALI_BIFROST_SAMPLER_LENGTH; |
| 1108 | assert(MALI_BIFROST_SAMPLER_LENGTH == MALI_MIDGARD_SAMPLER_LENGTH); |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1109 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 1110 | size_t sz = desc_size * ctx->sampler_count[stage]; |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 1111 | struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, sz, desc_size); |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 1112 | struct mali_midgard_sampler_packed *out = (struct mali_midgard_sampler_packed *) T.cpu; |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1113 | |
Alyssa Rosenzweig | f74186b | 2020-08-11 18:23:12 -0400 | [diff] [blame] | 1114 | for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i) |
| 1115 | out[i] = ctx->samplers[stage][i]->hw; |
Tomeu Vizoso | d3eb23a | 2020-04-17 14:23:39 +0200 | [diff] [blame] | 1116 | |
Alyssa Rosenzweig | b716936 | 2020-08-24 13:54:20 -0400 | [diff] [blame] | 1117 | return T.gpu; |
Boris Brezillon | 8e0a08b | 2020-03-05 18:43:13 +0100 | [diff] [blame] | 1118 | } |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 1119 | |
Alyssa Rosenzweig | 1513392 | 2020-08-25 12:48:12 -0400 | [diff] [blame] | 1120 | mali_ptr |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1121 | panfrost_emit_vertex_data(struct panfrost_batch *batch, |
Alyssa Rosenzweig | 1513392 | 2020-08-25 12:48:12 -0400 | [diff] [blame] | 1122 | mali_ptr *buffers) |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1123 | { |
| 1124 | struct panfrost_context *ctx = batch->ctx; |
| 1125 | struct panfrost_vertex_state *so = ctx->vertex; |
Alyssa Rosenzweig | 09ea7c0 | 2020-08-17 14:42:41 -0400 | [diff] [blame] | 1126 | struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX); |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1127 | |
Alyssa Rosenzweig | 9a6934d | 2020-08-17 14:46:56 -0400 | [diff] [blame] | 1128 | /* Worst case: everything is NPOT, which is only possible if instancing |
| 1129 | * is enabled. Otherwise single record is gauranteed */ |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 1130 | struct panfrost_transfer S = panfrost_pool_alloc_aligned(&batch->pool, |
Alyssa Rosenzweig | 94f4ecb | 2020-08-17 14:49:52 -0400 | [diff] [blame] | 1131 | MALI_ATTRIBUTE_BUFFER_LENGTH * vs->attribute_count * |
Alyssa Rosenzweig | 1513392 | 2020-08-25 12:48:12 -0400 | [diff] [blame] | 1132 | (ctx->instance_count > 1 ? 2 : 1), |
Alyssa Rosenzweig | 1cfbc5c | 2020-08-20 13:36:46 -0400 | [diff] [blame] | 1133 | MALI_ATTRIBUTE_BUFFER_LENGTH * 2); |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1134 | |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 1135 | struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, |
Alyssa Rosenzweig | 09ea7c0 | 2020-08-17 14:42:41 -0400 | [diff] [blame] | 1136 | MALI_ATTRIBUTE_LENGTH * vs->attribute_count, |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 1137 | MALI_ATTRIBUTE_LENGTH); |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1138 | |
| 1139 | struct mali_attribute_buffer_packed *bufs = |
| 1140 | (struct mali_attribute_buffer_packed *) S.cpu; |
| 1141 | |
| 1142 | struct mali_attribute_packed *out = |
| 1143 | (struct mali_attribute_packed *) T.cpu; |
| 1144 | |
Alyssa Rosenzweig | 8236fa3 | 2020-08-14 12:09:05 -0400 | [diff] [blame] | 1145 | unsigned attrib_to_buffer[PIPE_MAX_ATTRIBS] = { 0 }; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1146 | unsigned k = 0; |
| 1147 | |
| 1148 | for (unsigned i = 0; i < so->num_elements; ++i) { |
Alyssa Rosenzweig | d5a264f | 2020-08-14 15:24:35 -0400 | [diff] [blame] | 1149 | /* We map buffers 1:1 with the attributes, which |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1150 | * means duplicating some vertex buffers (who cares? aside from |
| 1151 | * maybe some caching implications but I somehow doubt that |
| 1152 | * matters) */ |
| 1153 | |
| 1154 | struct pipe_vertex_element *elem = &so->pipe[i]; |
| 1155 | unsigned vbi = elem->vertex_buffer_index; |
Alyssa Rosenzweig | 8236fa3 | 2020-08-14 12:09:05 -0400 | [diff] [blame] | 1156 | attrib_to_buffer[i] = k; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1157 | |
| 1158 | if (!(ctx->vb_mask & (1 << vbi))) |
| 1159 | continue; |
| 1160 | |
| 1161 | struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi]; |
| 1162 | struct panfrost_resource *rsrc; |
| 1163 | |
| 1164 | rsrc = pan_resource(buf->buffer.resource); |
| 1165 | if (!rsrc) |
| 1166 | continue; |
| 1167 | |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1168 | /* Add a dependency of the batch on the vertex buffer */ |
| 1169 | panfrost_batch_add_bo(batch, rsrc->bo, |
| 1170 | PAN_BO_ACCESS_SHARED | |
| 1171 | PAN_BO_ACCESS_READ | |
| 1172 | PAN_BO_ACCESS_VERTEX_TILER); |
| 1173 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1174 | /* Mask off lower bits, see offset fixup below */ |
| 1175 | mali_ptr raw_addr = rsrc->bo->gpu + buf->buffer_offset; |
| 1176 | mali_ptr addr = raw_addr & ~63; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1177 | |
| 1178 | /* Since we advanced the base pointer, we shrink the buffer |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1179 | * size, but add the offset we subtracted */ |
| 1180 | unsigned size = rsrc->base.width0 + (raw_addr - addr) |
| 1181 | - buf->buffer_offset; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1182 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1183 | /* When there is a divisor, the hardware-level divisor is |
| 1184 | * the product of the instance divisor and the padded count */ |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1185 | unsigned divisor = elem->instance_divisor; |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1186 | unsigned hw_divisor = ctx->padded_count * divisor; |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1187 | unsigned stride = buf->stride; |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1188 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1189 | /* If there's a divisor(=1) but no instancing, we want every |
| 1190 | * attribute to be the same */ |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1191 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1192 | if (divisor && ctx->instance_count == 1) |
| 1193 | stride = 0; |
| 1194 | |
| 1195 | if (!divisor || ctx->instance_count <= 1) { |
| 1196 | pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { |
Alyssa Rosenzweig | 1513392 | 2020-08-25 12:48:12 -0400 | [diff] [blame] | 1197 | if (ctx->instance_count > 1) { |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1198 | cfg.type = MALI_ATTRIBUTE_TYPE_1D_MODULUS; |
Alyssa Rosenzweig | 1513392 | 2020-08-25 12:48:12 -0400 | [diff] [blame] | 1199 | cfg.divisor = ctx->padded_count; |
| 1200 | } |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1201 | |
| 1202 | cfg.pointer = addr; |
| 1203 | cfg.stride = stride; |
| 1204 | cfg.size = size; |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1205 | } |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1206 | } else if (util_is_power_of_two_or_zero(hw_divisor)) { |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1207 | pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { |
| 1208 | cfg.type = MALI_ATTRIBUTE_TYPE_1D_POT_DIVISOR; |
| 1209 | cfg.pointer = addr; |
| 1210 | cfg.stride = stride; |
| 1211 | cfg.size = size; |
| 1212 | cfg.divisor_r = __builtin_ctz(hw_divisor); |
| 1213 | } |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1214 | |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1215 | } else { |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1216 | unsigned shift = 0, extra_flags = 0; |
| 1217 | |
| 1218 | unsigned magic_divisor = |
| 1219 | panfrost_compute_magic_divisor(hw_divisor, &shift, &extra_flags); |
| 1220 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1221 | pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { |
| 1222 | cfg.type = MALI_ATTRIBUTE_TYPE_1D_NPOT_DIVISOR; |
| 1223 | cfg.pointer = addr; |
| 1224 | cfg.stride = stride; |
| 1225 | cfg.size = size; |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1226 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1227 | cfg.divisor_r = shift; |
| 1228 | cfg.divisor_e = extra_flags; |
| 1229 | } |
Alyssa Rosenzweig | c9bb5dc | 2020-08-14 12:29:57 -0400 | [diff] [blame] | 1230 | |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1231 | pan_pack(bufs + k + 1, ATTRIBUTE_BUFFER_CONTINUATION_NPOT, cfg) { |
| 1232 | cfg.divisor_numerator = magic_divisor; |
| 1233 | cfg.divisor = divisor; |
| 1234 | } |
| 1235 | |
| 1236 | ++k; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1237 | } |
Alyssa Rosenzweig | e646c86 | 2020-08-14 12:51:36 -0400 | [diff] [blame] | 1238 | |
| 1239 | ++k; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1240 | } |
| 1241 | |
| 1242 | /* Add special gl_VertexID/gl_InstanceID buffers */ |
| 1243 | |
Alyssa Rosenzweig | 09ea7c0 | 2020-08-17 14:42:41 -0400 | [diff] [blame] | 1244 | if (unlikely(vs->attribute_count >= PAN_VERTEX_ID)) { |
| 1245 | panfrost_vertex_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); |
Alyssa Rosenzweig | 27f8b87 | 2020-08-14 12:19:10 -0400 | [diff] [blame] | 1246 | |
Alyssa Rosenzweig | 09ea7c0 | 2020-08-17 14:42:41 -0400 | [diff] [blame] | 1247 | pan_pack(out + PAN_VERTEX_ID, ATTRIBUTE, cfg) { |
| 1248 | cfg.buffer_index = k++; |
| 1249 | cfg.format = so->formats[PAN_VERTEX_ID]; |
| 1250 | } |
Alyssa Rosenzweig | 6caf789 | 2020-08-14 12:14:20 -0400 | [diff] [blame] | 1251 | |
Alyssa Rosenzweig | 09ea7c0 | 2020-08-17 14:42:41 -0400 | [diff] [blame] | 1252 | panfrost_instance_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); |
Alyssa Rosenzweig | 27f8b87 | 2020-08-14 12:19:10 -0400 | [diff] [blame] | 1253 | |
Alyssa Rosenzweig | 09ea7c0 | 2020-08-17 14:42:41 -0400 | [diff] [blame] | 1254 | pan_pack(out + PAN_INSTANCE_ID, ATTRIBUTE, cfg) { |
| 1255 | cfg.buffer_index = k++; |
| 1256 | cfg.format = so->formats[PAN_INSTANCE_ID]; |
| 1257 | } |
Alyssa Rosenzweig | 27f8b87 | 2020-08-14 12:19:10 -0400 | [diff] [blame] | 1258 | } |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1259 | |
Alyssa Rosenzweig | 9cc81ea | 2020-08-14 12:01:55 -0400 | [diff] [blame] | 1260 | /* Attribute addresses require 64-byte alignment, so let: |
Alyssa Rosenzweig | 76de3e6 | 2020-08-13 14:32:23 -0400 | [diff] [blame] | 1261 | * |
| 1262 | * base' = base & ~63 = base - (base & 63) |
Alyssa Rosenzweig | 9cc81ea | 2020-08-14 12:01:55 -0400 | [diff] [blame] | 1263 | * offset' = offset + (base & 63) |
Alyssa Rosenzweig | 76de3e6 | 2020-08-13 14:32:23 -0400 | [diff] [blame] | 1264 | * |
Alyssa Rosenzweig | 9cc81ea | 2020-08-14 12:01:55 -0400 | [diff] [blame] | 1265 | * Since base' + offset' = base + offset, these are equivalent |
| 1266 | * addressing modes and now base is 64 aligned. |
Alyssa Rosenzweig | 76de3e6 | 2020-08-13 14:32:23 -0400 | [diff] [blame] | 1267 | */ |
| 1268 | |
Alyssa Rosenzweig | 76de3e6 | 2020-08-13 14:32:23 -0400 | [diff] [blame] | 1269 | for (unsigned i = 0; i < so->num_elements; ++i) { |
| 1270 | unsigned vbi = so->pipe[i].vertex_buffer_index; |
| 1271 | struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi]; |
| 1272 | |
| 1273 | /* Adjust by the masked off bits of the offset. Make sure we |
| 1274 | * read src_offset from so->hw (which is not GPU visible) |
| 1275 | * rather than target (which is) due to caching effects */ |
| 1276 | |
| 1277 | unsigned src_offset = so->pipe[i].src_offset; |
| 1278 | |
| 1279 | /* BOs aligned to 4k so guaranteed aligned to 64 */ |
| 1280 | src_offset += (buf->buffer_offset & 63); |
| 1281 | |
| 1282 | /* Also, somewhat obscurely per-instance data needs to be |
| 1283 | * offset in response to a delayed start in an indexed draw */ |
| 1284 | |
Alyssa Rosenzweig | 1513392 | 2020-08-25 12:48:12 -0400 | [diff] [blame] | 1285 | if (so->pipe[i].instance_divisor && ctx->instance_count > 1) |
| 1286 | src_offset -= buf->stride * ctx->offset_start; |
Alyssa Rosenzweig | 76de3e6 | 2020-08-13 14:32:23 -0400 | [diff] [blame] | 1287 | |
Alyssa Rosenzweig | 27f8b87 | 2020-08-14 12:19:10 -0400 | [diff] [blame] | 1288 | pan_pack(out + i, ATTRIBUTE, cfg) { |
| 1289 | cfg.buffer_index = attrib_to_buffer[i]; |
| 1290 | cfg.format = so->formats[i]; |
| 1291 | cfg.offset = src_offset; |
| 1292 | } |
Alyssa Rosenzweig | 76de3e6 | 2020-08-13 14:32:23 -0400 | [diff] [blame] | 1293 | } |
| 1294 | |
Alyssa Rosenzweig | 1513392 | 2020-08-25 12:48:12 -0400 | [diff] [blame] | 1295 | *buffers = S.gpu; |
| 1296 | return T.gpu; |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1297 | } |
| 1298 | |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1299 | static mali_ptr |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1300 | panfrost_emit_varyings(struct panfrost_batch *batch, |
| 1301 | struct mali_attribute_buffer_packed *slot, |
| 1302 | unsigned stride, unsigned count) |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1303 | { |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1304 | unsigned size = stride * count; |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 1305 | mali_ptr ptr = panfrost_pool_alloc_aligned(&batch->invisible_pool, size, 64).gpu; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1306 | |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1307 | pan_pack(slot, ATTRIBUTE_BUFFER, cfg) { |
| 1308 | cfg.stride = stride; |
| 1309 | cfg.size = size; |
| 1310 | cfg.pointer = ptr; |
| 1311 | } |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1312 | |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1313 | return ptr; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1314 | } |
| 1315 | |
Alyssa Rosenzweig | e26ac2e | 2020-06-10 19:28:28 -0400 | [diff] [blame] | 1316 | static unsigned |
Ilia Mirkin | 4c050f2 | 2020-08-09 00:13:14 -0400 | [diff] [blame] | 1317 | panfrost_streamout_offset(unsigned stride, |
Alyssa Rosenzweig | e26ac2e | 2020-06-10 19:28:28 -0400 | [diff] [blame] | 1318 | struct pipe_stream_output_target *target) |
| 1319 | { |
Ilia Mirkin | 4c050f2 | 2020-08-09 00:13:14 -0400 | [diff] [blame] | 1320 | return (target->buffer_offset + (pan_so_target(target)->offset * stride * 4)) & 63; |
Alyssa Rosenzweig | e26ac2e | 2020-06-10 19:28:28 -0400 | [diff] [blame] | 1321 | } |
| 1322 | |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1323 | static void |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1324 | panfrost_emit_streamout(struct panfrost_batch *batch, |
| 1325 | struct mali_attribute_buffer_packed *slot, |
Ilia Mirkin | 4c050f2 | 2020-08-09 00:13:14 -0400 | [diff] [blame] | 1326 | unsigned stride_words, unsigned count, |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1327 | struct pipe_stream_output_target *target) |
| 1328 | { |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1329 | unsigned stride = stride_words * 4; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1330 | unsigned max_size = target->buffer_size; |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1331 | unsigned expected_size = stride * count; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1332 | |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1333 | /* Grab the BO and bind it to the batch */ |
| 1334 | struct panfrost_bo *bo = pan_resource(target->buffer)->bo; |
| 1335 | |
| 1336 | /* Varyings are WRITE from the perspective of the VERTEX but READ from |
| 1337 | * the perspective of the TILER and FRAGMENT. |
| 1338 | */ |
| 1339 | panfrost_batch_add_bo(batch, bo, |
| 1340 | PAN_BO_ACCESS_SHARED | |
| 1341 | PAN_BO_ACCESS_RW | |
| 1342 | PAN_BO_ACCESS_VERTEX_TILER | |
| 1343 | PAN_BO_ACCESS_FRAGMENT); |
| 1344 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1345 | /* We will have an offset applied to get alignment */ |
Ilia Mirkin | 4c050f2 | 2020-08-09 00:13:14 -0400 | [diff] [blame] | 1346 | mali_ptr addr = bo->gpu + target->buffer_offset + (pan_so_target(target)->offset * stride); |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1347 | |
| 1348 | pan_pack(slot, ATTRIBUTE_BUFFER, cfg) { |
| 1349 | cfg.pointer = (addr & ~63); |
| 1350 | cfg.stride = stride; |
| 1351 | cfg.size = MIN2(max_size, expected_size) + (addr & 63); |
| 1352 | } |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1353 | } |
| 1354 | |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1355 | /* Helpers for manipulating stream out information so we can pack varyings |
| 1356 | * accordingly. Compute the src_offset for a given captured varying */ |
| 1357 | |
| 1358 | static struct pipe_stream_output * |
| 1359 | pan_get_so(struct pipe_stream_output_info *info, gl_varying_slot loc) |
| 1360 | { |
| 1361 | for (unsigned i = 0; i < info->num_outputs; ++i) { |
| 1362 | if (info->output[i].register_index == loc) |
| 1363 | return &info->output[i]; |
| 1364 | } |
| 1365 | |
| 1366 | unreachable("Varying not captured"); |
| 1367 | } |
| 1368 | |
Alyssa Rosenzweig | 24c3b95 | 2020-06-10 15:35:41 -0400 | [diff] [blame] | 1369 | static unsigned |
| 1370 | pan_varying_size(enum mali_format fmt) |
| 1371 | { |
| 1372 | unsigned type = MALI_EXTRACT_TYPE(fmt); |
| 1373 | unsigned chan = MALI_EXTRACT_CHANNELS(fmt); |
| 1374 | unsigned bits = MALI_EXTRACT_BITS(fmt); |
| 1375 | unsigned bpc = 0; |
| 1376 | |
| 1377 | if (bits == MALI_CHANNEL_FLOAT) { |
| 1378 | /* No doubles */ |
| 1379 | bool fp16 = (type == MALI_FORMAT_SINT); |
| 1380 | assert(fp16 || (type == MALI_FORMAT_UNORM)); |
| 1381 | |
| 1382 | bpc = fp16 ? 2 : 4; |
| 1383 | } else { |
| 1384 | assert(type >= MALI_FORMAT_SNORM && type <= MALI_FORMAT_SINT); |
| 1385 | |
| 1386 | /* See the enums */ |
| 1387 | bits = 1 << bits; |
| 1388 | assert(bits >= 8); |
| 1389 | bpc = bits / 8; |
| 1390 | } |
| 1391 | |
| 1392 | return bpc * chan; |
| 1393 | } |
| 1394 | |
Alyssa Rosenzweig | 258b80b | 2020-06-08 12:56:33 -0400 | [diff] [blame] | 1395 | /* Indices for named (non-XFB) varyings that are present. These are packed |
| 1396 | * tightly so they correspond to a bitfield present (P) indexed by (1 << |
| 1397 | * PAN_VARY_*). This has the nice property that you can lookup the buffer index |
| 1398 | * of a given special field given a shift S by: |
| 1399 | * |
| 1400 | * idx = popcount(P & ((1 << S) - 1)) |
| 1401 | * |
| 1402 | * That is... look at all of the varyings that come earlier and count them, the |
| 1403 | * count is the new index since plus one. Likewise, the total number of special |
| 1404 | * buffers required is simply popcount(P) |
| 1405 | */ |
| 1406 | |
| 1407 | enum pan_special_varying { |
| 1408 | PAN_VARY_GENERAL = 0, |
| 1409 | PAN_VARY_POSITION = 1, |
| 1410 | PAN_VARY_PSIZ = 2, |
| 1411 | PAN_VARY_PNTCOORD = 3, |
| 1412 | PAN_VARY_FACE = 4, |
| 1413 | PAN_VARY_FRAGCOORD = 5, |
| 1414 | |
| 1415 | /* Keep last */ |
| 1416 | PAN_VARY_MAX, |
| 1417 | }; |
| 1418 | |
| 1419 | /* Given a varying, figure out which index it correpsonds to */ |
| 1420 | |
| 1421 | static inline unsigned |
| 1422 | pan_varying_index(unsigned present, enum pan_special_varying v) |
| 1423 | { |
| 1424 | unsigned mask = (1 << v) - 1; |
| 1425 | return util_bitcount(present & mask); |
| 1426 | } |
| 1427 | |
| 1428 | /* Get the base offset for XFB buffers, which by convention come after |
| 1429 | * everything else. Wrapper function for semantic reasons; by construction this |
| 1430 | * is just popcount. */ |
| 1431 | |
| 1432 | static inline unsigned |
| 1433 | pan_xfb_base(unsigned present) |
| 1434 | { |
| 1435 | return util_bitcount(present); |
| 1436 | } |
| 1437 | |
Alyssa Rosenzweig | 3d04ebf | 2020-06-08 13:32:38 -0400 | [diff] [blame] | 1438 | /* Computes the present mask for varyings so we can start emitting varying records */ |
| 1439 | |
| 1440 | static inline unsigned |
| 1441 | pan_varying_present( |
| 1442 | struct panfrost_shader_state *vs, |
| 1443 | struct panfrost_shader_state *fs, |
Alyssa Rosenzweig | b17b6cc | 2020-08-26 11:22:47 -0400 | [diff] [blame] | 1444 | unsigned quirks, |
| 1445 | uint16_t point_coord_mask) |
Alyssa Rosenzweig | 3d04ebf | 2020-06-08 13:32:38 -0400 | [diff] [blame] | 1446 | { |
| 1447 | /* At the moment we always emit general and position buffers. Not |
| 1448 | * strictly necessary but usually harmless */ |
| 1449 | |
| 1450 | unsigned present = (1 << PAN_VARY_GENERAL) | (1 << PAN_VARY_POSITION); |
| 1451 | |
| 1452 | /* Enable special buffers by the shader info */ |
| 1453 | |
| 1454 | if (vs->writes_point_size) |
| 1455 | present |= (1 << PAN_VARY_PSIZ); |
| 1456 | |
| 1457 | if (fs->reads_point_coord) |
| 1458 | present |= (1 << PAN_VARY_PNTCOORD); |
| 1459 | |
| 1460 | if (fs->reads_face) |
| 1461 | present |= (1 << PAN_VARY_FACE); |
| 1462 | |
| 1463 | if (fs->reads_frag_coord && !(quirks & IS_BIFROST)) |
| 1464 | present |= (1 << PAN_VARY_FRAGCOORD); |
| 1465 | |
| 1466 | /* Also, if we have a point sprite, we need a point coord buffer */ |
| 1467 | |
| 1468 | for (unsigned i = 0; i < fs->varying_count; i++) { |
| 1469 | gl_varying_slot loc = fs->varyings_loc[i]; |
| 1470 | |
Alyssa Rosenzweig | b17b6cc | 2020-08-26 11:22:47 -0400 | [diff] [blame] | 1471 | if (util_varying_is_point_coord(loc, point_coord_mask)) |
Alyssa Rosenzweig | 3d04ebf | 2020-06-08 13:32:38 -0400 | [diff] [blame] | 1472 | present |= (1 << PAN_VARY_PNTCOORD); |
| 1473 | } |
| 1474 | |
| 1475 | return present; |
| 1476 | } |
| 1477 | |
Alyssa Rosenzweig | 0c0217d | 2020-06-08 13:45:17 -0400 | [diff] [blame] | 1478 | /* Emitters for varying records */ |
| 1479 | |
Alyssa Rosenzweig | b805cf9 | 2020-08-14 15:12:39 -0400 | [diff] [blame] | 1480 | static void |
| 1481 | pan_emit_vary(struct mali_attribute_packed *out, |
| 1482 | unsigned present, enum pan_special_varying buf, |
Alyssa Rosenzweig | 0c0217d | 2020-06-08 13:45:17 -0400 | [diff] [blame] | 1483 | unsigned quirks, enum mali_format format, |
| 1484 | unsigned offset) |
| 1485 | { |
| 1486 | unsigned nr_channels = MALI_EXTRACT_CHANNELS(format); |
Alyssa Rosenzweig | 668ec24 | 2020-08-11 22:26:03 -0400 | [diff] [blame] | 1487 | unsigned swizzle = quirks & HAS_SWIZZLES ? |
| 1488 | panfrost_get_default_swizzle(nr_channels) : |
| 1489 | panfrost_bifrost_swizzle(nr_channels); |
Alyssa Rosenzweig | 0c0217d | 2020-06-08 13:45:17 -0400 | [diff] [blame] | 1490 | |
Alyssa Rosenzweig | 59fa269 | 2020-08-14 15:23:10 -0400 | [diff] [blame] | 1491 | pan_pack(out, ATTRIBUTE, cfg) { |
| 1492 | cfg.buffer_index = pan_varying_index(present, buf); |
| 1493 | cfg.unknown = quirks & IS_BIFROST ? 0x0 : 0x1; |
| 1494 | cfg.format = (format << 12) | swizzle; |
| 1495 | cfg.offset = offset; |
| 1496 | } |
Alyssa Rosenzweig | 0c0217d | 2020-06-08 13:45:17 -0400 | [diff] [blame] | 1497 | } |
| 1498 | |
| 1499 | /* General varying that is unused */ |
| 1500 | |
Alyssa Rosenzweig | b805cf9 | 2020-08-14 15:12:39 -0400 | [diff] [blame] | 1501 | static void |
| 1502 | pan_emit_vary_only(struct mali_attribute_packed *out, |
| 1503 | unsigned present, unsigned quirks) |
Alyssa Rosenzweig | 0c0217d | 2020-06-08 13:45:17 -0400 | [diff] [blame] | 1504 | { |
Alyssa Rosenzweig | b805cf9 | 2020-08-14 15:12:39 -0400 | [diff] [blame] | 1505 | pan_emit_vary(out, present, 0, quirks, MALI_VARYING_DISCARD, 0); |
Alyssa Rosenzweig | 0c0217d | 2020-06-08 13:45:17 -0400 | [diff] [blame] | 1506 | } |
| 1507 | |
Alyssa Rosenzweig | df24209 | 2020-06-08 13:52:38 -0400 | [diff] [blame] | 1508 | /* Special records */ |
| 1509 | |
| 1510 | static const enum mali_format pan_varying_formats[PAN_VARY_MAX] = { |
| 1511 | [PAN_VARY_POSITION] = MALI_VARYING_POS, |
| 1512 | [PAN_VARY_PSIZ] = MALI_R16F, |
| 1513 | [PAN_VARY_PNTCOORD] = MALI_R16F, |
| 1514 | [PAN_VARY_FACE] = MALI_R32I, |
| 1515 | [PAN_VARY_FRAGCOORD] = MALI_RGBA32F |
| 1516 | }; |
| 1517 | |
Alyssa Rosenzweig | b805cf9 | 2020-08-14 15:12:39 -0400 | [diff] [blame] | 1518 | static void |
| 1519 | pan_emit_vary_special(struct mali_attribute_packed *out, |
| 1520 | unsigned present, enum pan_special_varying buf, |
Alyssa Rosenzweig | df24209 | 2020-06-08 13:52:38 -0400 | [diff] [blame] | 1521 | unsigned quirks) |
| 1522 | { |
| 1523 | assert(buf < PAN_VARY_MAX); |
Alyssa Rosenzweig | b805cf9 | 2020-08-14 15:12:39 -0400 | [diff] [blame] | 1524 | pan_emit_vary(out, present, buf, quirks, pan_varying_formats[buf], 0); |
Alyssa Rosenzweig | df24209 | 2020-06-08 13:52:38 -0400 | [diff] [blame] | 1525 | } |
| 1526 | |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1527 | static enum mali_format |
| 1528 | pan_xfb_format(enum mali_format format, unsigned nr) |
| 1529 | { |
| 1530 | if (MALI_EXTRACT_BITS(format) == MALI_CHANNEL_FLOAT) |
| 1531 | return MALI_R32F | MALI_NR_CHANNELS(nr); |
| 1532 | else |
| 1533 | return MALI_EXTRACT_TYPE(format) | MALI_NR_CHANNELS(nr) | MALI_CHANNEL_32; |
| 1534 | } |
| 1535 | |
| 1536 | /* Transform feedback records. Note struct pipe_stream_output is (if packed as |
| 1537 | * a bitfield) 32-bit, smaller than a 64-bit pointer, so may as well pass by |
| 1538 | * value. */ |
| 1539 | |
Alyssa Rosenzweig | b805cf9 | 2020-08-14 15:12:39 -0400 | [diff] [blame] | 1540 | static void |
| 1541 | pan_emit_vary_xfb(struct mali_attribute_packed *out, |
| 1542 | unsigned present, |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1543 | unsigned max_xfb, |
| 1544 | unsigned *streamout_offsets, |
| 1545 | unsigned quirks, |
| 1546 | enum mali_format format, |
| 1547 | struct pipe_stream_output o) |
| 1548 | { |
Alyssa Rosenzweig | 668ec24 | 2020-08-11 22:26:03 -0400 | [diff] [blame] | 1549 | unsigned swizzle = quirks & HAS_SWIZZLES ? |
| 1550 | panfrost_get_default_swizzle(o.num_components) : |
| 1551 | panfrost_bifrost_swizzle(o.num_components); |
| 1552 | |
Alyssa Rosenzweig | 6c85063 | 2020-08-14 15:21:20 -0400 | [diff] [blame] | 1553 | pan_pack(out, ATTRIBUTE, cfg) { |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1554 | /* XFB buffers come after everything else */ |
Alyssa Rosenzweig | 6c85063 | 2020-08-14 15:21:20 -0400 | [diff] [blame] | 1555 | cfg.buffer_index = pan_xfb_base(present) + o.output_buffer; |
| 1556 | cfg.unknown = quirks & IS_BIFROST ? 0x0 : 0x1; |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1557 | |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1558 | /* Override number of channels and precision to highp */ |
Alyssa Rosenzweig | 6c85063 | 2020-08-14 15:21:20 -0400 | [diff] [blame] | 1559 | cfg.format = (pan_xfb_format(format, o.num_components) << 12) | swizzle; |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1560 | |
| 1561 | /* Apply given offsets together */ |
Alyssa Rosenzweig | 6c85063 | 2020-08-14 15:21:20 -0400 | [diff] [blame] | 1562 | cfg.offset = (o.dst_offset * 4) /* dwords */ |
| 1563 | + streamout_offsets[o.output_buffer]; |
| 1564 | } |
Alyssa Rosenzweig | c31af6f | 2020-06-08 14:08:45 -0400 | [diff] [blame] | 1565 | } |
| 1566 | |
Alyssa Rosenzweig | e9e9b2b | 2020-06-10 15:13:12 -0400 | [diff] [blame] | 1567 | /* Determine if we should capture a varying for XFB. This requires actually |
| 1568 | * having a buffer for it. If we don't capture it, we'll fallback to a general |
| 1569 | * varying path (linked or unlinked, possibly discarding the write) */ |
| 1570 | |
| 1571 | static bool |
| 1572 | panfrost_xfb_captured(struct panfrost_shader_state *xfb, |
| 1573 | unsigned loc, unsigned max_xfb) |
| 1574 | { |
| 1575 | if (!(xfb->so_mask & (1ll << loc))) |
| 1576 | return false; |
| 1577 | |
| 1578 | struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); |
| 1579 | return o->output_buffer < max_xfb; |
| 1580 | } |
| 1581 | |
Alyssa Rosenzweig | b805cf9 | 2020-08-14 15:12:39 -0400 | [diff] [blame] | 1582 | static void |
Alyssa Rosenzweig | 40b4ee9 | 2020-08-14 15:19:25 -0400 | [diff] [blame] | 1583 | pan_emit_general_varying(struct mali_attribute_packed *out, |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1584 | struct panfrost_shader_state *other, |
| 1585 | struct panfrost_shader_state *xfb, |
Alyssa Rosenzweig | 40b4ee9 | 2020-08-14 15:19:25 -0400 | [diff] [blame] | 1586 | gl_varying_slot loc, |
| 1587 | enum mali_format format, |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1588 | unsigned present, |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1589 | unsigned quirks, |
| 1590 | unsigned *gen_offsets, |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1591 | enum mali_format *gen_formats, |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1592 | unsigned *gen_stride, |
| 1593 | unsigned idx, |
Alyssa Rosenzweig | 40b4ee9 | 2020-08-14 15:19:25 -0400 | [diff] [blame] | 1594 | bool should_alloc) |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1595 | { |
Alyssa Rosenzweig | 40b4ee9 | 2020-08-14 15:19:25 -0400 | [diff] [blame] | 1596 | /* Check if we're linked */ |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1597 | signed other_idx = -1; |
| 1598 | |
| 1599 | for (unsigned j = 0; j < other->varying_count; ++j) { |
| 1600 | if (other->varyings_loc[j] == loc) { |
| 1601 | other_idx = j; |
| 1602 | break; |
| 1603 | } |
| 1604 | } |
| 1605 | |
Alyssa Rosenzweig | b805cf9 | 2020-08-14 15:12:39 -0400 | [diff] [blame] | 1606 | if (other_idx < 0) { |
| 1607 | pan_emit_vary_only(out, present, quirks); |
| 1608 | return; |
| 1609 | } |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1610 | |
| 1611 | unsigned offset = gen_offsets[other_idx]; |
| 1612 | |
| 1613 | if (should_alloc) { |
| 1614 | /* We're linked, so allocate a space via a watermark allocation */ |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1615 | enum mali_format alt = other->varyings[other_idx]; |
| 1616 | |
| 1617 | /* Do interpolation at minimum precision */ |
| 1618 | unsigned size_main = pan_varying_size(format); |
| 1619 | unsigned size_alt = pan_varying_size(alt); |
| 1620 | unsigned size = MIN2(size_main, size_alt); |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1621 | |
| 1622 | /* If a varying is marked for XFB but not actually captured, we |
| 1623 | * should match the format to the format that would otherwise |
| 1624 | * be used for XFB, since dEQP checks for invariance here. It's |
| 1625 | * unclear if this is required by the spec. */ |
| 1626 | |
| 1627 | if (xfb->so_mask & (1ull << loc)) { |
| 1628 | struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); |
| 1629 | format = pan_xfb_format(format, o->num_components); |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1630 | size = pan_varying_size(format); |
| 1631 | } else if (size == size_alt) { |
| 1632 | format = alt; |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1633 | } |
| 1634 | |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1635 | gen_offsets[idx] = *gen_stride; |
| 1636 | gen_formats[other_idx] = format; |
| 1637 | offset = *gen_stride; |
| 1638 | *gen_stride += size; |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1639 | } |
| 1640 | |
Alyssa Rosenzweig | b805cf9 | 2020-08-14 15:12:39 -0400 | [diff] [blame] | 1641 | pan_emit_vary(out, present, PAN_VARY_GENERAL, quirks, format, offset); |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1642 | } |
| 1643 | |
Alyssa Rosenzweig | 40b4ee9 | 2020-08-14 15:19:25 -0400 | [diff] [blame] | 1644 | /* Higher-level wrapper around all of the above, classifying a varying into one |
| 1645 | * of the above types */ |
| 1646 | |
| 1647 | static void |
| 1648 | panfrost_emit_varying( |
| 1649 | struct mali_attribute_packed *out, |
| 1650 | struct panfrost_shader_state *stage, |
| 1651 | struct panfrost_shader_state *other, |
| 1652 | struct panfrost_shader_state *xfb, |
| 1653 | unsigned present, |
Alyssa Rosenzweig | b17b6cc | 2020-08-26 11:22:47 -0400 | [diff] [blame] | 1654 | uint16_t point_sprite_mask, |
Alyssa Rosenzweig | 40b4ee9 | 2020-08-14 15:19:25 -0400 | [diff] [blame] | 1655 | unsigned max_xfb, |
| 1656 | unsigned *streamout_offsets, |
| 1657 | unsigned quirks, |
| 1658 | unsigned *gen_offsets, |
| 1659 | enum mali_format *gen_formats, |
| 1660 | unsigned *gen_stride, |
| 1661 | unsigned idx, |
| 1662 | bool should_alloc, |
| 1663 | bool is_fragment) |
| 1664 | { |
| 1665 | gl_varying_slot loc = stage->varyings_loc[idx]; |
| 1666 | enum mali_format format = stage->varyings[idx]; |
| 1667 | |
| 1668 | /* Override format to match linkage */ |
| 1669 | if (!should_alloc && gen_formats[idx]) |
| 1670 | format = gen_formats[idx]; |
| 1671 | |
Alyssa Rosenzweig | b17b6cc | 2020-08-26 11:22:47 -0400 | [diff] [blame] | 1672 | if (util_varying_is_point_coord(loc, point_sprite_mask)) { |
Alyssa Rosenzweig | 40b4ee9 | 2020-08-14 15:19:25 -0400 | [diff] [blame] | 1673 | pan_emit_vary_special(out, present, PAN_VARY_PNTCOORD, quirks); |
| 1674 | } else if (panfrost_xfb_captured(xfb, loc, max_xfb)) { |
| 1675 | struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); |
| 1676 | pan_emit_vary_xfb(out, present, max_xfb, streamout_offsets, quirks, format, *o); |
| 1677 | } else if (loc == VARYING_SLOT_POS) { |
| 1678 | if (is_fragment) |
| 1679 | pan_emit_vary_special(out, present, PAN_VARY_FRAGCOORD, quirks); |
| 1680 | else |
| 1681 | pan_emit_vary_special(out, present, PAN_VARY_POSITION, quirks); |
| 1682 | } else if (loc == VARYING_SLOT_PSIZ) { |
| 1683 | pan_emit_vary_special(out, present, PAN_VARY_PSIZ, quirks); |
| 1684 | } else if (loc == VARYING_SLOT_PNTC) { |
| 1685 | pan_emit_vary_special(out, present, PAN_VARY_PNTCOORD, quirks); |
| 1686 | } else if (loc == VARYING_SLOT_FACE) { |
| 1687 | pan_emit_vary_special(out, present, PAN_VARY_FACE, quirks); |
| 1688 | } else { |
| 1689 | pan_emit_general_varying(out, other, xfb, loc, format, present, |
| 1690 | quirks, gen_offsets, gen_formats, gen_stride, |
| 1691 | idx, should_alloc); |
| 1692 | } |
| 1693 | } |
| 1694 | |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1695 | static void |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1696 | pan_emit_special_input(struct mali_attribute_buffer_packed *out, |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1697 | unsigned present, |
| 1698 | enum pan_special_varying v, |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1699 | unsigned special) |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1700 | { |
| 1701 | if (present & (1 << v)) { |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1702 | unsigned idx = pan_varying_index(present, v); |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1703 | |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1704 | pan_pack(out + idx, ATTRIBUTE_BUFFER, cfg) { |
| 1705 | cfg.special = special; |
| 1706 | cfg.type = 0; |
| 1707 | } |
Alyssa Rosenzweig | 6ab87c5 | 2020-06-08 15:29:05 -0400 | [diff] [blame] | 1708 | } |
| 1709 | } |
| 1710 | |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1711 | void |
| 1712 | panfrost_emit_varying_descriptor(struct panfrost_batch *batch, |
| 1713 | unsigned vertex_count, |
Alyssa Rosenzweig | e5c77cb | 2020-08-25 13:37:22 -0400 | [diff] [blame] | 1714 | mali_ptr *vs_attribs, |
| 1715 | mali_ptr *fs_attribs, |
| 1716 | mali_ptr *buffers, |
| 1717 | mali_ptr *position, |
| 1718 | mali_ptr *psiz) |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1719 | { |
| 1720 | /* Load the shaders */ |
| 1721 | struct panfrost_context *ctx = batch->ctx; |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1722 | struct panfrost_device *dev = pan_device(ctx->base.screen); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1723 | struct panfrost_shader_state *vs, *fs; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1724 | size_t vs_size, fs_size; |
| 1725 | |
| 1726 | /* Allocate the varying descriptor */ |
| 1727 | |
| 1728 | vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX); |
| 1729 | fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); |
Alyssa Rosenzweig | 7ef205d | 2020-08-14 15:23:51 -0400 | [diff] [blame] | 1730 | vs_size = MALI_ATTRIBUTE_LENGTH * vs->varying_count; |
| 1731 | fs_size = MALI_ATTRIBUTE_LENGTH * fs->varying_count; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1732 | |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 1733 | struct panfrost_transfer trans = panfrost_pool_alloc_aligned( |
| 1734 | &batch->pool, vs_size + fs_size, MALI_ATTRIBUTE_LENGTH); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1735 | |
| 1736 | struct pipe_stream_output_info *so = &vs->stream_output; |
Alyssa Rosenzweig | b17b6cc | 2020-08-26 11:22:47 -0400 | [diff] [blame] | 1737 | uint16_t point_coord_mask = ctx->rasterizer->base.sprite_coord_enable; |
| 1738 | unsigned present = pan_varying_present(vs, fs, dev->quirks, point_coord_mask); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1739 | |
| 1740 | /* Check if this varying is linked by us. This is the case for |
| 1741 | * general-purpose, non-captured varyings. If it is, link it. If it's |
| 1742 | * not, use the provided stream out information to determine the |
| 1743 | * offset, since it was already linked for us. */ |
| 1744 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1745 | unsigned gen_offsets[32]; |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1746 | enum mali_format gen_formats[32]; |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1747 | memset(gen_offsets, 0, sizeof(gen_offsets)); |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1748 | memset(gen_formats, 0, sizeof(gen_formats)); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1749 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1750 | unsigned gen_stride = 0; |
| 1751 | assert(vs->varying_count < ARRAY_SIZE(gen_offsets)); |
| 1752 | assert(fs->varying_count < ARRAY_SIZE(gen_offsets)); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1753 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1754 | unsigned streamout_offsets[32]; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1755 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1756 | for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) { |
| 1757 | streamout_offsets[i] = panfrost_streamout_offset( |
| 1758 | so->stride[i], |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1759 | ctx->streamout.targets[i]); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1760 | } |
| 1761 | |
Alyssa Rosenzweig | b805cf9 | 2020-08-14 15:12:39 -0400 | [diff] [blame] | 1762 | struct mali_attribute_packed *ovs = (struct mali_attribute_packed *)trans.cpu; |
| 1763 | struct mali_attribute_packed *ofs = ovs + vs->varying_count; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1764 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1765 | for (unsigned i = 0; i < vs->varying_count; i++) { |
Alyssa Rosenzweig | b17b6cc | 2020-08-26 11:22:47 -0400 | [diff] [blame] | 1766 | panfrost_emit_varying(ovs + i, vs, fs, vs, present, 0, |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1767 | ctx->streamout.num_targets, streamout_offsets, |
| 1768 | dev->quirks, |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1769 | gen_offsets, gen_formats, &gen_stride, i, true, false); |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1770 | } |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1771 | |
| 1772 | for (unsigned i = 0; i < fs->varying_count; i++) { |
Alyssa Rosenzweig | b17b6cc | 2020-08-26 11:22:47 -0400 | [diff] [blame] | 1773 | panfrost_emit_varying(ofs + i, fs, vs, vs, present, point_coord_mask, |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1774 | ctx->streamout.num_targets, streamout_offsets, |
| 1775 | dev->quirks, |
Alyssa Rosenzweig | a7f5246 | 2020-06-08 18:11:29 -0400 | [diff] [blame] | 1776 | gen_offsets, gen_formats, &gen_stride, i, false, true); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1777 | } |
| 1778 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1779 | unsigned xfb_base = pan_xfb_base(present); |
Alyssa Rosenzweig | 373a204 | 2020-08-17 14:27:57 -0400 | [diff] [blame] | 1780 | struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, |
| 1781 | MALI_ATTRIBUTE_BUFFER_LENGTH * (xfb_base + ctx->streamout.num_targets), |
Alyssa Rosenzweig | 1cfbc5c | 2020-08-20 13:36:46 -0400 | [diff] [blame] | 1782 | MALI_ATTRIBUTE_BUFFER_LENGTH * 2); |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1783 | struct mali_attribute_buffer_packed *varyings = |
| 1784 | (struct mali_attribute_buffer_packed *) T.cpu; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1785 | |
| 1786 | /* Emit the stream out buffers */ |
| 1787 | |
| 1788 | unsigned out_count = u_stream_outputs_for_vertices(ctx->active_prim, |
| 1789 | ctx->vertex_count); |
| 1790 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1791 | for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) { |
| 1792 | panfrost_emit_streamout(batch, &varyings[xfb_base + i], |
| 1793 | so->stride[i], |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1794 | out_count, |
| 1795 | ctx->streamout.targets[i]); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1796 | } |
| 1797 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1798 | panfrost_emit_varyings(batch, |
| 1799 | &varyings[pan_varying_index(present, PAN_VARY_GENERAL)], |
| 1800 | gen_stride, vertex_count); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1801 | |
| 1802 | /* fp32 vec4 gl_Position */ |
Alyssa Rosenzweig | e5c77cb | 2020-08-25 13:37:22 -0400 | [diff] [blame] | 1803 | *position = panfrost_emit_varyings(batch, |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1804 | &varyings[pan_varying_index(present, PAN_VARY_POSITION)], |
| 1805 | sizeof(float) * 4, vertex_count); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1806 | |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1807 | if (present & (1 << PAN_VARY_PSIZ)) { |
Alyssa Rosenzweig | e5c77cb | 2020-08-25 13:37:22 -0400 | [diff] [blame] | 1808 | *psiz = panfrost_emit_varyings(batch, |
Alyssa Rosenzweig | 79e349a | 2020-06-04 15:45:34 -0400 | [diff] [blame] | 1809 | &varyings[pan_varying_index(present, PAN_VARY_PSIZ)], |
| 1810 | 2, vertex_count); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1811 | } |
| 1812 | |
Alyssa Rosenzweig | ec58cda | 2020-08-14 15:50:13 -0400 | [diff] [blame] | 1813 | pan_emit_special_input(varyings, present, PAN_VARY_PNTCOORD, MALI_ATTRIBUTE_SPECIAL_POINT_COORD); |
| 1814 | pan_emit_special_input(varyings, present, PAN_VARY_FACE, MALI_ATTRIBUTE_SPECIAL_FRONT_FACING); |
| 1815 | pan_emit_special_input(varyings, present, PAN_VARY_FRAGCOORD, MALI_ATTRIBUTE_SPECIAL_FRAG_COORD); |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1816 | |
Alyssa Rosenzweig | e5c77cb | 2020-08-25 13:37:22 -0400 | [diff] [blame] | 1817 | *buffers = T.gpu; |
| 1818 | *vs_attribs = trans.gpu; |
| 1819 | *fs_attribs = trans.gpu + vs_size; |
Boris Brezillon | 836686d | 2020-03-06 09:45:31 +0100 | [diff] [blame] | 1820 | } |
| 1821 | |
Boris Brezillon | b95530b | 2020-03-06 09:09:03 +0100 | [diff] [blame] | 1822 | void |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 1823 | panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch, |
Boris Brezillon | 6b92303 | 2020-09-08 20:32:41 +0200 | [diff] [blame] | 1824 | const struct panfrost_transfer *vertex_job, |
| 1825 | const struct panfrost_transfer *tiler_job) |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 1826 | { |
| 1827 | struct panfrost_context *ctx = batch->ctx; |
Alyssa Rosenzweig | 31197c2 | 2020-07-07 17:07:34 -0400 | [diff] [blame] | 1828 | bool wallpapering = ctx->wallpaper_batch && batch->scoreboard.tiler_dep; |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 1829 | |
| 1830 | if (wallpapering) { |
| 1831 | /* Inject in reverse order, with "predicted" job indices. |
| 1832 | * THIS IS A HACK XXX */ |
Boris Brezillon | 6b92303 | 2020-09-08 20:32:41 +0200 | [diff] [blame] | 1833 | |
| 1834 | panfrost_add_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false, |
| 1835 | batch->scoreboard.job_index + 2, tiler_job, true); |
| 1836 | panfrost_add_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0, |
| 1837 | vertex_job, true); |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 1838 | return; |
| 1839 | } |
| 1840 | |
| 1841 | /* If rasterizer discard is enable, only submit the vertex */ |
| 1842 | |
Boris Brezillon | 6b92303 | 2020-09-08 20:32:41 +0200 | [diff] [blame] | 1843 | unsigned vertex = panfrost_add_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0, |
| 1844 | vertex_job, false); |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 1845 | |
Alyssa Rosenzweig | ec35159 | 2020-08-14 17:50:44 -0400 | [diff] [blame] | 1846 | if (ctx->rasterizer->base.rasterizer_discard) |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 1847 | return; |
| 1848 | |
Boris Brezillon | 6b92303 | 2020-09-08 20:32:41 +0200 | [diff] [blame] | 1849 | panfrost_add_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false, vertex, tiler_job, false); |
Boris Brezillon | 528384c | 2020-03-05 18:53:08 +0100 | [diff] [blame] | 1850 | } |
Alyssa Rosenzweig | 0a9fa4b | 2020-04-06 19:44:58 -0400 | [diff] [blame] | 1851 | |
| 1852 | /* TODO: stop hardcoding this */ |
| 1853 | mali_ptr |
| 1854 | panfrost_emit_sample_locations(struct panfrost_batch *batch) |
| 1855 | { |
| 1856 | uint16_t locations[] = { |
| 1857 | 128, 128, |
| 1858 | 0, 256, |
| 1859 | 0, 256, |
| 1860 | 0, 256, |
| 1861 | 0, 256, |
| 1862 | 0, 256, |
| 1863 | 0, 256, |
| 1864 | 0, 256, |
| 1865 | 0, 256, |
| 1866 | 0, 256, |
| 1867 | 0, 256, |
| 1868 | 0, 256, |
| 1869 | 0, 256, |
| 1870 | 0, 256, |
| 1871 | 0, 256, |
| 1872 | 0, 256, |
| 1873 | 0, 256, |
| 1874 | 0, 256, |
| 1875 | 0, 256, |
| 1876 | 0, 256, |
| 1877 | 0, 256, |
| 1878 | 0, 256, |
| 1879 | 0, 256, |
| 1880 | 0, 256, |
| 1881 | 0, 256, |
| 1882 | 0, 256, |
| 1883 | 0, 256, |
| 1884 | 0, 256, |
| 1885 | 0, 256, |
| 1886 | 0, 256, |
| 1887 | 0, 256, |
| 1888 | 0, 256, |
| 1889 | 128, 128, |
| 1890 | 0, 0, |
| 1891 | 0, 0, |
| 1892 | 0, 0, |
| 1893 | 0, 0, |
| 1894 | 0, 0, |
| 1895 | 0, 0, |
| 1896 | 0, 0, |
| 1897 | 0, 0, |
| 1898 | 0, 0, |
| 1899 | 0, 0, |
| 1900 | 0, 0, |
| 1901 | 0, 0, |
| 1902 | 0, 0, |
| 1903 | 0, 0, |
| 1904 | 0, 0, |
| 1905 | }; |
| 1906 | |
Alyssa Rosenzweig | 1cfbc5c | 2020-08-20 13:36:46 -0400 | [diff] [blame] | 1907 | return panfrost_pool_upload_aligned(&batch->pool, locations, 96 * sizeof(uint16_t), 64); |
Alyssa Rosenzweig | 0a9fa4b | 2020-04-06 19:44:58 -0400 | [diff] [blame] | 1908 | } |