Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * on the rights to use, copy, modify, merge, publish, distribute, sub |
| 8 | * license, and/or sell copies of the Software, and to permit persons to whom |
| 9 | * the Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 19 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 20 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 21 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Christian König <christian.koenig@amd.com> |
| 25 | */ |
| 26 | |
Andreas Hartmetz | 786af2f | 2014-01-04 18:44:33 +0100 | [diff] [blame] | 27 | #include "si_pipe.h" |
| 28 | #include "si_shader.h" |
Emil Velikov | a131263 | 2014-08-16 17:58:25 +0100 | [diff] [blame] | 29 | #include "radeon/r600_cs.h" |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 30 | #include "sid.h" |
| 31 | |
Marek Olšák | 7209703 | 2014-01-22 18:50:36 +0100 | [diff] [blame] | 32 | #include "util/u_index_modify.h" |
Marek Olšák | 7209703 | 2014-01-22 18:50:36 +0100 | [diff] [blame] | 33 | #include "util/u_upload_mgr.h" |
| 34 | |
Marek Olšák | 20e570d | 2014-12-07 17:53:56 +0100 | [diff] [blame] | 35 | static void si_decompress_textures(struct si_context *sctx) |
Michel Dänzer | 404b29d | 2013-11-21 16:45:28 +0900 | [diff] [blame] | 36 | { |
Marek Olšák | 20e570d | 2014-12-07 17:53:56 +0100 | [diff] [blame] | 37 | if (!sctx->blitter->running) { |
| 38 | /* Flush depth textures which need to be flushed. */ |
| 39 | for (int i = 0; i < SI_NUM_SHADERS; i++) { |
| 40 | if (sctx->samplers[i].depth_texture_mask) { |
| 41 | si_flush_depth_textures(sctx, &sctx->samplers[i]); |
Tom Stellard | 0fb1e68 | 2012-09-06 16:18:11 -0400 | [diff] [blame] | 42 | } |
Marek Olšák | 20e570d | 2014-12-07 17:53:56 +0100 | [diff] [blame] | 43 | if (sctx->samplers[i].compressed_colortex_mask) { |
| 44 | si_decompress_color_textures(sctx, &sctx->samplers[i]); |
| 45 | } |
Tom Stellard | 0fb1e68 | 2012-09-06 16:18:11 -0400 | [diff] [blame] | 46 | } |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 47 | } |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 48 | } |
| 49 | |
Marek Olšák | 508c1ca | 2014-12-07 16:02:07 +0100 | [diff] [blame] | 50 | static unsigned si_conv_pipe_prim(unsigned mode) |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 51 | { |
| 52 | static const unsigned prim_conv[] = { |
| 53 | [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST, |
| 54 | [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST, |
| 55 | [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP, |
| 56 | [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP, |
| 57 | [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST, |
| 58 | [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP, |
| 59 | [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN, |
| 60 | [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST, |
| 61 | [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP, |
| 62 | [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON, |
Michel Dänzer | 2863071 | 2014-01-09 16:35:46 +0900 | [diff] [blame] | 63 | [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ, |
| 64 | [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ, |
| 65 | [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ, |
Marek Olšák | db51ab6 | 2014-08-18 00:55:40 +0200 | [diff] [blame] | 66 | [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ, |
| 67 | [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 68 | }; |
Marek Olšák | 508c1ca | 2014-12-07 16:02:07 +0100 | [diff] [blame] | 69 | assert(mode < Elements(prim_conv)); |
| 70 | return prim_conv[mode]; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 71 | } |
| 72 | |
Andreas Hartmetz | b902298 | 2014-01-07 03:18:25 +0100 | [diff] [blame] | 73 | static unsigned si_conv_prim_to_gs_out(unsigned mode) |
Marek Olšák | e4c5d3e | 2013-08-18 03:05:34 +0200 | [diff] [blame] | 74 | { |
| 75 | static const int prim_conv[] = { |
| 76 | [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST, |
| 77 | [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, |
| 78 | [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, |
| 79 | [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, |
| 80 | [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 81 | [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 82 | [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 83 | [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 84 | [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 85 | [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 86 | [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, |
| 87 | [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, |
| 88 | [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
Marek Olšák | db51ab6 | 2014-08-18 00:55:40 +0200 | [diff] [blame] | 89 | [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 90 | [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP |
Marek Olšák | e4c5d3e | 2013-08-18 03:05:34 +0200 | [diff] [blame] | 91 | }; |
| 92 | assert(mode < Elements(prim_conv)); |
| 93 | |
| 94 | return prim_conv[mode]; |
| 95 | } |
| 96 | |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 97 | static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx, |
| 98 | const struct pipe_draw_info *info) |
| 99 | { |
| 100 | struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; |
| 101 | unsigned prim = info->mode; |
Marek Olšák | f62f882 | 2014-08-18 23:14:34 +0200 | [diff] [blame] | 102 | unsigned primgroup_size = 128; /* recommended without a GS */ |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 103 | |
| 104 | /* SWITCH_ON_EOP(0) is always preferable. */ |
| 105 | bool wd_switch_on_eop = false; |
| 106 | bool ia_switch_on_eop = false; |
Marek Olšák | 4be7ff5 | 2014-08-15 22:45:10 +0200 | [diff] [blame] | 107 | bool partial_vs_wave = false; |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 108 | |
Marek Olšák | f62f882 | 2014-08-18 23:14:34 +0200 | [diff] [blame] | 109 | if (sctx->gs_shader) |
| 110 | primgroup_size = 64; /* recommended with a GS */ |
| 111 | |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 112 | /* This is a hardware requirement. */ |
| 113 | if ((rs && rs->line_stipple_enable) || |
| 114 | (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) { |
| 115 | ia_switch_on_eop = true; |
| 116 | wd_switch_on_eop = true; |
| 117 | } |
| 118 | |
Marek Olšák | 4be7ff5 | 2014-08-15 22:45:10 +0200 | [diff] [blame] | 119 | if (sctx->b.streamout.streamout_enabled || |
| 120 | sctx->b.streamout.prims_gen_query_enabled) |
| 121 | partial_vs_wave = true; |
| 122 | |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 123 | if (sctx->b.chip_class >= CIK) { |
| 124 | /* WD_SWITCH_ON_EOP has no effect on GPUs with less than |
| 125 | * 4 shader engines. Set 1 to pass the assertion below. |
| 126 | * The other cases are hardware requirements. */ |
| 127 | if (sctx->b.screen->info.max_se < 4 || |
| 128 | prim == PIPE_PRIM_POLYGON || |
| 129 | prim == PIPE_PRIM_LINE_LOOP || |
| 130 | prim == PIPE_PRIM_TRIANGLE_FAN || |
| 131 | prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY || |
| 132 | info->primitive_restart) |
| 133 | wd_switch_on_eop = true; |
| 134 | |
| 135 | /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0. |
| 136 | * We don't know that for indirect drawing, so treat it as |
| 137 | * always problematic. */ |
| 138 | if (sctx->b.family == CHIP_HAWAII && |
| 139 | (info->indirect || info->instance_count > 1)) |
| 140 | wd_switch_on_eop = true; |
| 141 | |
| 142 | /* If the WD switch is false, the IA switch must be false too. */ |
| 143 | assert(wd_switch_on_eop || !ia_switch_on_eop); |
| 144 | } |
| 145 | |
| 146 | return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | |
Marek Olšák | 4be7ff5 | 2014-08-15 22:45:10 +0200 | [diff] [blame] | 147 | S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) | |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 148 | S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) | |
| 149 | S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0); |
| 150 | } |
| 151 | |
Marek Olšák | 1fe7ba8 | 2015-01-31 20:09:46 +0100 | [diff] [blame] | 152 | /* rast_prim is the primitive type after GS. */ |
Marek Olšák | fdf2c04 | 2015-02-22 17:42:20 +0100 | [diff] [blame] | 153 | static void si_emit_rasterizer_prim_state(struct si_context *sctx) |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 154 | { |
| 155 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
Marek Olšák | fdf2c04 | 2015-02-22 17:42:20 +0100 | [diff] [blame] | 156 | unsigned rast_prim = sctx->current_rast_prim; |
Marek Olšák | 1f4bb38 | 2015-03-15 19:21:31 +0100 | [diff] [blame] | 157 | struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer; |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 158 | |
Marek Olšák | 567c8d7 | 2015-03-15 19:24:13 +0100 | [diff] [blame^] | 159 | /* Skip this if not rendering lines. */ |
| 160 | if (rast_prim != PIPE_PRIM_LINES && |
| 161 | rast_prim != PIPE_PRIM_LINE_LOOP && |
| 162 | rast_prim != PIPE_PRIM_LINE_STRIP && |
| 163 | rast_prim != PIPE_PRIM_LINES_ADJACENCY && |
| 164 | rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY) |
| 165 | return; |
| 166 | |
Marek Olšák | 1f4bb38 | 2015-03-15 19:21:31 +0100 | [diff] [blame] | 167 | if (rast_prim == sctx->last_rast_prim && |
| 168 | rs->pa_sc_line_stipple == sctx->last_sc_line_stipple) |
Marek Olšák | 3291eed | 2014-12-08 13:35:36 +0100 | [diff] [blame] | 169 | return; |
| 170 | |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 171 | r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE, |
Marek Olšák | 1f4bb38 | 2015-03-15 19:21:31 +0100 | [diff] [blame] | 172 | rs->pa_sc_line_stipple | |
Marek Olšák | 1fe7ba8 | 2015-01-31 20:09:46 +0100 | [diff] [blame] | 173 | S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : |
| 174 | rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0)); |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 175 | |
Marek Olšák | 1fe7ba8 | 2015-01-31 20:09:46 +0100 | [diff] [blame] | 176 | sctx->last_rast_prim = rast_prim; |
Marek Olšák | 1f4bb38 | 2015-03-15 19:21:31 +0100 | [diff] [blame] | 177 | sctx->last_sc_line_stipple = rs->pa_sc_line_stipple; |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | static void si_emit_draw_registers(struct si_context *sctx, |
Marek Olšák | fdf2c04 | 2015-02-22 17:42:20 +0100 | [diff] [blame] | 181 | const struct pipe_draw_info *info) |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 182 | { |
| 183 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
| 184 | unsigned prim = si_conv_pipe_prim(info->mode); |
Marek Olšák | fdf2c04 | 2015-02-22 17:42:20 +0100 | [diff] [blame] | 185 | unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim); |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 186 | unsigned ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info); |
| 187 | |
| 188 | /* Draw state. */ |
Marek Olšák | 834bee4 | 2014-12-07 20:23:56 +0100 | [diff] [blame] | 189 | if (prim != sctx->last_prim || |
| 190 | ia_multi_vgt_param != sctx->last_multi_vgt_param) { |
| 191 | if (sctx->b.chip_class >= CIK) { |
| 192 | radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0)); |
| 193 | radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */ |
| 194 | radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */ |
| 195 | radeon_emit(cs, 0); /* VGT_LS_HS_CONFIG */ |
| 196 | } else { |
| 197 | r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim); |
| 198 | r600_write_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); |
| 199 | } |
| 200 | sctx->last_prim = prim; |
| 201 | sctx->last_multi_vgt_param = ia_multi_vgt_param; |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 202 | } |
| 203 | |
Marek Olšák | 6fde194 | 2014-12-07 20:15:49 +0100 | [diff] [blame] | 204 | if (gs_out_prim != sctx->last_gs_out_prim) { |
| 205 | r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim); |
| 206 | sctx->last_gs_out_prim = gs_out_prim; |
| 207 | } |
Marek Olšák | 3435013 | 2014-12-07 20:14:41 +0100 | [diff] [blame] | 208 | |
| 209 | /* Primitive restart. */ |
| 210 | if (info->primitive_restart != sctx->last_primitive_restart_en) { |
| 211 | r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart); |
| 212 | sctx->last_primitive_restart_en = info->primitive_restart; |
| 213 | |
| 214 | if (info->primitive_restart && |
| 215 | (info->restart_index != sctx->last_restart_index || |
| 216 | sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) { |
| 217 | r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, |
| 218 | info->restart_index); |
| 219 | sctx->last_restart_index = info->restart_index; |
| 220 | } |
| 221 | } |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 222 | } |
| 223 | |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 224 | static void si_emit_draw_packets(struct si_context *sctx, |
| 225 | const struct pipe_draw_info *info, |
| 226 | const struct pipe_index_buffer *ib) |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 227 | { |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 228 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
Marek Olšák | 09056b3 | 2014-04-23 16:15:36 +0200 | [diff] [blame] | 229 | unsigned sh_base_reg = (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : |
| 230 | R_00B130_SPI_SHADER_USER_DATA_VS_0); |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 231 | |
Marek Olšák | 9d16e70 | 2013-08-26 18:17:09 +0200 | [diff] [blame] | 232 | if (info->count_from_stream_output) { |
| 233 | struct r600_so_target *t = |
| 234 | (struct r600_so_target*)info->count_from_stream_output; |
Marek Olšák | 1c03a69 | 2014-08-06 22:29:27 +0200 | [diff] [blame] | 235 | uint64_t va = t->buf_filled_size->gpu_address + |
| 236 | t->buf_filled_size_offset; |
Marek Olšák | 9d16e70 | 2013-08-26 18:17:09 +0200 | [diff] [blame] | 237 | |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 238 | r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, |
| 239 | t->stride_in_dw); |
Marek Olšák | 9d16e70 | 2013-08-26 18:17:09 +0200 | [diff] [blame] | 240 | |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 241 | radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); |
| 242 | radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) | |
| 243 | COPY_DATA_DST_SEL(COPY_DATA_REG) | |
| 244 | COPY_DATA_WR_CONFIRM); |
| 245 | radeon_emit(cs, va); /* src address lo */ |
| 246 | radeon_emit(cs, va >> 32); /* src address hi */ |
| 247 | radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); |
| 248 | radeon_emit(cs, 0); /* unused */ |
| 249 | |
| 250 | r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, |
| 251 | t->buf_filled_size, RADEON_USAGE_READ, |
| 252 | RADEON_PRIO_MIN); |
Marek Olšák | 9d16e70 | 2013-08-26 18:17:09 +0200 | [diff] [blame] | 253 | } |
| 254 | |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 255 | /* draw packet */ |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 256 | if (info->indexed) { |
| 257 | radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); |
| 258 | |
| 259 | if (ib->index_size == 4) { |
| 260 | radeon_emit(cs, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ? |
| 261 | V_028A7C_VGT_DMA_SWAP_32_BIT : 0)); |
| 262 | } else { |
| 263 | radeon_emit(cs, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ? |
| 264 | V_028A7C_VGT_DMA_SWAP_16_BIT : 0)); |
| 265 | } |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 266 | } |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 267 | |
Marek Olšák | 09056b3 | 2014-04-23 16:15:36 +0200 | [diff] [blame] | 268 | if (!info->indirect) { |
Marek Olšák | 3382036 | 2014-12-07 20:04:40 +0100 | [diff] [blame] | 269 | int base_vertex; |
| 270 | |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 271 | radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); |
| 272 | radeon_emit(cs, info->instance_count); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 273 | |
Marek Olšák | 3382036 | 2014-12-07 20:04:40 +0100 | [diff] [blame] | 274 | /* Base vertex and start instance. */ |
| 275 | base_vertex = info->indexed ? info->index_bias : info->start; |
| 276 | |
| 277 | if (base_vertex != sctx->last_base_vertex || |
| 278 | sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN || |
| 279 | info->start_instance != sctx->last_start_instance || |
| 280 | sh_base_reg != sctx->last_sh_base_reg) { |
| 281 | si_write_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2); |
| 282 | radeon_emit(cs, base_vertex); |
| 283 | radeon_emit(cs, info->start_instance); |
| 284 | |
| 285 | sctx->last_base_vertex = base_vertex; |
| 286 | sctx->last_start_instance = info->start_instance; |
| 287 | sctx->last_sh_base_reg = sh_base_reg; |
| 288 | } |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 289 | } else { |
Marek Olšák | 3382036 | 2014-12-07 20:04:40 +0100 | [diff] [blame] | 290 | si_invalidate_draw_sh_constants(sctx); |
| 291 | |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 292 | r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, |
| 293 | (struct r600_resource *)info->indirect, |
| 294 | RADEON_USAGE_READ, RADEON_PRIO_MIN); |
Marek Olšák | 09056b3 | 2014-04-23 16:15:36 +0200 | [diff] [blame] | 295 | } |
| 296 | |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 297 | if (info->indexed) { |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 298 | uint32_t index_max_size = (ib->buffer->width0 - ib->offset) / |
| 299 | ib->index_size; |
| 300 | uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset; |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 301 | |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 302 | r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, |
| 303 | (struct r600_resource *)ib->buffer, |
| 304 | RADEON_USAGE_READ, RADEON_PRIO_MIN); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 305 | |
| 306 | if (info->indirect) { |
Marek Olšák | 1c03a69 | 2014-08-06 22:29:27 +0200 | [diff] [blame] | 307 | uint64_t indirect_va = r600_resource(info->indirect)->gpu_address; |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 308 | |
| 309 | assert(indirect_va % 8 == 0); |
| 310 | assert(index_va % 2 == 0); |
| 311 | assert(info->indirect_offset % 4 == 0); |
| 312 | |
| 313 | radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); |
| 314 | radeon_emit(cs, 1); |
| 315 | radeon_emit(cs, indirect_va); |
| 316 | radeon_emit(cs, indirect_va >> 32); |
| 317 | |
| 318 | radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0)); |
| 319 | radeon_emit(cs, index_va); |
| 320 | radeon_emit(cs, index_va >> 32); |
| 321 | |
| 322 | radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0)); |
| 323 | radeon_emit(cs, index_max_size); |
| 324 | |
| 325 | radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, sctx->b.predicate_drawing)); |
| 326 | radeon_emit(cs, info->indirect_offset); |
| 327 | radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); |
| 328 | radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); |
| 329 | radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 330 | } else { |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 331 | index_va += info->start * ib->index_size; |
| 332 | |
| 333 | radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, sctx->b.predicate_drawing)); |
| 334 | radeon_emit(cs, index_max_size); |
| 335 | radeon_emit(cs, index_va); |
| 336 | radeon_emit(cs, (index_va >> 32UL) & 0xFF); |
| 337 | radeon_emit(cs, info->count); |
| 338 | radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 339 | } |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 340 | } else { |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 341 | if (info->indirect) { |
Marek Olšák | 1c03a69 | 2014-08-06 22:29:27 +0200 | [diff] [blame] | 342 | uint64_t indirect_va = r600_resource(info->indirect)->gpu_address; |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 343 | |
| 344 | assert(indirect_va % 8 == 0); |
| 345 | assert(info->indirect_offset % 4 == 0); |
| 346 | |
| 347 | radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); |
| 348 | radeon_emit(cs, 1); |
| 349 | radeon_emit(cs, indirect_va); |
| 350 | radeon_emit(cs, indirect_va >> 32); |
| 351 | |
| 352 | radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, sctx->b.predicate_drawing)); |
| 353 | radeon_emit(cs, info->indirect_offset); |
| 354 | radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); |
| 355 | radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); |
| 356 | radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 357 | } else { |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 358 | radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, sctx->b.predicate_drawing)); |
| 359 | radeon_emit(cs, info->count); |
| 360 | radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX | |
| 361 | S_0287F0_USE_OPAQUE(!!info->count_from_stream_output)); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 362 | } |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 363 | } |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 364 | } |
| 365 | |
Marek Olšák | 73c2b0d | 2014-12-28 23:11:38 +0100 | [diff] [blame] | 366 | #define BOTH_ICACHE_KCACHE (SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_KCACHE) |
| 367 | |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 368 | void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom) |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 369 | { |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 370 | struct radeon_winsys_cs *cs = sctx->rings.gfx.cs; |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 371 | uint32_t cp_coher_cntl = 0; |
Marek Olšák | 604b58b | 2014-09-20 11:48:58 +0200 | [diff] [blame] | 372 | uint32_t compute = |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 373 | PKT3_SHADER_TYPE_S(!!(sctx->flags & SI_CONTEXT_FLAG_COMPUTE)); |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 374 | |
Marek Olšák | 73c2b0d | 2014-12-28 23:11:38 +0100 | [diff] [blame] | 375 | /* SI has a bug that it always flushes ICACHE and KCACHE if either |
Marek Olšák | 7692704 | 2015-02-19 13:03:54 +0100 | [diff] [blame] | 376 | * bit is set. An alternative way is to write SQC_CACHES, but that |
| 377 | * doesn't seem to work reliably. Since the bug doesn't affect |
| 378 | * correctness (it only does more work than necessary) and |
| 379 | * the performance impact is likely negligible, there is no plan |
| 380 | * to fix it. |
| 381 | */ |
| 382 | |
| 383 | if (sctx->flags & SI_CONTEXT_INV_ICACHE) |
| 384 | cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1); |
| 385 | if (sctx->flags & SI_CONTEXT_INV_KCACHE) |
| 386 | cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1); |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 387 | |
Marek Olšák | ca9c5b2 | 2014-12-30 16:45:51 +0100 | [diff] [blame] | 388 | if (sctx->flags & SI_CONTEXT_INV_TC_L1) |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 389 | cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1); |
Marek Olšák | ca9c5b2 | 2014-12-30 16:45:51 +0100 | [diff] [blame] | 390 | if (sctx->flags & SI_CONTEXT_INV_TC_L2) |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 391 | cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1); |
| 392 | |
| 393 | if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) { |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 394 | cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) | |
| 395 | S_0085F0_CB0_DEST_BASE_ENA(1) | |
| 396 | S_0085F0_CB1_DEST_BASE_ENA(1) | |
| 397 | S_0085F0_CB2_DEST_BASE_ENA(1) | |
| 398 | S_0085F0_CB3_DEST_BASE_ENA(1) | |
| 399 | S_0085F0_CB4_DEST_BASE_ENA(1) | |
| 400 | S_0085F0_CB5_DEST_BASE_ENA(1) | |
| 401 | S_0085F0_CB6_DEST_BASE_ENA(1) | |
| 402 | S_0085F0_CB7_DEST_BASE_ENA(1); |
| 403 | } |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 404 | if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) { |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 405 | cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) | |
| 406 | S_0085F0_DB_DEST_BASE_ENA(1); |
| 407 | } |
| 408 | |
Marek Olšák | d8185aa | 2014-12-30 18:41:25 +0100 | [diff] [blame] | 409 | if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) { |
| 410 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 411 | radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); |
| 412 | } |
| 413 | if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) { |
| 414 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 415 | radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); |
| 416 | } |
| 417 | if (sctx->flags & SI_CONTEXT_FLUSH_WITH_INV_L2) { |
| 418 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 419 | radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) | EVENT_INDEX(7) | |
| 420 | EVENT_WRITE_INV_L2); |
| 421 | } |
| 422 | |
| 423 | /* FLUSH_AND_INV events must be emitted before PS_PARTIAL_FLUSH. |
| 424 | * Otherwise, clearing CMASK (CB meta) with CP DMA isn't reliable. |
| 425 | * |
| 426 | * I think the reason is that FLUSH_AND_INV is only added to a queue |
| 427 | * and it is PS_PARTIAL_FLUSH that waits for it to complete. |
| 428 | */ |
| 429 | if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) { |
| 430 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 431 | radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); |
| 432 | } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) { |
| 433 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 434 | radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); |
| 435 | } |
| 436 | if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) { |
| 437 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 438 | radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4))); |
| 439 | } |
| 440 | if (sctx->flags & SI_CONTEXT_VGT_FLUSH) { |
| 441 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 442 | radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); |
| 443 | } |
| 444 | if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) { |
| 445 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 446 | radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0)); |
| 447 | } |
| 448 | |
| 449 | /* SURFACE_SYNC must be emitted after partial flushes. |
| 450 | * It looks like SURFACE_SYNC flushes caches immediately and doesn't |
| 451 | * wait for any engines. This should be last. |
| 452 | */ |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 453 | if (cp_coher_cntl) { |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 454 | if (sctx->chip_class >= CIK) { |
Marek Olšák | 604b58b | 2014-09-20 11:48:58 +0200 | [diff] [blame] | 455 | radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute); |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 456 | radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ |
| 457 | radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ |
| 458 | radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */ |
| 459 | radeon_emit(cs, 0); /* CP_COHER_BASE */ |
| 460 | radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ |
| 461 | radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ |
| 462 | } else { |
Marek Olšák | 604b58b | 2014-09-20 11:48:58 +0200 | [diff] [blame] | 463 | radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0) | compute); |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 464 | radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ |
| 465 | radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ |
| 466 | radeon_emit(cs, 0); /* CP_COHER_BASE */ |
| 467 | radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ |
| 468 | } |
| 469 | } |
| 470 | |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 471 | sctx->flags = 0; |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 472 | } |
| 473 | |
Marek Olšák | 73c2b0d | 2014-12-28 23:11:38 +0100 | [diff] [blame] | 474 | const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 24 }; /* number of CS dwords */ |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 475 | |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 476 | static void si_get_draw_start_count(struct si_context *sctx, |
| 477 | const struct pipe_draw_info *info, |
| 478 | unsigned *start, unsigned *count) |
| 479 | { |
| 480 | if (info->indirect) { |
| 481 | struct r600_resource *indirect = |
| 482 | (struct r600_resource*)info->indirect; |
| 483 | int *data = r600_buffer_map_sync_with_rings(&sctx->b, |
| 484 | indirect, PIPE_TRANSFER_READ); |
| 485 | data += info->indirect_offset/sizeof(int); |
| 486 | *start = data[2]; |
| 487 | *count = data[0]; |
| 488 | } else { |
| 489 | *start = info->start; |
| 490 | *count = info->count; |
| 491 | } |
| 492 | } |
| 493 | |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 494 | void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 495 | { |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 496 | struct si_context *sctx = (struct si_context *)ctx; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 497 | struct pipe_index_buffer ib = {}; |
Marek Olšák | 1fe7ba8 | 2015-01-31 20:09:46 +0100 | [diff] [blame] | 498 | unsigned i; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 499 | |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 500 | if (!info->count && !info->indirect && |
| 501 | (info->indexed || !info->count_from_stream_output)) |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 502 | return; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 503 | |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 504 | if (!sctx->ps_shader || !sctx->vs_shader) |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 505 | return; |
| 506 | |
Marek Olšák | 0b1f31a | 2015-02-22 19:14:42 +0100 | [diff] [blame] | 507 | si_decompress_textures(sctx); |
| 508 | |
| 509 | /* Set the rasterization primitive type. |
| 510 | * |
| 511 | * This must be done after si_decompress_textures, which can call |
| 512 | * draw_vbo recursively, and before si_update_shaders, which uses |
| 513 | * current_rast_prim for this draw_vbo call. */ |
Marek Olšák | 1fe7ba8 | 2015-01-31 20:09:46 +0100 | [diff] [blame] | 514 | if (sctx->gs_shader) |
| 515 | sctx->current_rast_prim = sctx->gs_shader->gs_output_prim; |
| 516 | else |
| 517 | sctx->current_rast_prim = info->mode; |
| 518 | |
Marek Olšák | 20e570d | 2014-12-07 17:53:56 +0100 | [diff] [blame] | 519 | si_update_shaders(sctx); |
Marek Olšák | d808de3 | 2014-07-11 23:17:07 +0200 | [diff] [blame] | 520 | |
| 521 | if (sctx->vertex_buffers_dirty) { |
| 522 | si_update_vertex_buffers(sctx); |
| 523 | sctx->vertex_buffers_dirty = false; |
| 524 | } |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 525 | |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 526 | if (info->indexed) { |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 527 | /* Initialize the index buffer struct. */ |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 528 | pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer); |
| 529 | ib.user_buffer = sctx->index_buffer.user_buffer; |
| 530 | ib.index_size = sctx->index_buffer.index_size; |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 531 | ib.offset = sctx->index_buffer.offset; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 532 | |
| 533 | /* Translate or upload, if needed. */ |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 534 | if (ib.index_size == 1) { |
| 535 | struct pipe_resource *out_buffer = NULL; |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 536 | unsigned out_offset, start, count, start_offset; |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 537 | void *ptr; |
| 538 | |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 539 | si_get_draw_start_count(sctx, info, &start, &count); |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 540 | start_offset = start * ib.index_size; |
| 541 | |
| 542 | u_upload_alloc(sctx->b.uploader, start_offset, count * 2, |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 543 | &out_offset, &out_buffer, &ptr); |
| 544 | |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 545 | util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0, |
| 546 | ib.offset + start_offset, |
| 547 | count, ptr); |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 548 | |
| 549 | pipe_resource_reference(&ib.buffer, NULL); |
| 550 | ib.user_buffer = NULL; |
| 551 | ib.buffer = out_buffer; |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 552 | /* info->start will be added by the drawing code */ |
| 553 | ib.offset = out_offset - start_offset; |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 554 | ib.index_size = 2; |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 555 | } else if (ib.user_buffer && !ib.buffer) { |
| 556 | unsigned start, count, start_offset; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 557 | |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 558 | si_get_draw_start_count(sctx, info, &start, &count); |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 559 | start_offset = start * ib.index_size; |
| 560 | |
| 561 | u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size, |
| 562 | (char*)ib.user_buffer + start_offset, |
| 563 | &ib.offset, &ib.buffer); |
| 564 | /* info->start will be added by the drawing code */ |
| 565 | ib.offset -= start_offset; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 566 | } |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 567 | } |
| 568 | |
Marek Olšák | 18a30c9 | 2014-12-29 14:53:11 +0100 | [diff] [blame] | 569 | if (info->indexed && r600_resource(ib.buffer)->TC_L2_dirty) { |
| 570 | sctx->b.flags |= SI_CONTEXT_INV_TC_L2; |
| 571 | r600_resource(ib.buffer)->TC_L2_dirty = false; |
| 572 | } |
| 573 | |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 574 | /* Check flush flags. */ |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 575 | if (sctx->b.flags) |
Adam Jackson | 74388dd | 2014-04-22 12:46:08 -0400 | [diff] [blame] | 576 | sctx->atoms.s.cache_flush->dirty = true; |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 577 | |
Tom Stellard | 2397a72 | 2014-12-10 09:13:59 -0500 | [diff] [blame] | 578 | if (sctx->emit_scratch_reloc) { |
| 579 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
| 580 | r600_write_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, |
| 581 | sctx->spi_tmpring_size); |
| 582 | |
| 583 | if (sctx->scratch_buffer) { |
| 584 | r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, |
| 585 | sctx->scratch_buffer, RADEON_USAGE_READWRITE, |
| 586 | RADEON_PRIO_SHADER_RESOURCE_RW); |
| 587 | |
| 588 | } |
| 589 | sctx->emit_scratch_reloc = false; |
| 590 | } |
| 591 | |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 592 | si_need_cs_space(sctx, 0, TRUE); |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 593 | |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 594 | /* Emit states. */ |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 595 | for (i = 0; i < SI_NUM_ATOMS(sctx); i++) { |
| 596 | if (sctx->atoms.array[i]->dirty) { |
| 597 | sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]); |
| 598 | sctx->atoms.array[i]->dirty = false; |
Marek Olšák | c8e70e6 | 2013-08-06 06:42:22 +0200 | [diff] [blame] | 599 | } |
| 600 | } |
| 601 | |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 602 | si_pm4_emit_dirty(sctx); |
Marek Olšák | fdf2c04 | 2015-02-22 17:42:20 +0100 | [diff] [blame] | 603 | si_emit_rasterizer_prim_state(sctx); |
| 604 | si_emit_draw_registers(sctx, info); |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 605 | si_emit_draw_packets(sctx, info, &ib); |
| 606 | |
Andreas Hartmetz | 0b57fc1 | 2014-01-11 15:56:47 +0100 | [diff] [blame] | 607 | #if SI_TRACE_CS |
Marek Olšák | a4c218f | 2014-01-22 02:02:18 +0100 | [diff] [blame] | 608 | if (sctx->screen->b.trace_bo) { |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 609 | si_trace_emit(sctx); |
Jerome Glisse | 3f7d971 | 2013-03-25 11:46:38 -0400 | [diff] [blame] | 610 | } |
| 611 | #endif |
| 612 | |
Marek Olšák | 0e7f563 | 2014-07-26 03:16:22 +0200 | [diff] [blame] | 613 | /* Workaround for a VGT hang when streamout is enabled. |
| 614 | * It must be done after drawing. */ |
| 615 | if (sctx->b.family == CHIP_HAWAII && |
| 616 | (sctx->b.streamout.streamout_enabled || |
| 617 | sctx->b.streamout.prims_gen_query_enabled)) { |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 618 | sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC; |
Marek Olšák | 0e7f563 | 2014-07-26 03:16:22 +0200 | [diff] [blame] | 619 | } |
| 620 | |
Marek Olšák | 6f6112a | 2013-01-17 19:36:41 +0100 | [diff] [blame] | 621 | /* Set the depth buffer as dirty. */ |
Marek Olšák | 6a5499b | 2014-03-04 17:49:39 +0100 | [diff] [blame] | 622 | if (sctx->framebuffer.state.zsbuf) { |
| 623 | struct pipe_surface *surf = sctx->framebuffer.state.zsbuf; |
Marek Olšák | 363b280 | 2013-08-05 03:42:11 +0200 | [diff] [blame] | 624 | struct r600_texture *rtex = (struct r600_texture *)surf->texture; |
Marek Olšák | 6f6112a | 2013-01-17 19:36:41 +0100 | [diff] [blame] | 625 | |
Marek Olšák | 0469171 | 2013-08-05 14:40:43 +0200 | [diff] [blame] | 626 | rtex->dirty_level_mask |= 1 << surf->u.tex.level; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 627 | } |
Marek Olšák | 6a5499b | 2014-03-04 17:49:39 +0100 | [diff] [blame] | 628 | if (sctx->framebuffer.compressed_cb_mask) { |
Marek Olšák | 3c3feb3 | 2013-08-06 08:48:07 +0200 | [diff] [blame] | 629 | struct pipe_surface *surf; |
| 630 | struct r600_texture *rtex; |
Marek Olšák | 6a5499b | 2014-03-04 17:49:39 +0100 | [diff] [blame] | 631 | unsigned mask = sctx->framebuffer.compressed_cb_mask; |
Marek Olšák | 3c3feb3 | 2013-08-06 08:48:07 +0200 | [diff] [blame] | 632 | |
| 633 | do { |
| 634 | unsigned i = u_bit_scan(&mask); |
Marek Olšák | 6a5499b | 2014-03-04 17:49:39 +0100 | [diff] [blame] | 635 | surf = sctx->framebuffer.state.cbufs[i]; |
Marek Olšák | 3c3feb3 | 2013-08-06 08:48:07 +0200 | [diff] [blame] | 636 | rtex = (struct r600_texture*)surf->texture; |
| 637 | |
| 638 | rtex->dirty_level_mask |= 1 << surf->u.tex.level; |
| 639 | } while (mask); |
| 640 | } |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 641 | |
| 642 | pipe_resource_reference(&ib.buffer, NULL); |
Marek Olšák | ba0c16f | 2014-01-22 01:29:18 +0100 | [diff] [blame] | 643 | sctx->b.num_draw_calls++; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 644 | } |
Marek Olšák | 837907b | 2014-09-05 11:59:10 +0200 | [diff] [blame] | 645 | |
| 646 | #if SI_TRACE_CS |
| 647 | void si_trace_emit(struct si_context *sctx) |
| 648 | { |
| 649 | struct si_screen *sscreen = sctx->screen; |
| 650 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
| 651 | uint64_t va; |
| 652 | |
| 653 | va = sscreen->b.trace_bo->gpu_address; |
| 654 | r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, sscreen->b.trace_bo, |
| 655 | RADEON_USAGE_READWRITE, RADEON_PRIO_MIN); |
| 656 | radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0)); |
| 657 | radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) | |
| 658 | PKT3_WRITE_DATA_WR_CONFIRM | |
| 659 | PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME)); |
| 660 | radeon_emit(cs, va & 0xFFFFFFFFUL); |
| 661 | radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL); |
| 662 | radeon_emit(cs, cs->cdw); |
| 663 | radeon_emit(cs, sscreen->b.cs_count); |
| 664 | } |
| 665 | #endif |