blob: f5265a10945eb56e59e6671e2e09de6064e65e6d [file] [log] [blame]
José Fonseca974b6412011-04-27 12:02:08 +01001/**********************************************************
2 * Copyright 2011 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27#include "pipe/p_format.h"
28#include "util/u_debug.h"
Brian Paule0542512015-08-13 11:00:58 -070029#include "util/u_format.h"
José Fonseca974b6412011-04-27 12:02:08 +010030#include "util/u_memory.h"
31
32#include "svga_winsys.h"
33#include "svga_screen.h"
34#include "svga_format.h"
35
36
Brian Paule0542512015-08-13 11:00:58 -070037/** Describes mapping from gallium formats to SVGA vertex/pixel formats */
38struct vgpu10_format_entry
39{
40 enum pipe_format pformat;
41 SVGA3dSurfaceFormat vertex_format;
42 SVGA3dSurfaceFormat pixel_format;
43 unsigned flags;
44};
45
Thomas Hellstromca59fd12017-04-07 14:54:56 +020046struct format_compat_entry
47{
48 enum pipe_format pformat;
49 const SVGA3dSurfaceFormat *compat_format;
50};
Brian Paule0542512015-08-13 11:00:58 -070051
Brian Paul4542a632017-10-14 10:50:21 -060052
53/**
54 * Table mapping Gallium formats to SVGA3d vertex/pixel formats.
55 * Note: the table is ordered according to PIPE_FORMAT_x order.
56 */
Brian Paule0542512015-08-13 11:00:58 -070057static const struct vgpu10_format_entry format_conversion_table[] =
58{
59 /* Gallium format SVGA3D vertex format SVGA3D pixel format Flags */
60 { PIPE_FORMAT_NONE, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Charmaine Lee63032312015-12-22 11:20:41 -080061 { PIPE_FORMAT_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, TF_GEN_MIPS },
62 { PIPE_FORMAT_B8G8R8X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -070063 { PIPE_FORMAT_A8R8G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
64 { PIPE_FORMAT_X8R8G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Charmaine Lee63032312015-12-22 11:20:41 -080065 { PIPE_FORMAT_B5G5R5A1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B5G5R5A1_UNORM, TF_GEN_MIPS },
Brian Paul1a483262015-11-16 10:41:20 -070066 { PIPE_FORMAT_B4G4R4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Charmaine Lee63032312015-12-22 11:20:41 -080067 { PIPE_FORMAT_B5G6R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B5G6R5_UNORM, TF_GEN_MIPS },
68 { PIPE_FORMAT_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, TF_GEN_MIPS },
Brian Paul1a483262015-11-16 10:41:20 -070069 { PIPE_FORMAT_L8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Charmaine Lee63032312015-12-22 11:20:41 -080070 { PIPE_FORMAT_A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_A8_UNORM, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -070071 { PIPE_FORMAT_I8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
72 { PIPE_FORMAT_L8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
73 { PIPE_FORMAT_L16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
74 { PIPE_FORMAT_UYVY, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
75 { PIPE_FORMAT_YUYV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Brian Paul1a483262015-11-16 10:41:20 -070076 { PIPE_FORMAT_Z16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_D16_UNORM, 0 },
Brian Paule0542512015-08-13 11:00:58 -070077 { PIPE_FORMAT_Z32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
78 { PIPE_FORMAT_Z32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT, 0 },
79 { PIPE_FORMAT_Z24_UNORM_S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, 0 },
80 { PIPE_FORMAT_S8_UINT_Z24_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
81 { PIPE_FORMAT_Z24X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, 0 },
82 { PIPE_FORMAT_X8Z24_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
83 { PIPE_FORMAT_S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
84 { PIPE_FORMAT_R64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
85 { PIPE_FORMAT_R64G64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
86 { PIPE_FORMAT_R64G64B64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
87 { PIPE_FORMAT_R64G64B64A64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Charmaine Lee63032312015-12-22 11:20:41 -080088 { PIPE_FORMAT_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS },
89 { PIPE_FORMAT_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS },
90 { PIPE_FORMAT_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, TF_GEN_MIPS },
91 { PIPE_FORMAT_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -070092 { PIPE_FORMAT_R32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
93 { PIPE_FORMAT_R32G32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
94 { PIPE_FORMAT_R32G32B32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
95 { PIPE_FORMAT_R32G32B32A32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
96 { PIPE_FORMAT_R32_USCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
97 { PIPE_FORMAT_R32G32_USCALED, SVGA3D_R32G32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
98 { PIPE_FORMAT_R32G32B32_USCALED, SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
99 { PIPE_FORMAT_R32G32B32A32_USCALED, SVGA3D_R32G32B32A32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
100 { PIPE_FORMAT_R32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
101 { PIPE_FORMAT_R32G32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
102 { PIPE_FORMAT_R32G32B32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
103 { PIPE_FORMAT_R32G32B32A32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
104 { PIPE_FORMAT_R32_SSCALED, SVGA3D_R32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
105 { PIPE_FORMAT_R32G32_SSCALED, SVGA3D_R32G32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
106 { PIPE_FORMAT_R32G32B32_SSCALED, SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
107 { PIPE_FORMAT_R32G32B32A32_SSCALED, SVGA3D_R32G32B32A32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
Charmaine Lee63032312015-12-22 11:20:41 -0800108 { PIPE_FORMAT_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, TF_GEN_MIPS },
109 { PIPE_FORMAT_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -0700110 { PIPE_FORMAT_R16G16B16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
Charmaine Lee63032312015-12-22 11:20:41 -0800111 { PIPE_FORMAT_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -0700112 { PIPE_FORMAT_R16_USCALED, SVGA3D_R16_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
113 { PIPE_FORMAT_R16G16_USCALED, SVGA3D_R16G16_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
114 { PIPE_FORMAT_R16G16B16_USCALED, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
115 { PIPE_FORMAT_R16G16B16A16_USCALED, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
116 { PIPE_FORMAT_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, 0 },
117 { PIPE_FORMAT_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, 0 },
118 { PIPE_FORMAT_R16G16B16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
119 { PIPE_FORMAT_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, 0 },
120 { PIPE_FORMAT_R16_SSCALED, SVGA3D_R16_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
121 { PIPE_FORMAT_R16G16_SSCALED, SVGA3D_R16G16_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
122 { PIPE_FORMAT_R16G16B16_SSCALED, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
123 { PIPE_FORMAT_R16G16B16A16_SSCALED, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
Charmaine Lee63032312015-12-22 11:20:41 -0800124 { PIPE_FORMAT_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS },
125 { PIPE_FORMAT_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -0700126 { PIPE_FORMAT_R8G8B8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
Charmaine Lee63032312015-12-22 11:20:41 -0800127 { PIPE_FORMAT_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -0700128 { PIPE_FORMAT_X8B8G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
129 { PIPE_FORMAT_R8_USCALED, SVGA3D_R8_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
130 { PIPE_FORMAT_R8G8_USCALED, SVGA3D_R8G8_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
131 { PIPE_FORMAT_R8G8B8_USCALED, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
132 { PIPE_FORMAT_R8G8B8A8_USCALED, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
133 { 73, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
134 { PIPE_FORMAT_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, 0 },
135 { PIPE_FORMAT_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, 0 },
136 { PIPE_FORMAT_R8G8B8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
137 { PIPE_FORMAT_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, 0 },
138 { 78, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
139 { 79, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
140 { 80, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
141 { 81, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
142 { PIPE_FORMAT_R8_SSCALED, SVGA3D_R8_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
143 { PIPE_FORMAT_R8G8_SSCALED, SVGA3D_R8G8_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
144 { PIPE_FORMAT_R8G8B8_SSCALED, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
145 { PIPE_FORMAT_R8G8B8A8_SSCALED, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
146 { 86, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
147 { PIPE_FORMAT_R32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
148 { PIPE_FORMAT_R32G32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
149 { PIPE_FORMAT_R32G32B32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
150 { PIPE_FORMAT_R32G32B32A32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Charmaine Lee63032312015-12-22 11:20:41 -0800151 { PIPE_FORMAT_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, TF_GEN_MIPS },
152 { PIPE_FORMAT_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -0700153 { PIPE_FORMAT_R16G16B16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
Charmaine Lee63032312015-12-22 11:20:41 -0800154 { PIPE_FORMAT_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -0700155 { PIPE_FORMAT_L8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
156 { PIPE_FORMAT_L8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
157 { PIPE_FORMAT_R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
158 { PIPE_FORMAT_A8B8G8R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
159 { PIPE_FORMAT_X8B8G8R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Charmaine Lee63032312015-12-22 11:20:41 -0800160 { PIPE_FORMAT_B8G8R8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8A8_UNORM_SRGB, TF_GEN_MIPS },
161 { PIPE_FORMAT_B8G8R8X8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM_SRGB, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -0700162 { PIPE_FORMAT_A8R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
163 { PIPE_FORMAT_X8R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Charmaine Lee63032312015-12-22 11:20:41 -0800164 { PIPE_FORMAT_R8G8B8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8B8A8_UNORM_SRGB, TF_GEN_MIPS },
Brian Paul1a483262015-11-16 10:41:20 -0700165 { PIPE_FORMAT_DXT1_RGB, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, 0 },
166 { PIPE_FORMAT_DXT1_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, 0 },
167 { PIPE_FORMAT_DXT3_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM, 0 },
168 { PIPE_FORMAT_DXT5_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM, 0 },
169 { PIPE_FORMAT_DXT1_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, 0 },
170 { PIPE_FORMAT_DXT1_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, 0 },
171 { PIPE_FORMAT_DXT3_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM_SRGB, 0 },
172 { PIPE_FORMAT_DXT5_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM_SRGB, 0 },
Brian Paule0542512015-08-13 11:00:58 -0700173 { PIPE_FORMAT_RGTC1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC4_UNORM, 0 },
174 { PIPE_FORMAT_RGTC1_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC4_SNORM, 0 },
175 { PIPE_FORMAT_RGTC2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC5_UNORM, 0 },
176 { PIPE_FORMAT_RGTC2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC5_SNORM, 0 },
177 { PIPE_FORMAT_R8G8_B8G8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
178 { PIPE_FORMAT_G8R8_G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
179 { PIPE_FORMAT_R8SG8SB8UX8U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
180 { PIPE_FORMAT_R5SG5SB6U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
181 { PIPE_FORMAT_A8B8G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
182 { PIPE_FORMAT_B5G5R5X1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
183 { PIPE_FORMAT_R10G10B10A2_USCALED, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_USCALED },
Charmaine Lee63032312015-12-22 11:20:41 -0800184 { PIPE_FORMAT_R11G11B10_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_R11G11B10_FLOAT, TF_GEN_MIPS },
Brian Paule0542512015-08-13 11:00:58 -0700185 { PIPE_FORMAT_R9G9B9E5_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_R9G9B9E5_SHAREDEXP, 0 },
186 { PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT_S8X24_UINT, 0 },
187 { PIPE_FORMAT_R1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
188 { PIPE_FORMAT_R10G10B10X2_USCALED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
189 { PIPE_FORMAT_R10G10B10X2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
190 { PIPE_FORMAT_L4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
191 { PIPE_FORMAT_B10G10R10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_BGRA },
192 { PIPE_FORMAT_R10SG10SB10SA2U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
193 { PIPE_FORMAT_R8G8Bx_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
194 { PIPE_FORMAT_R8G8B8X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
195 { PIPE_FORMAT_B4G4R4X4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
196 { PIPE_FORMAT_X24S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
197 { PIPE_FORMAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
198 { PIPE_FORMAT_X32_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
199 { PIPE_FORMAT_B2G3R3_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
200 { PIPE_FORMAT_L16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
201 { PIPE_FORMAT_A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
202 { PIPE_FORMAT_I16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
203 { PIPE_FORMAT_LATC1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
204 { PIPE_FORMAT_LATC1_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
205 { PIPE_FORMAT_LATC2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
206 { PIPE_FORMAT_LATC2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
207 { PIPE_FORMAT_A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
208 { PIPE_FORMAT_L8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
209 { PIPE_FORMAT_L8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
210 { PIPE_FORMAT_I8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
211 { PIPE_FORMAT_A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
212 { PIPE_FORMAT_L16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
213 { PIPE_FORMAT_L16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
214 { PIPE_FORMAT_I16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
215 { PIPE_FORMAT_A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
216 { PIPE_FORMAT_L16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
217 { PIPE_FORMAT_L16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
218 { PIPE_FORMAT_I16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
219 { PIPE_FORMAT_A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
220 { PIPE_FORMAT_L32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
221 { PIPE_FORMAT_L32A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
222 { PIPE_FORMAT_I32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
223 { PIPE_FORMAT_YV12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
224 { PIPE_FORMAT_YV16, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
225 { PIPE_FORMAT_IYUV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
226 { PIPE_FORMAT_NV12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
227 { PIPE_FORMAT_NV21, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
228 { PIPE_FORMAT_A4R4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
229 { PIPE_FORMAT_R4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
230 { PIPE_FORMAT_R8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
231 { PIPE_FORMAT_A8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
232 { PIPE_FORMAT_R10G10B10A2_SSCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SSCALED },
233 { PIPE_FORMAT_R10G10B10A2_SNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SNORM },
234 { PIPE_FORMAT_B10G10R10A2_USCALED, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_USCALED },
235 { PIPE_FORMAT_B10G10R10A2_SSCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SSCALED },
236 { PIPE_FORMAT_B10G10R10A2_SNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SNORM },
237 { PIPE_FORMAT_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, 0 },
238 { PIPE_FORMAT_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, 0 },
239 { PIPE_FORMAT_R8G8B8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
240 { PIPE_FORMAT_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, 0 },
241 { PIPE_FORMAT_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, 0 },
242 { PIPE_FORMAT_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, 0 },
243 { PIPE_FORMAT_R8G8B8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
244 { PIPE_FORMAT_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, 0 },
245 { PIPE_FORMAT_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, 0 },
246 { PIPE_FORMAT_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, 0 },
247 { PIPE_FORMAT_R16G16B16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
248 { PIPE_FORMAT_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, 0 },
249 { PIPE_FORMAT_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, 0 },
250 { PIPE_FORMAT_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, 0 },
251 { PIPE_FORMAT_R16G16B16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
252 { PIPE_FORMAT_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, 0 },
253 { PIPE_FORMAT_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, 0 },
254 { PIPE_FORMAT_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, 0 },
Neha Bhende429ace22016-06-02 14:35:20 -0700255 { PIPE_FORMAT_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, 0 },
Brian Paule0542512015-08-13 11:00:58 -0700256 { PIPE_FORMAT_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, 0 },
257 { PIPE_FORMAT_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, 0 },
258 { PIPE_FORMAT_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, 0 },
Neha Bhende429ace22016-06-02 14:35:20 -0700259 { PIPE_FORMAT_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, 0 },
Brian Paule0542512015-08-13 11:00:58 -0700260 { PIPE_FORMAT_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, 0 },
261 { PIPE_FORMAT_A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
262 { PIPE_FORMAT_I8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
263 { PIPE_FORMAT_L8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
264 { PIPE_FORMAT_L8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
265 { PIPE_FORMAT_A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
266 { PIPE_FORMAT_I8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
267 { PIPE_FORMAT_L8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
268 { PIPE_FORMAT_L8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
269 { PIPE_FORMAT_A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
270 { PIPE_FORMAT_I16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
271 { PIPE_FORMAT_L16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
272 { PIPE_FORMAT_L16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
273 { PIPE_FORMAT_A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
274 { PIPE_FORMAT_I16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
275 { PIPE_FORMAT_L16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
276 { PIPE_FORMAT_L16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
277 { PIPE_FORMAT_A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
278 { PIPE_FORMAT_I32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
279 { PIPE_FORMAT_L32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
280 { PIPE_FORMAT_L32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
281 { PIPE_FORMAT_A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
282 { PIPE_FORMAT_I32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
283 { PIPE_FORMAT_L32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
284 { PIPE_FORMAT_L32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
285 { PIPE_FORMAT_B10G10R10A2_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
286 { PIPE_FORMAT_ETC1_RGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
287 { PIPE_FORMAT_R8G8_R8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
288 { PIPE_FORMAT_G8R8_B8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
289 { PIPE_FORMAT_R8G8B8X8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
290 { PIPE_FORMAT_R8G8B8X8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
291 { PIPE_FORMAT_R8G8B8X8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
292 { PIPE_FORMAT_R8G8B8X8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
293 { PIPE_FORMAT_B10G10R10X2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
294 { PIPE_FORMAT_R16G16B16X16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
295 { PIPE_FORMAT_R16G16B16X16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
296 { PIPE_FORMAT_R16G16B16X16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
297 { PIPE_FORMAT_R16G16B16X16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
298 { PIPE_FORMAT_R16G16B16X16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
299 { PIPE_FORMAT_R32G32B32X32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
300 { PIPE_FORMAT_R32G32B32X32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
301 { PIPE_FORMAT_R32G32B32X32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
302 { PIPE_FORMAT_R8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
303 { PIPE_FORMAT_R16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
304 { PIPE_FORMAT_R16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
305 { PIPE_FORMAT_R16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
306 { PIPE_FORMAT_R32A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
307 { PIPE_FORMAT_R8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
308 { PIPE_FORMAT_R8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
309 { PIPE_FORMAT_R16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
310 { PIPE_FORMAT_R16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
311 { PIPE_FORMAT_R32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
312 { PIPE_FORMAT_R32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
313 { PIPE_FORMAT_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, 0 },
314 { PIPE_FORMAT_B5G6R5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
315 { PIPE_FORMAT_BPTC_RGBA_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
316 { PIPE_FORMAT_BPTC_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
317 { PIPE_FORMAT_BPTC_RGB_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
318 { PIPE_FORMAT_BPTC_RGB_UFLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
319 { PIPE_FORMAT_A8L8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
320 { PIPE_FORMAT_A8L8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
321 { PIPE_FORMAT_A8L8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
322 { PIPE_FORMAT_A16L16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
323 { PIPE_FORMAT_G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
324 { PIPE_FORMAT_G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
325 { PIPE_FORMAT_G16R16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
326 { PIPE_FORMAT_G16R16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
327 { PIPE_FORMAT_A8B8G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
328 { PIPE_FORMAT_X8B8G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
329 { PIPE_FORMAT_ETC2_RGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
330 { PIPE_FORMAT_ETC2_SRGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
331 { PIPE_FORMAT_ETC2_RGB8A1, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
332 { PIPE_FORMAT_ETC2_SRGB8A1, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
333 { PIPE_FORMAT_ETC2_RGBA8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
334 { PIPE_FORMAT_ETC2_SRGBA8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
335 { PIPE_FORMAT_ETC2_R11_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
336 { PIPE_FORMAT_ETC2_R11_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
337 { PIPE_FORMAT_ETC2_RG11_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
338 { PIPE_FORMAT_ETC2_RG11_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Jose Fonsecac9651f02015-11-23 16:45:28 +0000339 { PIPE_FORMAT_ASTC_4x4, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
340 { PIPE_FORMAT_ASTC_5x4, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
341 { PIPE_FORMAT_ASTC_5x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
342 { PIPE_FORMAT_ASTC_6x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
343 { PIPE_FORMAT_ASTC_6x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
344 { PIPE_FORMAT_ASTC_8x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
345 { PIPE_FORMAT_ASTC_8x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
346 { PIPE_FORMAT_ASTC_8x8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
347 { PIPE_FORMAT_ASTC_10x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
348 { PIPE_FORMAT_ASTC_10x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
349 { PIPE_FORMAT_ASTC_10x8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
350 { PIPE_FORMAT_ASTC_10x10, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
351 { PIPE_FORMAT_ASTC_12x10, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
352 { PIPE_FORMAT_ASTC_12x12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
353 { PIPE_FORMAT_ASTC_4x4_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
354 { PIPE_FORMAT_ASTC_5x4_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
355 { PIPE_FORMAT_ASTC_5x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
356 { PIPE_FORMAT_ASTC_6x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
357 { PIPE_FORMAT_ASTC_6x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
358 { PIPE_FORMAT_ASTC_8x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
359 { PIPE_FORMAT_ASTC_8x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
360 { PIPE_FORMAT_ASTC_8x8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
361 { PIPE_FORMAT_ASTC_10x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
362 { PIPE_FORMAT_ASTC_10x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
363 { PIPE_FORMAT_ASTC_10x8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
364 { PIPE_FORMAT_ASTC_10x10_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
365 { PIPE_FORMAT_ASTC_12x10_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
366 { PIPE_FORMAT_ASTC_12x12_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Christian König8dee3252017-03-13 12:43:18 +0100367 { PIPE_FORMAT_P016, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Nicolai Hähnle85a3e1c2017-09-27 15:25:35 +0200368 { PIPE_FORMAT_R10G10B10X2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Brian Paul4542a632017-10-14 10:50:21 -0600369 { PIPE_FORMAT_A1B5G5R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
370 { PIPE_FORMAT_X1B5G5R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
Brian Paule0542512015-08-13 11:00:58 -0700371};
372
373
374/**
375 * Translate a gallium vertex format to a vgpu10 vertex format.
376 * Also, return any special vertex format flags.
377 */
378void
379svga_translate_vertex_format_vgpu10(enum pipe_format format,
380 SVGA3dSurfaceFormat *svga_format,
381 unsigned *vf_flags)
382{
Brian Paule0184b32016-04-25 09:34:40 -0600383 assert(format < ARRAY_SIZE(format_conversion_table));
384 if (format >= ARRAY_SIZE(format_conversion_table)) {
Brian Paule0542512015-08-13 11:00:58 -0700385 format = PIPE_FORMAT_NONE;
386 }
387 *svga_format = format_conversion_table[format].vertex_format;
388 *vf_flags = format_conversion_table[format].flags;
389}
390
391
Charmaine Lee5bd5ec62017-04-18 15:55:59 -0700392/**
393 * Translate a gallium scanout format to a svga format valid
394 * for screen target surface.
395 */
396static SVGA3dSurfaceFormat
397svga_translate_screen_target_format_vgpu10(enum pipe_format format)
398{
399 switch (format) {
400 case PIPE_FORMAT_B8G8R8A8_UNORM:
401 return SVGA3D_B8G8R8A8_UNORM;
402 case PIPE_FORMAT_B8G8R8X8_UNORM:
403 return SVGA3D_B8G8R8X8_UNORM;
404 case PIPE_FORMAT_B5G6R5_UNORM:
405 return SVGA3D_R5G6B5;
406 case PIPE_FORMAT_B5G5R5A1_UNORM:
407 return SVGA3D_A1R5G5B5;
408 default:
409 debug_printf("Invalid format %s specified for screen target\n",
410 svga_format_name(format));
411 return SVGA3D_FORMAT_INVALID;
412 }
413}
414
José Fonseca974b6412011-04-27 12:02:08 +0100415/*
416 * Translate from gallium format to SVGA3D format.
417 */
418SVGA3dSurfaceFormat
Brian Paul2ad4ba02016-09-20 17:01:20 -0600419svga_translate_format(const struct svga_screen *ss,
José Fonseca974b6412011-04-27 12:02:08 +0100420 enum pipe_format format,
421 unsigned bind)
422{
Brian Paule0542512015-08-13 11:00:58 -0700423 if (ss->sws->have_vgpu10) {
424 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
425 return format_conversion_table[format].vertex_format;
426 }
Charmaine Lee5bd5ec62017-04-18 15:55:59 -0700427 else if (bind & PIPE_BIND_SCANOUT) {
428 return svga_translate_screen_target_format_vgpu10(format);
429 }
Brian Paule0542512015-08-13 11:00:58 -0700430 else {
431 return format_conversion_table[format].pixel_format;
432 }
433 }
José Fonseca974b6412011-04-27 12:02:08 +0100434
Brian Paule0542512015-08-13 11:00:58 -0700435 switch(format) {
José Fonseca974b6412011-04-27 12:02:08 +0100436 case PIPE_FORMAT_B8G8R8A8_UNORM:
437 return SVGA3D_A8R8G8B8;
438 case PIPE_FORMAT_B8G8R8X8_UNORM:
439 return SVGA3D_X8R8G8B8;
440
Brian Paul681f9212011-07-27 16:12:25 -0600441 /* sRGB required for GL2.1 */
José Fonseca974b6412011-04-27 12:02:08 +0100442 case PIPE_FORMAT_B8G8R8A8_SRGB:
443 return SVGA3D_A8R8G8B8;
Brian Paul681f9212011-07-27 16:12:25 -0600444 case PIPE_FORMAT_DXT1_SRGB:
445 case PIPE_FORMAT_DXT1_SRGBA:
446 return SVGA3D_DXT1;
447 case PIPE_FORMAT_DXT3_SRGBA:
448 return SVGA3D_DXT3;
449 case PIPE_FORMAT_DXT5_SRGBA:
450 return SVGA3D_DXT5;
José Fonseca974b6412011-04-27 12:02:08 +0100451
452 case PIPE_FORMAT_B5G6R5_UNORM:
453 return SVGA3D_R5G6B5;
454 case PIPE_FORMAT_B5G5R5A1_UNORM:
455 return SVGA3D_A1R5G5B5;
456 case PIPE_FORMAT_B4G4R4A4_UNORM:
457 return SVGA3D_A4R4G4B4;
458
John KÃ¥re Alsaker1a4aad12012-10-09 00:50:53 +0200459 case PIPE_FORMAT_R16G16B16A16_UNORM:
460 return SVGA3D_A16B16G16R16;
461
José Fonseca974b6412011-04-27 12:02:08 +0100462 case PIPE_FORMAT_Z16_UNORM:
Brian Paule0542512015-08-13 11:00:58 -0700463 assert(!ss->sws->have_vgpu10);
José Fonseca974b6412011-04-27 12:02:08 +0100464 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.z16 : SVGA3D_Z_D16;
Dave Airlie866f9b12011-09-11 09:45:10 +0100465 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
Brian Paule0542512015-08-13 11:00:58 -0700466 assert(!ss->sws->have_vgpu10);
José Fonseca974b6412011-04-27 12:02:08 +0100467 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.s8z24 : SVGA3D_Z_D24S8;
468 case PIPE_FORMAT_X8Z24_UNORM:
Brian Paule0542512015-08-13 11:00:58 -0700469 assert(!ss->sws->have_vgpu10);
José Fonseca974b6412011-04-27 12:02:08 +0100470 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.x8z24 : SVGA3D_Z_D24X8;
471
472 case PIPE_FORMAT_A8_UNORM:
473 return SVGA3D_ALPHA8;
474 case PIPE_FORMAT_L8_UNORM:
475 return SVGA3D_LUMINANCE8;
476
477 case PIPE_FORMAT_DXT1_RGB:
478 case PIPE_FORMAT_DXT1_RGBA:
479 return SVGA3D_DXT1;
480 case PIPE_FORMAT_DXT3_RGBA:
481 return SVGA3D_DXT3;
482 case PIPE_FORMAT_DXT5_RGBA:
483 return SVGA3D_DXT5;
484
Brian Paul9a41eca2011-07-11 10:30:56 -0600485 /* Float formats (only 1, 2 and 4-component formats supported) */
486 case PIPE_FORMAT_R32_FLOAT:
487 return SVGA3D_R_S23E8;
488 case PIPE_FORMAT_R32G32_FLOAT:
489 return SVGA3D_RG_S23E8;
490 case PIPE_FORMAT_R32G32B32A32_FLOAT:
491 return SVGA3D_ARGB_S23E8;
492 case PIPE_FORMAT_R16_FLOAT:
493 return SVGA3D_R_S10E5;
494 case PIPE_FORMAT_R16G16_FLOAT:
495 return SVGA3D_RG_S10E5;
496 case PIPE_FORMAT_R16G16B16A16_FLOAT:
497 return SVGA3D_ARGB_S10E5;
498
José Fonseca974b6412011-04-27 12:02:08 +0100499 case PIPE_FORMAT_Z32_UNORM:
500 /* SVGA3D_Z_D32 is not yet unsupported */
501 /* fall-through */
502 default:
503 return SVGA3D_FORMAT_INVALID;
504 }
505}
506
507
508/*
509 * Format capability description entry.
510 */
511struct format_cap {
Brian Paule0542512015-08-13 11:00:58 -0700512 const char *name;
513
José Fonseca974b6412011-04-27 12:02:08 +0100514 SVGA3dSurfaceFormat format;
515
516 /*
517 * Capability index corresponding to the format.
518 */
Brian Paule0542512015-08-13 11:00:58 -0700519 SVGA3dDevCapIndex devcap;
520
521 /* size of each pixel/block */
522 unsigned block_width, block_height, block_bytes;
José Fonseca974b6412011-04-27 12:02:08 +0100523
524 /*
525 * Mask of supported SVGA3dFormatOp operations, to be inferred when the
526 * capability is not explicitly present.
527 */
528 uint32 defaultOperations;
529};
530
531
532/*
533 * Format capability description table.
534 *
Brian Paule0542512015-08-13 11:00:58 -0700535 * Ordered by increasing SVGA3dSurfaceFormat value, but with gaps.
536 *
537 * Note: there are some special cases below where we set devcap=0 and
538 * avoid querying the host. In particular, depth/stencil formats which
539 * can be rendered to and sampled from. For example, the gallium format
540 * PIPE_FORMAT_Z24_UNORM_S8_UINT is converted to SVGA3D_D24_UNORM_S8_UINT
Brian Paul07823502017-06-28 16:43:52 -0600541 * for rendering but converted to SVGA3D_R24_UNORM_X8 for sampling.
Brian Paule0542512015-08-13 11:00:58 -0700542 * If we want to query if a format supports both rendering and sampling the
Brian Paul1a483262015-11-16 10:41:20 -0700543 * host will tell us no for SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D16_UNORM and
Brian Paul07823502017-06-28 16:43:52 -0600544 * SVGA3D_R24_UNORM_X8. So we override the host query for those
Brian Paule0542512015-08-13 11:00:58 -0700545 * formats and report that both can do rendering and sampling.
José Fonseca974b6412011-04-27 12:02:08 +0100546 */
547static const struct format_cap format_cap_table[] = {
548 {
Brian Paule0542512015-08-13 11:00:58 -0700549 "SVGA3D_FORMAT_INVALID",
550 SVGA3D_FORMAT_INVALID, 0, 0, 0, 0, 0
551 },
552 {
553 "SVGA3D_X8R8G8B8",
José Fonseca974b6412011-04-27 12:02:08 +0100554 SVGA3D_X8R8G8B8,
555 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8,
Brian Paule0542512015-08-13 11:00:58 -0700556 1, 1, 4,
José Fonseca974b6412011-04-27 12:02:08 +0100557 SVGA3DFORMAT_OP_TEXTURE |
558 SVGA3DFORMAT_OP_CUBETEXTURE |
559 SVGA3DFORMAT_OP_VOLUMETEXTURE |
560 SVGA3DFORMAT_OP_DISPLAYMODE |
José Fonseca974b6412011-04-27 12:02:08 +0100561 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
562 },
563 {
Brian Paule0542512015-08-13 11:00:58 -0700564 "SVGA3D_A8R8G8B8",
José Fonseca974b6412011-04-27 12:02:08 +0100565 SVGA3D_A8R8G8B8,
566 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8,
Brian Paule0542512015-08-13 11:00:58 -0700567 1, 1, 4,
José Fonseca974b6412011-04-27 12:02:08 +0100568 SVGA3DFORMAT_OP_TEXTURE |
569 SVGA3DFORMAT_OP_CUBETEXTURE |
570 SVGA3DFORMAT_OP_VOLUMETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100571 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
572 },
573 {
Brian Paule0542512015-08-13 11:00:58 -0700574 "SVGA3D_R5G6B5",
José Fonseca974b6412011-04-27 12:02:08 +0100575 SVGA3D_R5G6B5,
576 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5,
Brian Paule0542512015-08-13 11:00:58 -0700577 1, 1, 2,
José Fonseca974b6412011-04-27 12:02:08 +0100578 SVGA3DFORMAT_OP_TEXTURE |
579 SVGA3DFORMAT_OP_CUBETEXTURE |
580 SVGA3DFORMAT_OP_VOLUMETEXTURE |
581 SVGA3DFORMAT_OP_DISPLAYMODE |
José Fonseca974b6412011-04-27 12:02:08 +0100582 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
583 },
584 {
Brian Paule0542512015-08-13 11:00:58 -0700585 "SVGA3D_X1R5G5B5",
José Fonseca974b6412011-04-27 12:02:08 +0100586 SVGA3D_X1R5G5B5,
587 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5,
Brian Paule0542512015-08-13 11:00:58 -0700588 1, 1, 2,
José Fonseca974b6412011-04-27 12:02:08 +0100589 SVGA3DFORMAT_OP_TEXTURE |
590 SVGA3DFORMAT_OP_CUBETEXTURE |
591 SVGA3DFORMAT_OP_VOLUMETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100592 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
593 },
594 {
Brian Paule0542512015-08-13 11:00:58 -0700595 "SVGA3D_A1R5G5B5",
José Fonseca974b6412011-04-27 12:02:08 +0100596 SVGA3D_A1R5G5B5,
597 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5,
Brian Paule0542512015-08-13 11:00:58 -0700598 1, 1, 2,
José Fonseca974b6412011-04-27 12:02:08 +0100599 SVGA3DFORMAT_OP_TEXTURE |
600 SVGA3DFORMAT_OP_CUBETEXTURE |
601 SVGA3DFORMAT_OP_VOLUMETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100602 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
603 },
604 {
Brian Paule0542512015-08-13 11:00:58 -0700605 "SVGA3D_A4R4G4B4",
José Fonseca974b6412011-04-27 12:02:08 +0100606 SVGA3D_A4R4G4B4,
607 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4,
Brian Paule0542512015-08-13 11:00:58 -0700608 1, 1, 2,
José Fonseca974b6412011-04-27 12:02:08 +0100609 SVGA3DFORMAT_OP_TEXTURE |
610 SVGA3DFORMAT_OP_CUBETEXTURE |
611 SVGA3DFORMAT_OP_VOLUMETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100612 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
613 },
José Fonseca974b6412011-04-27 12:02:08 +0100614 {
Brian Paule0542512015-08-13 11:00:58 -0700615 /*
616 * SVGA3D_Z_D32 is not yet supported, and has no corresponding
617 * SVGA3D_DEVCAP_xxx.
618 */
619 "SVGA3D_Z_D32",
620 SVGA3D_Z_D32, 0, 0, 0, 0, 0
621 },
622 {
623 "SVGA3D_Z_D16",
José Fonseca974b6412011-04-27 12:02:08 +0100624 SVGA3D_Z_D16,
625 SVGA3D_DEVCAP_SURFACEFMT_Z_D16,
Brian Paule0542512015-08-13 11:00:58 -0700626 1, 1, 2,
627 SVGA3DFORMAT_OP_ZSTENCIL
José Fonseca974b6412011-04-27 12:02:08 +0100628 },
629 {
Brian Paule0542512015-08-13 11:00:58 -0700630 "SVGA3D_Z_D24S8",
José Fonseca974b6412011-04-27 12:02:08 +0100631 SVGA3D_Z_D24S8,
632 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8,
Brian Paule0542512015-08-13 11:00:58 -0700633 1, 1, 4,
634 SVGA3DFORMAT_OP_ZSTENCIL
José Fonseca974b6412011-04-27 12:02:08 +0100635 },
636 {
Brian Paule0542512015-08-13 11:00:58 -0700637 "SVGA3D_Z_D15S1",
José Fonseca974b6412011-04-27 12:02:08 +0100638 SVGA3D_Z_D15S1,
639 SVGA3D_DEVCAP_MAX,
Brian Paule0542512015-08-13 11:00:58 -0700640 1, 1, 2,
641 SVGA3DFORMAT_OP_ZSTENCIL
José Fonseca974b6412011-04-27 12:02:08 +0100642 },
643 {
Brian Paule0542512015-08-13 11:00:58 -0700644 "SVGA3D_LUMINANCE8",
José Fonseca974b6412011-04-27 12:02:08 +0100645 SVGA3D_LUMINANCE8,
646 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8,
Brian Paule0542512015-08-13 11:00:58 -0700647 1, 1, 1,
José Fonseca974b6412011-04-27 12:02:08 +0100648 SVGA3DFORMAT_OP_TEXTURE |
649 SVGA3DFORMAT_OP_CUBETEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700650 SVGA3DFORMAT_OP_VOLUMETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100651 },
652 {
Brian Paule0542512015-08-13 11:00:58 -0700653 /*
654 * SVGA3D_LUMINANCE4_ALPHA4 is not supported, and has no corresponding
655 * SVGA3D_DEVCAP_xxx.
656 */
657 "SVGA3D_LUMINANCE4_ALPHA4",
658 SVGA3D_LUMINANCE4_ALPHA4, 0, 0, 0, 0, 0
José Fonseca974b6412011-04-27 12:02:08 +0100659 },
José Fonseca974b6412011-04-27 12:02:08 +0100660 {
Brian Paule0542512015-08-13 11:00:58 -0700661 "SVGA3D_LUMINANCE16",
José Fonseca974b6412011-04-27 12:02:08 +0100662 SVGA3D_LUMINANCE16,
663 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16,
Brian Paule0542512015-08-13 11:00:58 -0700664 1, 1, 2,
José Fonseca974b6412011-04-27 12:02:08 +0100665 SVGA3DFORMAT_OP_TEXTURE |
666 SVGA3DFORMAT_OP_CUBETEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700667 SVGA3DFORMAT_OP_VOLUMETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100668 },
669 {
Brian Paule0542512015-08-13 11:00:58 -0700670 "SVGA3D_LUMINANCE8_ALPHA8",
671 SVGA3D_LUMINANCE8_ALPHA8,
672 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8,
673 1, 1, 2,
674 SVGA3DFORMAT_OP_TEXTURE |
675 SVGA3DFORMAT_OP_CUBETEXTURE |
676 SVGA3DFORMAT_OP_VOLUMETEXTURE
677 },
678 {
679 "SVGA3D_DXT1",
José Fonseca974b6412011-04-27 12:02:08 +0100680 SVGA3D_DXT1,
681 SVGA3D_DEVCAP_SURFACEFMT_DXT1,
Brian Paule0542512015-08-13 11:00:58 -0700682 4, 4, 8,
José Fonseca974b6412011-04-27 12:02:08 +0100683 SVGA3DFORMAT_OP_TEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700684 SVGA3DFORMAT_OP_CUBETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100685 },
686 {
Brian Paule0542512015-08-13 11:00:58 -0700687 "SVGA3D_DXT2",
José Fonseca974b6412011-04-27 12:02:08 +0100688 SVGA3D_DXT2,
689 SVGA3D_DEVCAP_SURFACEFMT_DXT2,
Brian Paule0542512015-08-13 11:00:58 -0700690 4, 4, 8,
José Fonseca974b6412011-04-27 12:02:08 +0100691 SVGA3DFORMAT_OP_TEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700692 SVGA3DFORMAT_OP_CUBETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100693 },
694 {
Brian Paule0542512015-08-13 11:00:58 -0700695 "SVGA3D_DXT3",
José Fonseca974b6412011-04-27 12:02:08 +0100696 SVGA3D_DXT3,
697 SVGA3D_DEVCAP_SURFACEFMT_DXT3,
Brian Paule0542512015-08-13 11:00:58 -0700698 4, 4, 16,
José Fonseca974b6412011-04-27 12:02:08 +0100699 SVGA3DFORMAT_OP_TEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700700 SVGA3DFORMAT_OP_CUBETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100701 },
702 {
Brian Paule0542512015-08-13 11:00:58 -0700703 "SVGA3D_DXT4",
José Fonseca974b6412011-04-27 12:02:08 +0100704 SVGA3D_DXT4,
705 SVGA3D_DEVCAP_SURFACEFMT_DXT4,
Brian Paule0542512015-08-13 11:00:58 -0700706 4, 4, 16,
José Fonseca974b6412011-04-27 12:02:08 +0100707 SVGA3DFORMAT_OP_TEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700708 SVGA3DFORMAT_OP_CUBETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100709 },
710 {
Brian Paule0542512015-08-13 11:00:58 -0700711 "SVGA3D_DXT5",
José Fonseca974b6412011-04-27 12:02:08 +0100712 SVGA3D_DXT5,
713 SVGA3D_DEVCAP_SURFACEFMT_DXT5,
Brian Paule0542512015-08-13 11:00:58 -0700714 4, 4, 8,
José Fonseca974b6412011-04-27 12:02:08 +0100715 SVGA3DFORMAT_OP_TEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700716 SVGA3DFORMAT_OP_CUBETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100717 },
718 {
Brian Paule0542512015-08-13 11:00:58 -0700719 "SVGA3D_BUMPU8V8",
José Fonseca974b6412011-04-27 12:02:08 +0100720 SVGA3D_BUMPU8V8,
721 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8,
Brian Paule0542512015-08-13 11:00:58 -0700722 1, 1, 2,
José Fonseca974b6412011-04-27 12:02:08 +0100723 SVGA3DFORMAT_OP_TEXTURE |
724 SVGA3DFORMAT_OP_CUBETEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700725 SVGA3DFORMAT_OP_VOLUMETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100726 },
José Fonseca974b6412011-04-27 12:02:08 +0100727 {
Brian Paule0542512015-08-13 11:00:58 -0700728 /*
729 * SVGA3D_BUMPL6V5U5 is unsupported; it has no corresponding
730 * SVGA3D_DEVCAP_xxx.
731 */
732 "SVGA3D_BUMPL6V5U5",
733 SVGA3D_BUMPL6V5U5, 0, 0, 0, 0, 0
734 },
735 {
736 "SVGA3D_BUMPX8L8V8U8",
José Fonseca974b6412011-04-27 12:02:08 +0100737 SVGA3D_BUMPX8L8V8U8,
738 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8,
Brian Paule0542512015-08-13 11:00:58 -0700739 1, 1, 4,
José Fonseca974b6412011-04-27 12:02:08 +0100740 SVGA3DFORMAT_OP_TEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700741 SVGA3DFORMAT_OP_CUBETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100742 },
José Fonseca974b6412011-04-27 12:02:08 +0100743 {
Brian Paule0542512015-08-13 11:00:58 -0700744 "SVGA3D_FORMAT_DEAD1",
745 SVGA3D_FORMAT_DEAD1, 0, 0, 0, 0, 0
746 },
747 {
748 "SVGA3D_ARGB_S10E5",
José Fonseca974b6412011-04-27 12:02:08 +0100749 SVGA3D_ARGB_S10E5,
750 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5,
Brian Paule0542512015-08-13 11:00:58 -0700751 1, 1, 2,
José Fonseca974b6412011-04-27 12:02:08 +0100752 SVGA3DFORMAT_OP_TEXTURE |
753 SVGA3DFORMAT_OP_CUBETEXTURE |
754 SVGA3DFORMAT_OP_VOLUMETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100755 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
756 },
757 {
Brian Paule0542512015-08-13 11:00:58 -0700758 "SVGA3D_ARGB_S23E8",
José Fonseca974b6412011-04-27 12:02:08 +0100759 SVGA3D_ARGB_S23E8,
760 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8,
Brian Paule0542512015-08-13 11:00:58 -0700761 1, 1, 4,
José Fonseca974b6412011-04-27 12:02:08 +0100762 SVGA3DFORMAT_OP_TEXTURE |
763 SVGA3DFORMAT_OP_CUBETEXTURE |
764 SVGA3DFORMAT_OP_VOLUMETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100765 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
766 },
767 {
Brian Paule0542512015-08-13 11:00:58 -0700768 "SVGA3D_A2R10G10B10",
José Fonseca974b6412011-04-27 12:02:08 +0100769 SVGA3D_A2R10G10B10,
770 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10,
Brian Paule0542512015-08-13 11:00:58 -0700771 1, 1, 4,
José Fonseca974b6412011-04-27 12:02:08 +0100772 SVGA3DFORMAT_OP_TEXTURE |
773 SVGA3DFORMAT_OP_CUBETEXTURE |
774 SVGA3DFORMAT_OP_VOLUMETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100775 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
776 },
José Fonseca974b6412011-04-27 12:02:08 +0100777 {
Brian Paule0542512015-08-13 11:00:58 -0700778 /*
779 * SVGA3D_V8U8 is unsupported; it has no corresponding
780 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPU8V8 should be used instead.
781 */
782 "SVGA3D_V8U8",
783 SVGA3D_V8U8, 0, 0, 0, 0, 0
784 },
785 {
786 "SVGA3D_Q8W8V8U8",
José Fonseca974b6412011-04-27 12:02:08 +0100787 SVGA3D_Q8W8V8U8,
788 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8,
Brian Paule0542512015-08-13 11:00:58 -0700789 1, 1, 4,
José Fonseca974b6412011-04-27 12:02:08 +0100790 SVGA3DFORMAT_OP_TEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700791 SVGA3DFORMAT_OP_CUBETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100792 },
793 {
Brian Paule0542512015-08-13 11:00:58 -0700794 "SVGA3D_CxV8U8",
José Fonseca974b6412011-04-27 12:02:08 +0100795 SVGA3D_CxV8U8,
796 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8,
Brian Paule0542512015-08-13 11:00:58 -0700797 1, 1, 2,
798 SVGA3DFORMAT_OP_TEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100799 },
José Fonseca974b6412011-04-27 12:02:08 +0100800 {
Brian Paule0542512015-08-13 11:00:58 -0700801 /*
802 * SVGA3D_X8L8V8U8 is unsupported; it has no corresponding
803 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPX8L8V8U8 should be used instead.
804 */
805 "SVGA3D_X8L8V8U8",
806 SVGA3D_X8L8V8U8, 0, 0, 0, 0, 0
807 },
808 {
809 "SVGA3D_A2W10V10U10",
José Fonseca974b6412011-04-27 12:02:08 +0100810 SVGA3D_A2W10V10U10,
811 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10,
Brian Paule0542512015-08-13 11:00:58 -0700812 1, 1, 4,
813 SVGA3DFORMAT_OP_TEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100814 },
815 {
Brian Paule0542512015-08-13 11:00:58 -0700816 "SVGA3D_ALPHA8",
José Fonseca974b6412011-04-27 12:02:08 +0100817 SVGA3D_ALPHA8,
818 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8,
Brian Paule0542512015-08-13 11:00:58 -0700819 1, 1, 1,
José Fonseca974b6412011-04-27 12:02:08 +0100820 SVGA3DFORMAT_OP_TEXTURE |
821 SVGA3DFORMAT_OP_CUBETEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700822 SVGA3DFORMAT_OP_VOLUMETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100823 },
824 {
Brian Paule0542512015-08-13 11:00:58 -0700825 "SVGA3D_R_S10E5",
José Fonseca974b6412011-04-27 12:02:08 +0100826 SVGA3D_R_S10E5,
827 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5,
Brian Paule0542512015-08-13 11:00:58 -0700828 1, 1, 2,
José Fonseca974b6412011-04-27 12:02:08 +0100829 SVGA3DFORMAT_OP_TEXTURE |
830 SVGA3DFORMAT_OP_VOLUMETEXTURE |
831 SVGA3DFORMAT_OP_CUBETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100832 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
833 },
834 {
Brian Paule0542512015-08-13 11:00:58 -0700835 "SVGA3D_R_S23E8",
José Fonseca974b6412011-04-27 12:02:08 +0100836 SVGA3D_R_S23E8,
837 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8,
Brian Paule0542512015-08-13 11:00:58 -0700838 1, 1, 4,
José Fonseca974b6412011-04-27 12:02:08 +0100839 SVGA3DFORMAT_OP_TEXTURE |
840 SVGA3DFORMAT_OP_VOLUMETEXTURE |
841 SVGA3DFORMAT_OP_CUBETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100842 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
843 },
844 {
Brian Paule0542512015-08-13 11:00:58 -0700845 "SVGA3D_RG_S10E5",
José Fonseca974b6412011-04-27 12:02:08 +0100846 SVGA3D_RG_S10E5,
847 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5,
Brian Paule0542512015-08-13 11:00:58 -0700848 1, 1, 2,
José Fonseca974b6412011-04-27 12:02:08 +0100849 SVGA3DFORMAT_OP_TEXTURE |
850 SVGA3DFORMAT_OP_VOLUMETEXTURE |
851 SVGA3DFORMAT_OP_CUBETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100852 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
853 },
854 {
Brian Paule0542512015-08-13 11:00:58 -0700855 "SVGA3D_RG_S23E8",
José Fonseca974b6412011-04-27 12:02:08 +0100856 SVGA3D_RG_S23E8,
857 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8,
Brian Paule0542512015-08-13 11:00:58 -0700858 1, 1, 4,
José Fonseca974b6412011-04-27 12:02:08 +0100859 SVGA3DFORMAT_OP_TEXTURE |
860 SVGA3DFORMAT_OP_VOLUMETEXTURE |
861 SVGA3DFORMAT_OP_CUBETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100862 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
863 },
José Fonseca974b6412011-04-27 12:02:08 +0100864 {
Brian Paule0542512015-08-13 11:00:58 -0700865 /*
866 * SVGA3D_BUFFER is a placeholder format for index/vertex buffers.
867 */
868 "SVGA3D_BUFFER",
869 SVGA3D_BUFFER, 0, 1, 1, 1, 0
870 },
871 {
872 "SVGA3D_Z_D24X8",
José Fonseca974b6412011-04-27 12:02:08 +0100873 SVGA3D_Z_D24X8,
874 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8,
Brian Paule0542512015-08-13 11:00:58 -0700875 1, 1, 4,
876 SVGA3DFORMAT_OP_ZSTENCIL
José Fonseca974b6412011-04-27 12:02:08 +0100877 },
878 {
Brian Paule0542512015-08-13 11:00:58 -0700879 "SVGA3D_V16U16",
José Fonseca974b6412011-04-27 12:02:08 +0100880 SVGA3D_V16U16,
881 SVGA3D_DEVCAP_SURFACEFMT_V16U16,
Brian Paule0542512015-08-13 11:00:58 -0700882 1, 1, 4,
José Fonseca974b6412011-04-27 12:02:08 +0100883 SVGA3DFORMAT_OP_TEXTURE |
884 SVGA3DFORMAT_OP_CUBETEXTURE |
Brian Paule0542512015-08-13 11:00:58 -0700885 SVGA3DFORMAT_OP_VOLUMETEXTURE
José Fonseca974b6412011-04-27 12:02:08 +0100886 },
887 {
Brian Paule0542512015-08-13 11:00:58 -0700888 "SVGA3D_G16R16",
José Fonseca974b6412011-04-27 12:02:08 +0100889 SVGA3D_G16R16,
890 SVGA3D_DEVCAP_SURFACEFMT_G16R16,
Brian Paule0542512015-08-13 11:00:58 -0700891 1, 1, 4,
José Fonseca974b6412011-04-27 12:02:08 +0100892 SVGA3DFORMAT_OP_TEXTURE |
893 SVGA3DFORMAT_OP_CUBETEXTURE |
894 SVGA3DFORMAT_OP_VOLUMETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100895 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
896 },
897 {
Brian Paule0542512015-08-13 11:00:58 -0700898 "SVGA3D_A16B16G16R16",
José Fonseca974b6412011-04-27 12:02:08 +0100899 SVGA3D_A16B16G16R16,
900 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16,
Brian Paule0542512015-08-13 11:00:58 -0700901 1, 1, 8,
José Fonseca974b6412011-04-27 12:02:08 +0100902 SVGA3DFORMAT_OP_TEXTURE |
903 SVGA3DFORMAT_OP_CUBETEXTURE |
904 SVGA3DFORMAT_OP_VOLUMETEXTURE |
José Fonseca974b6412011-04-27 12:02:08 +0100905 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
906 },
907 {
Brian Paule0542512015-08-13 11:00:58 -0700908 "SVGA3D_UYVY",
José Fonseca974b6412011-04-27 12:02:08 +0100909 SVGA3D_UYVY,
910 SVGA3D_DEVCAP_SURFACEFMT_UYVY,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600911 0, 0, 0, 0
José Fonseca974b6412011-04-27 12:02:08 +0100912 },
913 {
Brian Paule0542512015-08-13 11:00:58 -0700914 "SVGA3D_YUY2",
José Fonseca974b6412011-04-27 12:02:08 +0100915 SVGA3D_YUY2,
916 SVGA3D_DEVCAP_SURFACEFMT_YUY2,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600917 0, 0, 0, 0
José Fonseca974b6412011-04-27 12:02:08 +0100918 },
919 {
Brian Paule0542512015-08-13 11:00:58 -0700920 "SVGA3D_NV12",
José Fonseca974b6412011-04-27 12:02:08 +0100921 SVGA3D_NV12,
922 SVGA3D_DEVCAP_SURFACEFMT_NV12,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600923 0, 0, 0, 0
José Fonseca974b6412011-04-27 12:02:08 +0100924 },
925 {
Brian Paule0542512015-08-13 11:00:58 -0700926 "SVGA3D_AYUV",
José Fonseca974b6412011-04-27 12:02:08 +0100927 SVGA3D_AYUV,
928 SVGA3D_DEVCAP_SURFACEFMT_AYUV,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600929 0, 0, 0, 0
José Fonseca974b6412011-04-27 12:02:08 +0100930 },
931 {
Brian Paule0542512015-08-13 11:00:58 -0700932 "SVGA3D_R32G32B32A32_TYPELESS",
933 SVGA3D_R32G32B32A32_TYPELESS,
934 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600935 1, 1, 16, 0
Brian Paule0542512015-08-13 11:00:58 -0700936 },
937 {
938 "SVGA3D_R32G32B32A32_UINT",
939 SVGA3D_R32G32B32A32_UINT,
940 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600941 1, 1, 16, 0
Brian Paule0542512015-08-13 11:00:58 -0700942 },
943 {
944 "SVGA3D_R32G32B32A32_SINT",
945 SVGA3D_R32G32B32A32_SINT,
946 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600947 1, 1, 16, 0
Brian Paule0542512015-08-13 11:00:58 -0700948 },
949 {
950 "SVGA3D_R32G32B32_TYPELESS",
951 SVGA3D_R32G32B32_TYPELESS,
952 SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600953 1, 1, 12, 0
Brian Paule0542512015-08-13 11:00:58 -0700954 },
955 {
956 "SVGA3D_R32G32B32_FLOAT",
957 SVGA3D_R32G32B32_FLOAT,
958 SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600959 1, 1, 12, 0
Brian Paule0542512015-08-13 11:00:58 -0700960 },
961 {
962 "SVGA3D_R32G32B32_UINT",
963 SVGA3D_R32G32B32_UINT,
964 SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600965 1, 1, 12, 0
Brian Paule0542512015-08-13 11:00:58 -0700966 },
967 {
968 "SVGA3D_R32G32B32_SINT",
969 SVGA3D_R32G32B32_SINT,
970 SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600971 1, 1, 12, 0
Brian Paule0542512015-08-13 11:00:58 -0700972 },
973 {
974 "SVGA3D_R16G16B16A16_TYPELESS",
975 SVGA3D_R16G16B16A16_TYPELESS,
976 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600977 1, 1, 8, 0
Brian Paule0542512015-08-13 11:00:58 -0700978 },
979 {
980 "SVGA3D_R16G16B16A16_UINT",
981 SVGA3D_R16G16B16A16_UINT,
982 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600983 1, 1, 8, 0
Brian Paule0542512015-08-13 11:00:58 -0700984 },
985 {
986 "SVGA3D_R16G16B16A16_SNORM",
987 SVGA3D_R16G16B16A16_SNORM,
988 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600989 1, 1, 8, 0
Brian Paule0542512015-08-13 11:00:58 -0700990 },
991 {
992 "SVGA3D_R16G16B16A16_SINT",
993 SVGA3D_R16G16B16A16_SINT,
994 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -0600995 1, 1, 8, 0
Brian Paule0542512015-08-13 11:00:58 -0700996 },
997 {
998 "SVGA3D_R32G32_TYPELESS",
999 SVGA3D_R32G32_TYPELESS,
1000 SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001001 1, 1, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001002 },
1003 {
1004 "SVGA3D_R32G32_UINT",
1005 SVGA3D_R32G32_UINT,
1006 SVGA3D_DEVCAP_DXFMT_R32G32_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001007 1, 1, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001008 },
1009 {
1010 "SVGA3D_R32G32_SINT",
1011 SVGA3D_R32G32_SINT,
1012 SVGA3D_DEVCAP_DXFMT_R32G32_SINT,
1013 1, 1, 8,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001014 0
Brian Paule0542512015-08-13 11:00:58 -07001015 },
1016 {
1017 "SVGA3D_R32G8X24_TYPELESS",
1018 SVGA3D_R32G8X24_TYPELESS,
1019 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001020 1, 1, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001021 },
1022 {
1023 /* Special case: no devcap / report sampler and depth/stencil ability
1024 */
1025 "SVGA3D_D32_FLOAT_S8X24_UINT",
1026 SVGA3D_D32_FLOAT_S8X24_UINT,
1027 0, /*SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT*/
1028 1, 1, 8,
1029 SVGA3DFORMAT_OP_TEXTURE |
1030 SVGA3DFORMAT_OP_CUBETEXTURE |
1031 SVGA3DFORMAT_OP_VOLUMETEXTURE |
1032 SVGA3DFORMAT_OP_ZSTENCIL
1033 },
1034 {
1035 /* Special case: no devcap / report sampler and depth/stencil ability
1036 */
Brian Paul07823502017-06-28 16:43:52 -06001037 "SVGA3D_R32_FLOAT_X8X24",
1038 SVGA3D_R32_FLOAT_X8X24,
Brian Paule0542512015-08-13 11:00:58 -07001039 0, /*SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS*/
1040 1, 1, 8,
1041 SVGA3DFORMAT_OP_TEXTURE |
1042 SVGA3DFORMAT_OP_CUBETEXTURE |
1043 SVGA3DFORMAT_OP_VOLUMETEXTURE |
1044 SVGA3DFORMAT_OP_ZSTENCIL
1045 },
1046 {
Brian Paul07823502017-06-28 16:43:52 -06001047 "SVGA3D_X32_G8X24_UINT",
1048 SVGA3D_X32_G8X24_UINT,
Brian Paule0542512015-08-13 11:00:58 -07001049 SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001050 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001051 },
1052 {
1053 "SVGA3D_R10G10B10A2_TYPELESS",
1054 SVGA3D_R10G10B10A2_TYPELESS,
1055 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001056 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001057 },
1058 {
1059 "SVGA3D_R10G10B10A2_UINT",
1060 SVGA3D_R10G10B10A2_UINT,
1061 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001062 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001063 },
1064 {
1065 "SVGA3D_R11G11B10_FLOAT",
1066 SVGA3D_R11G11B10_FLOAT,
1067 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001068 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001069 },
1070 {
1071 "SVGA3D_R8G8B8A8_TYPELESS",
1072 SVGA3D_R8G8B8A8_TYPELESS,
1073 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001074 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001075 },
1076 {
1077 "SVGA3D_R8G8B8A8_UNORM",
1078 SVGA3D_R8G8B8A8_UNORM,
1079 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001080 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001081 },
1082 {
1083 "SVGA3D_R8G8B8A8_UNORM_SRGB",
1084 SVGA3D_R8G8B8A8_UNORM_SRGB,
1085 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001086 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001087 },
1088 {
1089 "SVGA3D_R8G8B8A8_UINT",
1090 SVGA3D_R8G8B8A8_UINT,
1091 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001092 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001093 },
1094 {
1095 "SVGA3D_R8G8B8A8_SINT",
1096 SVGA3D_R8G8B8A8_SINT,
1097 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001098 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001099 },
1100 {
1101 "SVGA3D_R16G16_TYPELESS",
1102 SVGA3D_R16G16_TYPELESS,
1103 SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001104 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001105 },
1106 {
1107 "SVGA3D_R16G16_UINT",
1108 SVGA3D_R16G16_UINT,
1109 SVGA3D_DEVCAP_DXFMT_R16G16_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001110 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001111 },
1112 {
1113 "SVGA3D_R16G16_SINT",
1114 SVGA3D_R16G16_SINT,
1115 SVGA3D_DEVCAP_DXFMT_R16G16_SINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001116 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001117 },
1118 {
1119 "SVGA3D_R32_TYPELESS",
1120 SVGA3D_R32_TYPELESS,
1121 SVGA3D_DEVCAP_DXFMT_R32_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001122 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001123 },
1124 {
1125 /* Special case: no devcap / report sampler and depth/stencil ability
1126 */
1127 "SVGA3D_D32_FLOAT",
1128 SVGA3D_D32_FLOAT,
1129 0, /*SVGA3D_DEVCAP_DXFMT_D32_FLOAT*/
1130 1, 1, 4,
1131 SVGA3DFORMAT_OP_TEXTURE |
1132 SVGA3DFORMAT_OP_CUBETEXTURE |
1133 SVGA3DFORMAT_OP_VOLUMETEXTURE |
1134 SVGA3DFORMAT_OP_ZSTENCIL
1135 },
1136 {
1137 "SVGA3D_R32_UINT",
1138 SVGA3D_R32_UINT,
1139 SVGA3D_DEVCAP_DXFMT_R32_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001140 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001141 },
1142 {
1143 "SVGA3D_R32_SINT",
1144 SVGA3D_R32_SINT,
1145 SVGA3D_DEVCAP_DXFMT_R32_SINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001146 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001147 },
1148 {
1149 "SVGA3D_R24G8_TYPELESS",
1150 SVGA3D_R24G8_TYPELESS,
1151 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001152 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001153 },
1154 {
1155 /* Special case: no devcap / report sampler and depth/stencil ability
1156 */
1157 "SVGA3D_D24_UNORM_S8_UINT",
1158 SVGA3D_D24_UNORM_S8_UINT,
1159 0, /*SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT*/
1160 1, 1, 4,
1161 SVGA3DFORMAT_OP_TEXTURE |
1162 SVGA3DFORMAT_OP_CUBETEXTURE |
1163 SVGA3DFORMAT_OP_VOLUMETEXTURE |
1164 SVGA3DFORMAT_OP_ZSTENCIL
1165 },
1166 {
1167 /* Special case: no devcap / report sampler and depth/stencil ability
1168 */
Brian Paul07823502017-06-28 16:43:52 -06001169 "SVGA3D_R24_UNORM_X8",
1170 SVGA3D_R24_UNORM_X8,
Brian Paule0542512015-08-13 11:00:58 -07001171 0, /*SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS*/
1172 1, 1, 4,
1173 SVGA3DFORMAT_OP_TEXTURE |
1174 SVGA3DFORMAT_OP_CUBETEXTURE |
1175 SVGA3DFORMAT_OP_VOLUMETEXTURE |
1176 SVGA3DFORMAT_OP_ZSTENCIL
1177 },
1178 {
Brian Paul07823502017-06-28 16:43:52 -06001179 "SVGA3D_X24_G8_UINT",
1180 SVGA3D_X24_G8_UINT,
Brian Paule0542512015-08-13 11:00:58 -07001181 SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001182 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001183 },
1184 {
1185 "SVGA3D_R8G8_TYPELESS",
1186 SVGA3D_R8G8_TYPELESS,
1187 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001188 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001189 },
1190 {
1191 "SVGA3D_R8G8_UNORM",
1192 SVGA3D_R8G8_UNORM,
1193 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001194 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001195 },
1196 {
1197 "SVGA3D_R8G8_UINT",
1198 SVGA3D_R8G8_UINT,
1199 SVGA3D_DEVCAP_DXFMT_R8G8_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001200 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001201 },
1202 {
1203 "SVGA3D_R8G8_SINT",
1204 SVGA3D_R8G8_SINT,
1205 SVGA3D_DEVCAP_DXFMT_R8G8_SINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001206 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001207 },
1208 {
1209 "SVGA3D_R16_TYPELESS",
1210 SVGA3D_R16_TYPELESS,
1211 SVGA3D_DEVCAP_DXFMT_R16_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001212 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001213 },
1214 {
1215 "SVGA3D_R16_UNORM",
1216 SVGA3D_R16_UNORM,
1217 SVGA3D_DEVCAP_DXFMT_R16_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001218 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001219 },
1220 {
1221 "SVGA3D_R16_UINT",
1222 SVGA3D_R16_UINT,
1223 SVGA3D_DEVCAP_DXFMT_R16_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001224 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001225 },
1226 {
1227 "SVGA3D_R16_SNORM",
1228 SVGA3D_R16_SNORM,
1229 SVGA3D_DEVCAP_DXFMT_R16_SNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001230 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001231 },
1232 {
1233 "SVGA3D_R16_SINT",
1234 SVGA3D_R16_SINT,
1235 SVGA3D_DEVCAP_DXFMT_R16_SINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001236 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001237 },
1238 {
1239 "SVGA3D_R8_TYPELESS",
1240 SVGA3D_R8_TYPELESS,
1241 SVGA3D_DEVCAP_DXFMT_R8_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001242 1, 1, 1, 0
Brian Paule0542512015-08-13 11:00:58 -07001243 },
1244 {
1245 "SVGA3D_R8_UNORM",
1246 SVGA3D_R8_UNORM,
1247 SVGA3D_DEVCAP_DXFMT_R8_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001248 1, 1, 1, 0
Brian Paule0542512015-08-13 11:00:58 -07001249 },
1250 {
1251 "SVGA3D_R8_UINT",
1252 SVGA3D_R8_UINT,
1253 SVGA3D_DEVCAP_DXFMT_R8_UINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001254 1, 1, 1, 0
Brian Paule0542512015-08-13 11:00:58 -07001255 },
1256 {
1257 "SVGA3D_R8_SNORM",
1258 SVGA3D_R8_SNORM,
1259 SVGA3D_DEVCAP_DXFMT_R8_SNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001260 1, 1, 1, 0
Brian Paule0542512015-08-13 11:00:58 -07001261 },
1262 {
1263 "SVGA3D_R8_SINT",
1264 SVGA3D_R8_SINT,
1265 SVGA3D_DEVCAP_DXFMT_R8_SINT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001266 1, 1, 1, 0
Brian Paule0542512015-08-13 11:00:58 -07001267 },
1268 {
1269 "SVGA3D_P8",
1270 SVGA3D_P8, 0, 0, 0, 0, 0
1271 },
1272 {
1273 "SVGA3D_R9G9B9E5_SHAREDEXP",
1274 SVGA3D_R9G9B9E5_SHAREDEXP,
1275 SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001276 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001277 },
1278 {
1279 "SVGA3D_R8G8_B8G8_UNORM",
1280 SVGA3D_R8G8_B8G8_UNORM, 0, 0, 0, 0, 0
1281 },
1282 {
1283 "SVGA3D_G8R8_G8B8_UNORM",
1284 SVGA3D_G8R8_G8B8_UNORM, 0, 0, 0, 0, 0
1285 },
1286 {
1287 "SVGA3D_BC1_TYPELESS",
Brian Paul1a483262015-11-16 10:41:20 -07001288 SVGA3D_BC1_TYPELESS,
1289 SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001290 4, 4, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001291 },
1292 {
1293 "SVGA3D_BC1_UNORM_SRGB",
Brian Paul1a483262015-11-16 10:41:20 -07001294 SVGA3D_BC1_UNORM_SRGB,
1295 SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001296 4, 4, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001297 },
1298 {
1299 "SVGA3D_BC2_TYPELESS",
Brian Paul1a483262015-11-16 10:41:20 -07001300 SVGA3D_BC2_TYPELESS,
1301 SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001302 4, 4, 16, 0
Brian Paule0542512015-08-13 11:00:58 -07001303 },
1304 {
1305 "SVGA3D_BC2_UNORM_SRGB",
Brian Paul1a483262015-11-16 10:41:20 -07001306 SVGA3D_BC2_UNORM_SRGB,
1307 SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001308 4, 4, 16, 0
Brian Paule0542512015-08-13 11:00:58 -07001309 },
1310 {
1311 "SVGA3D_BC3_TYPELESS",
Brian Paul1a483262015-11-16 10:41:20 -07001312 SVGA3D_BC3_TYPELESS,
1313 SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001314 4, 4, 16, 0
Brian Paule0542512015-08-13 11:00:58 -07001315 },
1316 {
1317 "SVGA3D_BC3_UNORM_SRGB",
Brian Paul1a483262015-11-16 10:41:20 -07001318 SVGA3D_BC3_UNORM_SRGB,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001319 4, 4, 16, 0
Brian Paule0542512015-08-13 11:00:58 -07001320 },
1321 {
1322 "SVGA3D_BC4_TYPELESS",
1323 SVGA3D_BC4_TYPELESS,
1324 SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001325 4, 4, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001326 },
1327 {
1328 "SVGA3D_ATI1",
1329 SVGA3D_ATI1, 0, 0, 0, 0, 0
1330 },
1331 {
1332 "SVGA3D_BC4_SNORM",
1333 SVGA3D_BC4_SNORM,
1334 SVGA3D_DEVCAP_DXFMT_BC4_SNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001335 4, 4, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001336 },
1337 {
1338 "SVGA3D_BC5_TYPELESS",
1339 SVGA3D_BC5_TYPELESS,
1340 SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001341 4, 4, 16, 0
Brian Paule0542512015-08-13 11:00:58 -07001342 },
1343 {
1344 "SVGA3D_ATI2",
1345 SVGA3D_ATI2, 0, 0, 0, 0, 0
1346 },
1347 {
1348 "SVGA3D_BC5_SNORM",
1349 SVGA3D_BC5_SNORM,
1350 SVGA3D_DEVCAP_DXFMT_BC5_SNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001351 4, 4, 16, 0
Brian Paule0542512015-08-13 11:00:58 -07001352 },
1353 {
1354 "SVGA3D_R10G10B10_XR_BIAS_A2_UNORM",
1355 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, 0, 0, 0, 0, 0
1356 },
1357 {
1358 "SVGA3D_B8G8R8A8_TYPELESS",
1359 SVGA3D_B8G8R8A8_TYPELESS,
1360 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001361 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001362 },
1363 {
1364 "SVGA3D_B8G8R8A8_UNORM_SRGB",
1365 SVGA3D_B8G8R8A8_UNORM_SRGB,
1366 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001367 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001368 },
1369 {
1370 "SVGA3D_B8G8R8X8_TYPELESS",
1371 SVGA3D_B8G8R8X8_TYPELESS,
1372 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001373 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001374 },
1375 {
1376 "SVGA3D_B8G8R8X8_UNORM_SRGB",
1377 SVGA3D_B8G8R8X8_UNORM_SRGB,
1378 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001379 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001380 },
1381 {
1382 "SVGA3D_Z_DF16",
José Fonseca974b6412011-04-27 12:02:08 +01001383 SVGA3D_Z_DF16,
1384 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001385 1, 1, 2, 0
José Fonseca974b6412011-04-27 12:02:08 +01001386 },
1387 {
Brian Paule0542512015-08-13 11:00:58 -07001388 "SVGA3D_Z_DF24",
José Fonseca974b6412011-04-27 12:02:08 +01001389 SVGA3D_Z_DF24,
1390 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001391 1, 1, 4, 0
José Fonseca974b6412011-04-27 12:02:08 +01001392 },
1393 {
Brian Paule0542512015-08-13 11:00:58 -07001394 "SVGA3D_Z_D24S8_INT",
José Fonseca974b6412011-04-27 12:02:08 +01001395 SVGA3D_Z_D24S8_INT,
1396 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001397 1, 1, 4, 0
José Fonseca974b6412011-04-27 12:02:08 +01001398 },
Brian Paule0542512015-08-13 11:00:58 -07001399 {
1400 "SVGA3D_YV12",
1401 SVGA3D_YV12, 0, 0, 0, 0, 0
1402 },
1403 {
1404 "SVGA3D_R32G32B32A32_FLOAT",
1405 SVGA3D_R32G32B32A32_FLOAT,
1406 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001407 1, 1, 16, 0
Brian Paule0542512015-08-13 11:00:58 -07001408 },
1409 {
1410 "SVGA3D_R16G16B16A16_FLOAT",
1411 SVGA3D_R16G16B16A16_FLOAT,
1412 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001413 1, 1, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001414 },
1415 {
1416 "SVGA3D_R16G16B16A16_UNORM",
1417 SVGA3D_R16G16B16A16_UNORM,
1418 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001419 1, 1, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001420 },
1421 {
1422 "SVGA3D_R32G32_FLOAT",
1423 SVGA3D_R32G32_FLOAT,
1424 SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001425 1, 1, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001426 },
1427 {
1428 "SVGA3D_R10G10B10A2_UNORM",
1429 SVGA3D_R10G10B10A2_UNORM,
1430 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001431 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001432 },
1433 {
1434 "SVGA3D_R8G8B8A8_SNORM",
1435 SVGA3D_R8G8B8A8_SNORM,
1436 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001437 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001438 },
1439 {
1440 "SVGA3D_R16G16_FLOAT",
1441 SVGA3D_R16G16_FLOAT,
1442 SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001443 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001444 },
1445 {
1446 "SVGA3D_R16G16_UNORM",
1447 SVGA3D_R16G16_UNORM,
1448 SVGA3D_DEVCAP_DXFMT_R16G16_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001449 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001450 },
1451 {
1452 "SVGA3D_R16G16_SNORM",
1453 SVGA3D_R16G16_SNORM,
1454 SVGA3D_DEVCAP_DXFMT_R16G16_SNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001455 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001456 },
1457 {
Brian Paule0542512015-08-13 11:00:58 -07001458 "SVGA3D_R32_FLOAT",
1459 SVGA3D_R32_FLOAT,
Brian Paulf942a702016-09-22 09:15:20 -06001460 SVGA3D_DEVCAP_DXFMT_R32_FLOAT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001461 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001462 },
1463 {
1464 "SVGA3D_R8G8_SNORM",
1465 SVGA3D_R8G8_SNORM,
1466 SVGA3D_DEVCAP_DXFMT_R8G8_SNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001467 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001468 },
1469 {
1470 "SVGA3D_R16_FLOAT",
1471 SVGA3D_R16_FLOAT,
1472 SVGA3D_DEVCAP_DXFMT_R16_FLOAT,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001473 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001474 },
1475 {
1476 "SVGA3D_D16_UNORM",
1477 SVGA3D_D16_UNORM,
Brian Paul1a483262015-11-16 10:41:20 -07001478 0, /*SVGA3D_DEVCAP_DXFMT_D16_UNORM*/
Brian Paule0542512015-08-13 11:00:58 -07001479 1, 1, 2,
1480 SVGA3DFORMAT_OP_TEXTURE |
1481 SVGA3DFORMAT_OP_CUBETEXTURE |
1482 SVGA3DFORMAT_OP_VOLUMETEXTURE |
1483 SVGA3DFORMAT_OP_ZSTENCIL
1484 },
1485 {
1486 "SVGA3D_A8_UNORM",
1487 SVGA3D_A8_UNORM,
1488 SVGA3D_DEVCAP_DXFMT_A8_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001489 1, 1, 1, 0
Brian Paule0542512015-08-13 11:00:58 -07001490 },
1491 {
1492 "SVGA3D_BC1_UNORM",
Brian Paul1a483262015-11-16 10:41:20 -07001493 SVGA3D_BC1_UNORM,
1494 SVGA3D_DEVCAP_DXFMT_BC1_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001495 4, 4, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001496 },
1497 {
1498 "SVGA3D_BC2_UNORM",
Brian Paul1a483262015-11-16 10:41:20 -07001499 SVGA3D_BC2_UNORM,
1500 SVGA3D_DEVCAP_DXFMT_BC2_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001501 4, 4, 16, 0
Brian Paule0542512015-08-13 11:00:58 -07001502 },
1503 {
1504 "SVGA3D_BC3_UNORM",
Brian Paul1a483262015-11-16 10:41:20 -07001505 SVGA3D_BC3_UNORM,
1506 SVGA3D_DEVCAP_DXFMT_BC3_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001507 4, 4, 16, 0
Brian Paule0542512015-08-13 11:00:58 -07001508 },
1509 {
1510 "SVGA3D_B5G6R5_UNORM",
1511 SVGA3D_B5G6R5_UNORM,
1512 SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001513 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001514 },
1515 {
1516 "SVGA3D_B5G5R5A1_UNORM",
1517 SVGA3D_B5G5R5A1_UNORM,
1518 SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001519 1, 1, 2, 0
Brian Paule0542512015-08-13 11:00:58 -07001520 },
1521 {
1522 "SVGA3D_B8G8R8A8_UNORM",
1523 SVGA3D_B8G8R8A8_UNORM,
1524 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001525 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001526 },
1527 {
1528 "SVGA3D_B8G8R8X8_UNORM",
1529 SVGA3D_B8G8R8X8_UNORM,
1530 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001531 1, 1, 4, 0
Brian Paule0542512015-08-13 11:00:58 -07001532 },
1533 {
1534 "SVGA3D_BC4_UNORM",
1535 SVGA3D_BC4_UNORM,
1536 SVGA3D_DEVCAP_DXFMT_BC4_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001537 4, 4, 8, 0
Brian Paule0542512015-08-13 11:00:58 -07001538 },
1539 {
1540 "SVGA3D_BC5_UNORM",
1541 SVGA3D_BC5_UNORM,
1542 SVGA3D_DEVCAP_DXFMT_BC5_UNORM,
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001543 4, 4, 16, 0
Brian Paule0542512015-08-13 11:00:58 -07001544 }
José Fonseca974b6412011-04-27 12:02:08 +01001545};
1546
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001547static const SVGA3dSurfaceFormat compat_x8r8g8b8[] = {
1548 SVGA3D_X8R8G8B8, SVGA3D_A8R8G8B8, SVGA3D_B8G8R8X8_UNORM,
1549 SVGA3D_B8G8R8A8_UNORM, 0
1550};
1551static const SVGA3dSurfaceFormat compat_r8[] = {
1552 SVGA3D_R8_UNORM, SVGA3D_NV12, SVGA3D_YV12, 0
1553};
1554static const SVGA3dSurfaceFormat compat_g8r8[] = {
1555 SVGA3D_R8G8_UNORM, SVGA3D_NV12, 0
1556};
Thomas Hellstrom1887faf2017-05-30 15:02:19 +02001557static const SVGA3dSurfaceFormat compat_r5g6b5[] = {
1558 SVGA3D_R5G6B5, SVGA3D_B5G6R5_UNORM, 0
1559};
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001560
1561static const struct format_compat_entry format_compats[] = {
1562 {PIPE_FORMAT_B8G8R8X8_UNORM, compat_x8r8g8b8},
1563 {PIPE_FORMAT_B8G8R8A8_UNORM, compat_x8r8g8b8},
1564 {PIPE_FORMAT_R8_UNORM, compat_r8},
Thomas Hellstrom1887faf2017-05-30 15:02:19 +02001565 {PIPE_FORMAT_R8G8_UNORM, compat_g8r8},
1566 {PIPE_FORMAT_B5G6R5_UNORM, compat_r5g6b5}
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001567};
José Fonseca974b6412011-04-27 12:02:08 +01001568
Brian Paule0542512015-08-13 11:00:58 -07001569/**
1570 * Debug only:
1571 * 1. check that format_cap_table[i] matches the i-th SVGA3D format.
1572 * 2. check that format_conversion_table[i].pformat == i.
1573 */
1574static void
1575check_format_tables(void)
1576{
1577 static boolean first_call = TRUE;
1578
1579 if (first_call) {
1580 unsigned i;
1581
Brian Paule0184b32016-04-25 09:34:40 -06001582 STATIC_ASSERT(ARRAY_SIZE(format_cap_table) == SVGA3D_FORMAT_MAX);
1583 for (i = 0; i < ARRAY_SIZE(format_cap_table); i++) {
Brian Paule0542512015-08-13 11:00:58 -07001584 assert(format_cap_table[i].format == i);
1585 }
1586
Brian Paule0184b32016-04-25 09:34:40 -06001587 STATIC_ASSERT(ARRAY_SIZE(format_conversion_table) == PIPE_FORMAT_COUNT);
1588 for (i = 0; i < ARRAY_SIZE(format_conversion_table); i++) {
Brian Paule0542512015-08-13 11:00:58 -07001589 assert(format_conversion_table[i].pformat == i);
1590 }
1591
1592 first_call = FALSE;
1593 }
1594}
1595
1596
José Fonseca974b6412011-04-27 12:02:08 +01001597/*
1598 * Get format capabilities from the host. It takes in consideration
1599 * deprecated/unsupported formats, and formats which are implicitely assumed to
1600 * be supported when the host does not provide an explicit capability entry.
1601 */
1602void
1603svga_get_format_cap(struct svga_screen *ss,
1604 SVGA3dSurfaceFormat format,
1605 SVGA3dSurfaceFormatCaps *caps)
1606{
Brian Paule0542512015-08-13 11:00:58 -07001607 struct svga_winsys_screen *sws = ss->sws;
1608 SVGA3dDevCapResult result;
José Fonseca974b6412011-04-27 12:02:08 +01001609 const struct format_cap *entry;
1610
Brian Paule0542512015-08-13 11:00:58 -07001611#ifdef DEBUG
1612 check_format_tables();
1613#else
1614 (void) check_format_tables;
1615#endif
José Fonseca974b6412011-04-27 12:02:08 +01001616
Brian Paule0184b32016-04-25 09:34:40 -06001617 assert(format < ARRAY_SIZE(format_cap_table));
Brian Paule0542512015-08-13 11:00:58 -07001618 entry = &format_cap_table[format];
1619 assert(entry->format == format);
José Fonseca974b6412011-04-27 12:02:08 +01001620
Brian Paule0542512015-08-13 11:00:58 -07001621 if (entry->devcap && sws->get_cap(sws, entry->devcap, &result)) {
Charmaine Leeb2e78e72017-06-26 14:18:33 -06001622 assert(format < SVGA3D_UYVY || entry->defaultOperations == 0);
1623
Brian Paule0542512015-08-13 11:00:58 -07001624 /* Explicitly advertised format */
1625 if (entry->devcap > SVGA3D_DEVCAP_DX) {
1626 /* Translate DX/VGPU10 format cap to VGPU9 cap */
1627 caps->value = 0;
1628 if (result.u & SVGA3D_DXFMT_COLOR_RENDERTARGET)
1629 caps->value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
1630 if (!(result.u & SVGA3D_DXFMT_BLENDABLE))
1631 caps->value |= SVGA3DFORMAT_OP_NOALPHABLEND;
1632 if (result.u & SVGA3D_DXFMT_DEPTH_RENDERTARGET)
1633 caps->value |= SVGA3DFORMAT_OP_ZSTENCIL;
1634 if (result.u & SVGA3D_DXFMT_SHADER_SAMPLE)
1635 caps->value |= (SVGA3DFORMAT_OP_TEXTURE |
1636 SVGA3DFORMAT_OP_CUBETEXTURE);
1637 if (result.u & SVGA3D_DXFMT_VOLUME)
1638 caps->value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
José Fonseca974b6412011-04-27 12:02:08 +01001639 }
Brian Paule0542512015-08-13 11:00:58 -07001640 else {
1641 /* Return VGPU9 format cap as-is */
1642 caps->value = result.u;
1643 }
José Fonseca974b6412011-04-27 12:02:08 +01001644
Brian Paule0542512015-08-13 11:00:58 -07001645 } else {
1646 /* Implicitly advertised format -- use default caps */
1647 caps->value = entry->defaultOperations;
1648 }
José Fonseca974b6412011-04-27 12:02:08 +01001649}
Brian Paul32f669e2011-12-07 17:05:48 -07001650
1651
Brian Paul32f669e2011-12-07 17:05:48 -07001652void
1653svga_format_size(SVGA3dSurfaceFormat format,
1654 unsigned *block_width,
1655 unsigned *block_height,
1656 unsigned *bytes_per_block)
1657{
Brian Paule0184b32016-04-25 09:34:40 -06001658 assert(format < ARRAY_SIZE(format_cap_table));
Brian Paule0542512015-08-13 11:00:58 -07001659 *block_width = format_cap_table[format].block_width;
1660 *block_height = format_cap_table[format].block_height;
1661 *bytes_per_block = format_cap_table[format].block_bytes;
Giuseppe Bilotta60a27ad2016-06-23 19:20:18 +02001662 /* Make sure the table entry was valid */
Brian Paule0542512015-08-13 11:00:58 -07001663 if (*block_width == 0)
1664 debug_printf("Bad table entry for %s\n", svga_format_name(format));
1665 assert(*block_width);
1666 assert(*block_height);
1667 assert(*bytes_per_block);
1668}
Brian Paul32f669e2011-12-07 17:05:48 -07001669
Brian Paule0542512015-08-13 11:00:58 -07001670
1671const char *
1672svga_format_name(SVGA3dSurfaceFormat format)
1673{
Brian Paule0184b32016-04-25 09:34:40 -06001674 assert(format < ARRAY_SIZE(format_cap_table));
Brian Paule0542512015-08-13 11:00:58 -07001675 return format_cap_table[format].name;
1676}
1677
1678
1679/**
1680 * Is the given SVGA3dSurfaceFormat a signed or unsigned integer color format?
1681 */
1682boolean
1683svga_format_is_integer(SVGA3dSurfaceFormat format)
1684{
Brian Paul32f669e2011-12-07 17:05:48 -07001685 switch (format) {
Brian Paule0542512015-08-13 11:00:58 -07001686 case SVGA3D_R32G32B32A32_SINT:
1687 case SVGA3D_R32G32B32_SINT:
1688 case SVGA3D_R32G32_SINT:
1689 case SVGA3D_R32_SINT:
1690 case SVGA3D_R16G16B16A16_SINT:
1691 case SVGA3D_R16G16_SINT:
1692 case SVGA3D_R16_SINT:
1693 case SVGA3D_R8G8B8A8_SINT:
1694 case SVGA3D_R8G8_SINT:
1695 case SVGA3D_R8_SINT:
1696 case SVGA3D_R32G32B32A32_UINT:
1697 case SVGA3D_R32G32B32_UINT:
1698 case SVGA3D_R32G32_UINT:
1699 case SVGA3D_R32_UINT:
1700 case SVGA3D_R16G16B16A16_UINT:
1701 case SVGA3D_R16G16_UINT:
1702 case SVGA3D_R16_UINT:
1703 case SVGA3D_R8G8B8A8_UINT:
1704 case SVGA3D_R8G8_UINT:
1705 case SVGA3D_R8_UINT:
1706 case SVGA3D_R10G10B10A2_UINT:
1707 return TRUE;
1708 default:
1709 return FALSE;
1710 }
1711}
Brian Paul32f669e2011-12-07 17:05:48 -07001712
Charmaine Lee63032312015-12-22 11:20:41 -08001713boolean
1714svga_format_support_gen_mips(enum pipe_format format)
1715{
Brian Paule0184b32016-04-25 09:34:40 -06001716 assert(format < ARRAY_SIZE(format_conversion_table));
Charmaine Lee63032312015-12-22 11:20:41 -08001717 return ((format_conversion_table[format].flags & TF_GEN_MIPS) > 0);
1718}
1719
Brian Paule0542512015-08-13 11:00:58 -07001720
1721/**
1722 * Given a texture format, return the expected data type returned from
1723 * the texture sampler. For example, UNORM8 formats return floating point
1724 * values while SINT formats returned signed integer values.
1725 * Note: this function could be moved into the gallum u_format.[ch] code
1726 * if it's useful to anyone else.
1727 */
1728enum tgsi_return_type
1729svga_get_texture_datatype(enum pipe_format format)
1730{
1731 const struct util_format_description *desc = util_format_description(format);
1732 enum tgsi_return_type t;
1733
1734 if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN ) {
1735 if (util_format_is_depth_or_stencil(format)) {
1736 t = TGSI_RETURN_TYPE_FLOAT; /* XXX revisit this */
1737 }
1738 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) {
1739 t = TGSI_RETURN_TYPE_FLOAT;
1740 }
1741 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1742 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_UNORM : TGSI_RETURN_TYPE_UINT;
1743 }
1744 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
1745 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_SNORM : TGSI_RETURN_TYPE_SINT;
1746 }
1747 else {
1748 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1749 t = TGSI_RETURN_TYPE_FLOAT;
1750 }
1751 }
1752 else {
1753 /* compressed format, shared exponent format, etc. */
1754 switch (format) {
1755 case PIPE_FORMAT_DXT1_RGB:
1756 case PIPE_FORMAT_DXT1_RGBA:
1757 case PIPE_FORMAT_DXT3_RGBA:
1758 case PIPE_FORMAT_DXT5_RGBA:
1759 case PIPE_FORMAT_DXT1_SRGB:
1760 case PIPE_FORMAT_DXT1_SRGBA:
1761 case PIPE_FORMAT_DXT3_SRGBA:
1762 case PIPE_FORMAT_DXT5_SRGBA:
1763 case PIPE_FORMAT_RGTC1_UNORM:
1764 case PIPE_FORMAT_RGTC2_UNORM:
1765 case PIPE_FORMAT_LATC1_UNORM:
1766 case PIPE_FORMAT_LATC2_UNORM:
1767 case PIPE_FORMAT_ETC1_RGB8:
1768 t = TGSI_RETURN_TYPE_UNORM;
1769 break;
1770 case PIPE_FORMAT_RGTC1_SNORM:
1771 case PIPE_FORMAT_RGTC2_SNORM:
1772 case PIPE_FORMAT_LATC1_SNORM:
1773 case PIPE_FORMAT_LATC2_SNORM:
1774 case PIPE_FORMAT_R10G10B10X2_SNORM:
1775 t = TGSI_RETURN_TYPE_SNORM;
1776 break;
1777 case PIPE_FORMAT_R11G11B10_FLOAT:
1778 case PIPE_FORMAT_R9G9B9E5_FLOAT:
1779 t = TGSI_RETURN_TYPE_FLOAT;
1780 break;
1781 default:
1782 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1783 t = TGSI_RETURN_TYPE_FLOAT;
1784 }
1785 }
1786
1787 return t;
1788}
1789
1790
1791/**
1792 * Given an svga context, return true iff there are currently any integer color
1793 * buffers attached to the framebuffer.
1794 */
1795boolean
1796svga_has_any_integer_cbufs(const struct svga_context *svga)
1797{
1798 unsigned i;
1799 for (i = 0; i < PIPE_MAX_COLOR_BUFS; ++i) {
1800 struct pipe_surface *cbuf = svga->curr.framebuffer.cbufs[i];
1801
1802 if (cbuf && util_format_is_pure_integer(cbuf->format)) {
1803 return TRUE;
1804 }
1805 }
1806 return FALSE;
1807}
1808
1809
1810/**
1811 * Given an SVGA format, return the corresponding typeless format.
1812 * If there is no typeless format, return the format unchanged.
1813 */
1814SVGA3dSurfaceFormat
1815svga_typeless_format(SVGA3dSurfaceFormat format)
1816{
1817 switch (format) {
1818 case SVGA3D_R32G32B32A32_UINT:
1819 case SVGA3D_R32G32B32A32_SINT:
1820 case SVGA3D_R32G32B32A32_FLOAT:
1821 return SVGA3D_R32G32B32A32_TYPELESS;
1822 case SVGA3D_R32G32B32_FLOAT:
1823 case SVGA3D_R32G32B32_UINT:
1824 case SVGA3D_R32G32B32_SINT:
1825 return SVGA3D_R32G32B32_TYPELESS;
1826 case SVGA3D_R16G16B16A16_UINT:
1827 case SVGA3D_R16G16B16A16_UNORM:
1828 case SVGA3D_R16G16B16A16_SNORM:
1829 case SVGA3D_R16G16B16A16_SINT:
1830 case SVGA3D_R16G16B16A16_FLOAT:
1831 return SVGA3D_R16G16B16A16_TYPELESS;
1832 case SVGA3D_R32G32_UINT:
1833 case SVGA3D_R32G32_SINT:
1834 case SVGA3D_R32G32_FLOAT:
1835 return SVGA3D_R32G32_TYPELESS;
1836 case SVGA3D_D32_FLOAT_S8X24_UINT:
Brian Paulb7c08e52017-06-27 10:00:58 -06001837 case SVGA3D_X32_G8X24_UINT:
Brian Paulcbe72ae2017-06-26 20:49:35 -06001838 case SVGA3D_R32G8X24_TYPELESS:
Brian Paule0542512015-08-13 11:00:58 -07001839 return SVGA3D_R32G8X24_TYPELESS;
Brian Paule0542512015-08-13 11:00:58 -07001840 case SVGA3D_R10G10B10A2_UINT:
1841 case SVGA3D_R10G10B10A2_UNORM:
1842 return SVGA3D_R10G10B10A2_TYPELESS;
1843 case SVGA3D_R8G8B8A8_UNORM:
1844 case SVGA3D_R8G8B8A8_SNORM:
1845 case SVGA3D_R8G8B8A8_UNORM_SRGB:
1846 case SVGA3D_R8G8B8A8_UINT:
1847 case SVGA3D_R8G8B8A8_SINT:
Brian Paulcbe72ae2017-06-26 20:49:35 -06001848 case SVGA3D_R8G8B8A8_TYPELESS:
Brian Paule0542512015-08-13 11:00:58 -07001849 return SVGA3D_R8G8B8A8_TYPELESS;
1850 case SVGA3D_R16G16_UINT:
1851 case SVGA3D_R16G16_SINT:
1852 case SVGA3D_R16G16_UNORM:
1853 case SVGA3D_R16G16_SNORM:
1854 case SVGA3D_R16G16_FLOAT:
1855 return SVGA3D_R16G16_TYPELESS;
1856 case SVGA3D_D32_FLOAT:
1857 case SVGA3D_R32_FLOAT:
1858 case SVGA3D_R32_UINT:
1859 case SVGA3D_R32_SINT:
Brian Paulcbe72ae2017-06-26 20:49:35 -06001860 case SVGA3D_R32_TYPELESS:
Brian Paule0542512015-08-13 11:00:58 -07001861 return SVGA3D_R32_TYPELESS;
1862 case SVGA3D_D24_UNORM_S8_UINT:
Brian Paulcbe72ae2017-06-26 20:49:35 -06001863 case SVGA3D_R24G8_TYPELESS:
Brian Paule0542512015-08-13 11:00:58 -07001864 return SVGA3D_R24G8_TYPELESS;
Brian Paul07823502017-06-28 16:43:52 -06001865 case SVGA3D_X24_G8_UINT:
1866 return SVGA3D_R24_UNORM_X8;
Brian Paule0542512015-08-13 11:00:58 -07001867 case SVGA3D_R8G8_UNORM:
1868 case SVGA3D_R8G8_SNORM:
1869 case SVGA3D_R8G8_UINT:
1870 case SVGA3D_R8G8_SINT:
1871 return SVGA3D_R8G8_TYPELESS;
Brian Paul1a483262015-11-16 10:41:20 -07001872 case SVGA3D_D16_UNORM:
Brian Paule0542512015-08-13 11:00:58 -07001873 case SVGA3D_R16_UNORM:
1874 case SVGA3D_R16_UINT:
1875 case SVGA3D_R16_SNORM:
1876 case SVGA3D_R16_SINT:
1877 case SVGA3D_R16_FLOAT:
Brian Paulcbe72ae2017-06-26 20:49:35 -06001878 case SVGA3D_R16_TYPELESS:
Brian Paule0542512015-08-13 11:00:58 -07001879 return SVGA3D_R16_TYPELESS;
1880 case SVGA3D_R8_UNORM:
1881 case SVGA3D_R8_UINT:
1882 case SVGA3D_R8_SNORM:
1883 case SVGA3D_R8_SINT:
1884 return SVGA3D_R8_TYPELESS;
1885 case SVGA3D_B8G8R8A8_UNORM_SRGB:
1886 case SVGA3D_B8G8R8A8_UNORM:
Brian Paulcbe72ae2017-06-26 20:49:35 -06001887 case SVGA3D_B8G8R8A8_TYPELESS:
Brian Paule0542512015-08-13 11:00:58 -07001888 return SVGA3D_B8G8R8A8_TYPELESS;
1889 case SVGA3D_B8G8R8X8_UNORM_SRGB:
1890 case SVGA3D_B8G8R8X8_UNORM:
Brian Paulcbe72ae2017-06-26 20:49:35 -06001891 case SVGA3D_B8G8R8X8_TYPELESS:
Brian Paule0542512015-08-13 11:00:58 -07001892 return SVGA3D_B8G8R8X8_TYPELESS;
Brian Paul1a483262015-11-16 10:41:20 -07001893 case SVGA3D_BC1_UNORM:
1894 case SVGA3D_BC1_UNORM_SRGB:
Brian Paulcbe72ae2017-06-26 20:49:35 -06001895 case SVGA3D_BC1_TYPELESS:
Brian Paul1a483262015-11-16 10:41:20 -07001896 return SVGA3D_BC1_TYPELESS;
1897 case SVGA3D_BC2_UNORM:
1898 case SVGA3D_BC2_UNORM_SRGB:
Brian Paulcbe72ae2017-06-26 20:49:35 -06001899 case SVGA3D_BC2_TYPELESS:
Brian Paul1a483262015-11-16 10:41:20 -07001900 return SVGA3D_BC2_TYPELESS;
1901 case SVGA3D_BC3_UNORM:
1902 case SVGA3D_BC3_UNORM_SRGB:
Brian Paulcbe72ae2017-06-26 20:49:35 -06001903 case SVGA3D_BC3_TYPELESS:
Brian Paul1a483262015-11-16 10:41:20 -07001904 return SVGA3D_BC3_TYPELESS;
Brian Paule0542512015-08-13 11:00:58 -07001905 case SVGA3D_BC4_UNORM:
1906 case SVGA3D_BC4_SNORM:
1907 return SVGA3D_BC4_TYPELESS;
1908 case SVGA3D_BC5_UNORM:
1909 case SVGA3D_BC5_SNORM:
1910 return SVGA3D_BC5_TYPELESS;
1911
1912 /* Special cases (no corresponding _TYPELESS formats) */
1913 case SVGA3D_A8_UNORM:
Brian Paule0542512015-08-13 11:00:58 -07001914 case SVGA3D_B5G5R5A1_UNORM:
1915 case SVGA3D_B5G6R5_UNORM:
Brian Paule0542512015-08-13 11:00:58 -07001916 case SVGA3D_R11G11B10_FLOAT:
1917 case SVGA3D_R9G9B9E5_SHAREDEXP:
Brian Paule0542512015-08-13 11:00:58 -07001918 return format;
Brian Paul32f669e2011-12-07 17:05:48 -07001919 default:
Brian Paule0542512015-08-13 11:00:58 -07001920 debug_printf("Unexpected format %s in %s\n",
1921 svga_format_name(format), __FUNCTION__);
1922 return format;
Brian Paul32f669e2011-12-07 17:05:48 -07001923 }
1924}
Brian Paul1a90e3e2015-11-16 10:31:46 -07001925
1926
1927/**
1928 * Given a surface format, return the corresponding format to use for
1929 * a texture sampler. In most cases, it's the format unchanged, but there
1930 * are some special cases.
1931 */
1932SVGA3dSurfaceFormat
1933svga_sampler_format(SVGA3dSurfaceFormat format)
1934{
1935 switch (format) {
1936 case SVGA3D_D16_UNORM:
1937 return SVGA3D_R16_UNORM;
1938 case SVGA3D_D24_UNORM_S8_UINT:
Brian Paul07823502017-06-28 16:43:52 -06001939 return SVGA3D_R24_UNORM_X8;
Brian Paul1a90e3e2015-11-16 10:31:46 -07001940 case SVGA3D_D32_FLOAT:
1941 return SVGA3D_R32_FLOAT;
1942 case SVGA3D_D32_FLOAT_S8X24_UINT:
Brian Paul07823502017-06-28 16:43:52 -06001943 return SVGA3D_R32_FLOAT_X8X24;
Brian Paul1a90e3e2015-11-16 10:31:46 -07001944 default:
1945 return format;
1946 }
1947}
Brian Paul46e73552016-06-27 11:17:45 -06001948
1949
1950/**
1951 * Is the given format an uncompressed snorm format?
1952 */
1953bool
1954svga_format_is_uncompressed_snorm(SVGA3dSurfaceFormat format)
1955{
1956 switch (format) {
1957 case SVGA3D_R8G8B8A8_SNORM:
1958 case SVGA3D_R8G8_SNORM:
1959 case SVGA3D_R8_SNORM:
1960 case SVGA3D_R16G16B16A16_SNORM:
1961 case SVGA3D_R16G16_SNORM:
1962 case SVGA3D_R16_SNORM:
1963 return true;
1964 default:
1965 return false;
1966 }
1967}
Charmaine Lee0d221fc2016-10-24 10:50:29 -07001968
1969
1970bool
1971svga_format_is_typeless(SVGA3dSurfaceFormat format)
1972{
1973 switch (format) {
1974 case SVGA3D_R32G32B32A32_TYPELESS:
1975 case SVGA3D_R32G32B32_TYPELESS:
1976 case SVGA3D_R16G16B16A16_TYPELESS:
1977 case SVGA3D_R32G32_TYPELESS:
1978 case SVGA3D_R32G8X24_TYPELESS:
1979 case SVGA3D_R10G10B10A2_TYPELESS:
1980 case SVGA3D_R8G8B8A8_TYPELESS:
1981 case SVGA3D_R16G16_TYPELESS:
1982 case SVGA3D_R32_TYPELESS:
1983 case SVGA3D_R24G8_TYPELESS:
1984 case SVGA3D_R8G8_TYPELESS:
1985 case SVGA3D_R16_TYPELESS:
1986 case SVGA3D_R8_TYPELESS:
1987 case SVGA3D_BC1_TYPELESS:
1988 case SVGA3D_BC2_TYPELESS:
1989 case SVGA3D_BC3_TYPELESS:
1990 case SVGA3D_BC4_TYPELESS:
1991 case SVGA3D_BC5_TYPELESS:
1992 case SVGA3D_B8G8R8A8_TYPELESS:
1993 case SVGA3D_B8G8R8X8_TYPELESS:
1994 return true;
1995 default:
1996 return false;
1997 }
1998}
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001999
2000
2001/**
2002 * \brief Can we import a surface with a given SVGA3D format as a texture?
2003 *
2004 * \param ss[in] pointer to the svga screen.
2005 * \param pformat[in] pipe format of the local texture.
2006 * \param sformat[in] svga3d format of the imported surface.
2007 * \param bind[in] bind flags of the imported texture.
2008 * \param verbose[in] Print out incompatibilities in debug mode.
2009 */
2010bool
2011svga_format_is_shareable(const struct svga_screen *ss,
2012 enum pipe_format pformat,
2013 SVGA3dSurfaceFormat sformat,
2014 unsigned bind,
2015 bool verbose)
2016{
2017 SVGA3dSurfaceFormat default_format =
2018 svga_translate_format(ss, pformat, bind);
2019 int i;
2020
2021 if (default_format == SVGA3D_FORMAT_INVALID)
2022 return false;
2023 if (default_format == sformat)
2024 return true;
2025
2026 for (i = 0; i < ARRAY_SIZE(format_compats); ++i) {
2027 if (format_compats[i].pformat == pformat) {
2028 const SVGA3dSurfaceFormat *compat_format =
2029 format_compats[i].compat_format;
2030 while (*compat_format != 0) {
2031 if (*compat_format == sformat)
2032 return true;
2033 compat_format++;
2034 }
2035 }
2036 }
2037
2038 if (verbose) {
2039 debug_printf("Incompatible imported surface format.\n");
2040 debug_printf("Texture format: \"%s\". Imported format: \"%s\".\n",
2041 svga_format_name(default_format),
2042 svga_format_name(sformat));
2043 }
2044
2045 return false;
2046}
Neha Bhende1b415a52017-04-27 10:37:02 -07002047
2048
2049/**
2050 * Return the sRGB format which corresponds to the given (linear) format.
2051 * If there's no such sRGB format, return the format as-is.
2052 */
2053SVGA3dSurfaceFormat
2054svga_linear_to_srgb(SVGA3dSurfaceFormat format)
2055{
2056 switch (format) {
2057 case SVGA3D_R8G8B8A8_UNORM:
2058 return SVGA3D_R8G8B8A8_UNORM_SRGB;
2059 case SVGA3D_BC1_UNORM:
2060 return SVGA3D_BC1_UNORM_SRGB;
2061 case SVGA3D_BC2_UNORM:
2062 return SVGA3D_BC2_UNORM_SRGB;
2063 case SVGA3D_BC3_UNORM:
2064 return SVGA3D_BC3_UNORM_SRGB;
2065 case SVGA3D_B8G8R8A8_UNORM:
2066 return SVGA3D_B8G8R8A8_UNORM_SRGB;
2067 case SVGA3D_B8G8R8X8_UNORM:
2068 return SVGA3D_B8G8R8X8_UNORM_SRGB;
2069 default:
2070 return format;
2071 }
2072}