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Keith Whitwell287c94e2010-04-10 16:05:54 +01001/**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
Brian Paul3d1fd6d2014-02-08 09:51:15 -080026#include "svga3d_reg.h"
27#include "svga3d_surfacedefs.h"
Keith Whitwell287c94e2010-04-10 16:05:54 +010028
29#include "pipe/p_state.h"
30#include "pipe/p_defines.h"
Keith Whitwell287c94e2010-04-10 16:05:54 +010031#include "os/os_thread.h"
32#include "util/u_format.h"
Brian Paul3d1fd6d2014-02-08 09:51:15 -080033#include "util/u_inlines.h"
Keith Whitwell287c94e2010-04-10 16:05:54 +010034#include "util/u_math.h"
35#include "util/u_memory.h"
Brian Paulac114c62013-04-03 10:23:57 -060036#include "util/u_resource.h"
Charmaine Leef1b33742016-09-06 11:29:41 -070037#include "util/u_upload_mgr.h"
Keith Whitwell287c94e2010-04-10 16:05:54 +010038
Brian Paul3d1fd6d2014-02-08 09:51:15 -080039#include "svga_cmd.h"
José Fonseca974b6412011-04-27 12:02:08 +010040#include "svga_format.h"
Keith Whitwell287c94e2010-04-10 16:05:54 +010041#include "svga_screen.h"
42#include "svga_context.h"
43#include "svga_resource_texture.h"
44#include "svga_resource_buffer.h"
45#include "svga_sampler_view.h"
46#include "svga_winsys.h"
47#include "svga_debug.h"
48
Keith Whitwell287c94e2010-04-10 16:05:54 +010049
Brian Paulbfb6b762014-08-13 16:30:48 -060050static void
José Fonsecab8459092010-05-02 23:54:42 +010051svga_transfer_dma_band(struct svga_context *svga,
52 struct svga_transfer *st,
Keith Whitwell287c94e2010-04-10 16:05:54 +010053 SVGA3dTransferType transfer,
Charmaine Lee0cf0d7c2016-05-31 16:33:52 -070054 unsigned x, unsigned y, unsigned z,
55 unsigned w, unsigned h, unsigned d,
56 unsigned srcx, unsigned srcy, unsigned srcz,
José Fonseca530ad1f2011-03-11 14:49:45 +000057 SVGA3dSurfaceDMAFlags flags)
Keith Whitwell287c94e2010-04-10 16:05:54 +010058{
Brian Paule0542512015-08-13 11:00:58 -070059 struct svga_texture *texture = svga_texture(st->base.resource);
Keith Whitwell287c94e2010-04-10 16:05:54 +010060 SVGA3dCopyBox box;
61 enum pipe_error ret;
Brian Paule0542512015-08-13 11:00:58 -070062
Brian Paul3d1fd6d2014-02-08 09:51:15 -080063 assert(!st->use_direct_map);
64
Charmaine Lee0cf0d7c2016-05-31 16:33:52 -070065 box.x = x;
Keith Whitwell287c94e2010-04-10 16:05:54 +010066 box.y = y;
Charmaine Lee0cf0d7c2016-05-31 16:33:52 -070067 box.z = z;
68 box.w = w;
Keith Whitwell287c94e2010-04-10 16:05:54 +010069 box.h = h;
Charmaine Lee0cf0d7c2016-05-31 16:33:52 -070070 box.d = d;
71 box.srcx = srcx;
Keith Whitwell287c94e2010-04-10 16:05:54 +010072 box.srcy = srcy;
Charmaine Lee0cf0d7c2016-05-31 16:33:52 -070073 box.srcz = srcz;
Keith Whitwell287c94e2010-04-10 16:05:54 +010074
Brian Paule0542512015-08-13 11:00:58 -070075 SVGA_DBG(DEBUG_DMA, "dma %s sid %p, face %u, (%u, %u, %u) - "
76 "(%u, %u, %u), %ubpp\n",
77 transfer == SVGA3D_WRITE_HOST_VRAM ? "to" : "from",
78 texture->handle,
79 st->slice,
Charmaine Lee0cf0d7c2016-05-31 16:33:52 -070080 x,
Brian Paule0542512015-08-13 11:00:58 -070081 y,
Charmaine Lee0cf0d7c2016-05-31 16:33:52 -070082 z,
83 x + w,
Brian Paule0542512015-08-13 11:00:58 -070084 y + h,
Charmaine Lee0cf0d7c2016-05-31 16:33:52 -070085 z + 1,
Brian Paule0542512015-08-13 11:00:58 -070086 util_format_get_blocksize(texture->b.b.format) * 8 /
87 (util_format_get_blockwidth(texture->b.b.format)
88 * util_format_get_blockheight(texture->b.b.format)));
Roland Scheidegger4c700142010-12-02 04:33:43 +010089
José Fonseca530ad1f2011-03-11 14:49:45 +000090 ret = SVGA3D_SurfaceDMA(svga->swc, st, transfer, &box, 1, flags);
Brian Paule0542512015-08-13 11:00:58 -070091 if (ret != PIPE_OK) {
José Fonseca5c296a52011-02-03 15:02:07 +000092 svga_context_flush(svga, NULL);
José Fonseca530ad1f2011-03-11 14:49:45 +000093 ret = SVGA3D_SurfaceDMA(svga->swc, st, transfer, &box, 1, flags);
Keith Whitwell287c94e2010-04-10 16:05:54 +010094 assert(ret == PIPE_OK);
95 }
Keith Whitwell287c94e2010-04-10 16:05:54 +010096}
97
98
Brian Paulbfb6b762014-08-13 16:30:48 -060099static void
José Fonsecab8459092010-05-02 23:54:42 +0100100svga_transfer_dma(struct svga_context *svga,
101 struct svga_transfer *st,
José Fonseca530ad1f2011-03-11 14:49:45 +0000102 SVGA3dTransferType transfer,
103 SVGA3dSurfaceDMAFlags flags)
Keith Whitwell287c94e2010-04-10 16:05:54 +0100104{
Brian Paule0542512015-08-13 11:00:58 -0700105 struct svga_texture *texture = svga_texture(st->base.resource);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100106 struct svga_screen *screen = svga_screen(texture->b.b.screen);
107 struct svga_winsys_screen *sws = screen->sws;
108 struct pipe_fence_handle *fence = NULL;
Roland Scheidegger4c700142010-12-02 04:33:43 +0100109
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800110 assert(!st->use_direct_map);
111
Keith Whitwell287c94e2010-04-10 16:05:54 +0100112 if (transfer == SVGA3D_READ_HOST_VRAM) {
113 SVGA_DBG(DEBUG_PERF, "%s: readback transfer\n", __FUNCTION__);
114 }
115
José Fonseca0ced7892011-02-18 14:33:55 +0000116 /* Ensure any pending operations on host surfaces are queued on the command
117 * buffer first.
118 */
119 svga_surfaces_flush( svga );
Keith Whitwell287c94e2010-04-10 16:05:54 +0100120
Brian Paule0542512015-08-13 11:00:58 -0700121 if (!st->swbuf) {
Keith Whitwell287c94e2010-04-10 16:05:54 +0100122 /* Do the DMA transfer in a single go */
José Fonseca530ad1f2011-03-11 14:49:45 +0000123 svga_transfer_dma_band(svga, st, transfer,
Charmaine Lee0cf0d7c2016-05-31 16:33:52 -0700124 st->base.box.x, st->base.box.y, st->base.box.z,
125 st->base.box.width, st->base.box.height, st->base.box.depth,
126 0, 0, 0,
José Fonseca530ad1f2011-03-11 14:49:45 +0000127 flags);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100128
Brian Paule0542512015-08-13 11:00:58 -0700129 if (transfer == SVGA3D_READ_HOST_VRAM) {
José Fonsecab8459092010-05-02 23:54:42 +0100130 svga_context_flush(svga, &fence);
Sinclair Yeh65175df2017-05-03 11:48:25 -0700131 sws->fence_finish(sws, fence, PIPE_TIMEOUT_INFINITE, 0);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100132 sws->fence_reference(sws, &fence, NULL);
133 }
134 }
135 else {
Brian Paul25cd2c22012-10-16 17:54:37 -0600136 int y, h, srcy;
Brian Paule0542512015-08-13 11:00:58 -0700137 unsigned blockheight =
138 util_format_get_blockheight(st->base.resource->format);
139
Keith Whitwell287c94e2010-04-10 16:05:54 +0100140 h = st->hw_nblocksy * blockheight;
141 srcy = 0;
Brian Paule0542512015-08-13 11:00:58 -0700142
143 for (y = 0; y < st->base.box.height; y += h) {
Keith Whitwell287c94e2010-04-10 16:05:54 +0100144 unsigned offset, length;
145 void *hw, *sw;
146
147 if (y + h > st->base.box.height)
148 h = st->base.box.height - y;
149
150 /* Transfer band must be aligned to pixel block boundaries */
151 assert(y % blockheight == 0);
152 assert(h % blockheight == 0);
Roland Scheidegger4c700142010-12-02 04:33:43 +0100153
Keith Whitwell287c94e2010-04-10 16:05:54 +0100154 offset = y * st->base.stride / blockheight;
155 length = h * st->base.stride / blockheight;
156
Brian Paule0542512015-08-13 11:00:58 -0700157 sw = (uint8_t *) st->swbuf + offset;
Roland Scheidegger4c700142010-12-02 04:33:43 +0100158
José Fonsecab881ea82011-03-21 17:28:21 +0000159 if (transfer == SVGA3D_WRITE_HOST_VRAM) {
160 unsigned usage = PIPE_TRANSFER_WRITE;
161
Keith Whitwell287c94e2010-04-10 16:05:54 +0100162 /* Wait for the previous DMAs to complete */
163 /* TODO: keep one DMA (at half the size) in the background */
José Fonsecab881ea82011-03-21 17:28:21 +0000164 if (y) {
165 svga_context_flush(svga, NULL);
166 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
Keith Whitwell287c94e2010-04-10 16:05:54 +0100167 }
168
José Fonsecab881ea82011-03-21 17:28:21 +0000169 hw = sws->buffer_map(sws, st->hwbuf, usage);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100170 assert(hw);
José Fonsecab881ea82011-03-21 17:28:21 +0000171 if (hw) {
Keith Whitwell287c94e2010-04-10 16:05:54 +0100172 memcpy(hw, sw, length);
173 sws->buffer_unmap(sws, st->hwbuf);
174 }
175 }
Roland Scheidegger4c700142010-12-02 04:33:43 +0100176
Charmaine Lee0cf0d7c2016-05-31 16:33:52 -0700177 svga_transfer_dma_band(svga, st, transfer,
178 st->base.box.x, y, st->base.box.z,
179 st->base.box.width, h, st->base.box.depth,
180 0, srcy, 0, flags);
José Fonseca530ad1f2011-03-11 14:49:45 +0000181
182 /*
183 * Prevent the texture contents to be discarded on the next band
184 * upload.
185 */
José Fonseca530ad1f2011-03-11 14:49:45 +0000186 flags.discard = FALSE;
Roland Scheidegger4c700142010-12-02 04:33:43 +0100187
Brian Paule0542512015-08-13 11:00:58 -0700188 if (transfer == SVGA3D_READ_HOST_VRAM) {
José Fonsecab8459092010-05-02 23:54:42 +0100189 svga_context_flush(svga, &fence);
Sinclair Yeh65175df2017-05-03 11:48:25 -0700190 sws->fence_finish(sws, fence, PIPE_TIMEOUT_INFINITE, 0);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100191
192 hw = sws->buffer_map(sws, st->hwbuf, PIPE_TRANSFER_READ);
193 assert(hw);
Brian Paule0542512015-08-13 11:00:58 -0700194 if (hw) {
Keith Whitwell287c94e2010-04-10 16:05:54 +0100195 memcpy(sw, hw, length);
196 sws->buffer_unmap(sws, st->hwbuf);
197 }
198 }
199 }
200 }
201}
202
203
Charmaine Leea9c4a862016-09-01 17:45:28 -0700204
Brian Paule0542512015-08-13 11:00:58 -0700205static boolean
Keith Whitwell287c94e2010-04-10 16:05:54 +0100206svga_texture_get_handle(struct pipe_screen *screen,
Brian Paule0542512015-08-13 11:00:58 -0700207 struct pipe_resource *texture,
208 struct winsys_handle *whandle)
Keith Whitwell287c94e2010-04-10 16:05:54 +0100209{
210 struct svga_winsys_screen *sws = svga_winsys_screen(texture->screen);
211 unsigned stride;
212
213 assert(svga_texture(texture)->key.cachable == 0);
214 svga_texture(texture)->key.cachable = 0;
Brian Paule0542512015-08-13 11:00:58 -0700215
Keith Whitwell287c94e2010-04-10 16:05:54 +0100216 stride = util_format_get_nblocksx(texture->format, texture->width0) *
217 util_format_get_blocksize(texture->format);
Brian Paule0542512015-08-13 11:00:58 -0700218
219 return sws->surface_get_handle(sws, svga_texture(texture)->handle,
220 stride, whandle);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100221}
222
223
224static void
225svga_texture_destroy(struct pipe_screen *screen,
226 struct pipe_resource *pt)
227{
228 struct svga_screen *ss = svga_screen(screen);
Brian Paul82d6a522013-06-24 14:42:38 -0600229 struct svga_texture *tex = svga_texture(pt);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100230
231 ss->texture_timestamp++;
232
233 svga_sampler_view_reference(&tex->cached_view, NULL);
234
235 /*
236 DBG("%s deleting %p\n", __FUNCTION__, (void *) tex);
237 */
238 SVGA_DBG(DEBUG_DMA, "unref sid %p (texture)\n", tex->handle);
239 svga_screen_surface_destroy(ss, &tex->key, &tex->handle);
240
Charmaine Lee36261122017-04-25 14:32:59 -0600241 /* Destroy the backed surface handle if exists */
242 if (tex->backed_handle)
243 svga_screen_surface_destroy(ss, &tex->backed_key, &tex->backed_handle);
244
Neha Bhende9bc7e312015-10-09 16:10:16 -0600245 ss->hud.total_resource_bytes -= tex->size;
Brian Paulac114c62013-04-03 10:23:57 -0600246
Brian Paule0542512015-08-13 11:00:58 -0700247 FREE(tex->defined);
Brian Paulc1e60a62014-02-08 09:51:14 -0800248 FREE(tex->rendered_to);
Charmaine Leed7a6c1a2016-04-14 17:33:32 -0700249 FREE(tex->dirty);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100250 FREE(tex);
Neha Bhende9bc7e312015-10-09 16:10:16 -0600251
252 assert(ss->hud.num_resources > 0);
253 if (ss->hud.num_resources > 0)
254 ss->hud.num_resources--;
Keith Whitwell287c94e2010-04-10 16:05:54 +0100255}
256
257
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800258/**
Charmaine Lee3dfb4242016-09-30 15:52:14 -0700259 * Determine if the resource was rendered to
260 */
261static inline boolean
262was_tex_rendered_to(struct pipe_resource *resource,
263 const struct pipe_transfer *transfer)
264{
265 unsigned face;
266
267 if (resource->target == PIPE_TEXTURE_CUBE) {
268 assert(transfer->box.depth == 1);
269 face = transfer->box.z;
270 }
271 else {
272 face = 0;
273 }
274
275 return svga_was_texture_rendered_to(svga_texture(resource),
276 face, transfer->level);
277}
278
279
280/**
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800281 * Determine if we need to read back a texture image before mapping it.
282 */
Charmaine Lee3dfb4242016-09-30 15:52:14 -0700283static inline boolean
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800284need_tex_readback(struct pipe_transfer *transfer)
285{
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800286 if (transfer->usage & PIPE_TRANSFER_READ)
287 return TRUE;
288
289 if ((transfer->usage & PIPE_TRANSFER_WRITE) &&
290 ((transfer->usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) == 0)) {
Charmaine Lee3dfb4242016-09-30 15:52:14 -0700291 return was_tex_rendered_to(transfer->resource, transfer);
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800292 }
293
294 return FALSE;
295}
296
297
Brian Paule0542512015-08-13 11:00:58 -0700298static enum pipe_error
299readback_image_vgpu9(struct svga_context *svga,
300 struct svga_winsys_surface *surf,
301 unsigned slice,
302 unsigned level)
303{
304 enum pipe_error ret;
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800305
Brian Paule0542512015-08-13 11:00:58 -0700306 ret = SVGA3D_ReadbackGBImage(svga->swc, surf, slice, level);
307 if (ret != PIPE_OK) {
308 svga_context_flush(svga, NULL);
309 ret = SVGA3D_ReadbackGBImage(svga->swc, surf, slice, level);
310 }
311 return ret;
312}
313
314
315static enum pipe_error
316readback_image_vgpu10(struct svga_context *svga,
317 struct svga_winsys_surface *surf,
318 unsigned slice,
319 unsigned level,
320 unsigned numMipLevels)
321{
322 enum pipe_error ret;
323 unsigned subResource;
324
325 subResource = slice * numMipLevels + level;
326 ret = SVGA3D_vgpu10_ReadbackSubResource(svga->swc, surf, subResource);
327 if (ret != PIPE_OK) {
328 svga_context_flush(svga, NULL);
329 ret = SVGA3D_vgpu10_ReadbackSubResource(svga->swc, surf, subResource);
330 }
331 return ret;
332}
333
334
Charmaine Leea9c4a862016-09-01 17:45:28 -0700335/**
336 * Use DMA for the transfer request
337 */
338static void *
339svga_texture_transfer_map_dma(struct svga_context *svga,
340 struct svga_transfer *st)
341{
342 struct svga_winsys_screen *sws = svga_screen(svga->pipe.screen)->sws;
343 struct pipe_resource *texture = st->base.resource;
344 unsigned nblocksx, nblocksy;
345 unsigned d;
346 unsigned usage = st->base.usage;
347
348 /* we'll put the data into a tightly packed buffer */
349 nblocksx = util_format_get_nblocksx(texture->format, st->base.box.width);
350 nblocksy = util_format_get_nblocksy(texture->format, st->base.box.height);
351 d = st->base.box.depth;
352
353 st->base.stride = nblocksx*util_format_get_blocksize(texture->format);
354 st->base.layer_stride = st->base.stride * nblocksy;
355 st->hw_nblocksy = nblocksy;
356
357 st->hwbuf = svga_winsys_buffer_create(svga, 1, 0,
358 st->hw_nblocksy * st->base.stride * d);
359
360 while (!st->hwbuf && (st->hw_nblocksy /= 2)) {
361 st->hwbuf =
362 svga_winsys_buffer_create(svga, 1, 0,
363 st->hw_nblocksy * st->base.stride * d);
364 }
365
366 if (!st->hwbuf)
367 return NULL;
368
369 if (st->hw_nblocksy < nblocksy) {
370 /* We couldn't allocate a hardware buffer big enough for the transfer,
371 * so allocate regular malloc memory instead
372 */
373 if (0) {
374 debug_printf("%s: failed to allocate %u KB of DMA, "
375 "splitting into %u x %u KB DMA transfers\n",
376 __FUNCTION__,
377 (nblocksy * st->base.stride + 1023) / 1024,
378 (nblocksy + st->hw_nblocksy - 1) / st->hw_nblocksy,
379 (st->hw_nblocksy * st->base.stride + 1023) / 1024);
380 }
381
382 st->swbuf = MALLOC(nblocksy * st->base.stride * d);
383 if (!st->swbuf) {
384 sws->buffer_destroy(sws, st->hwbuf);
385 return NULL;
386 }
387 }
388
389 if (usage & PIPE_TRANSFER_READ) {
390 SVGA3dSurfaceDMAFlags flags;
391 memset(&flags, 0, sizeof flags);
392 svga_transfer_dma(svga, st, SVGA3D_READ_HOST_VRAM, flags);
393 }
394
395 if (st->swbuf) {
396 return st->swbuf;
397 }
398 else {
399 return sws->buffer_map(sws, st->hwbuf, usage);
400 }
401}
402
403
404/**
405 * Use direct map for the transfer request
406 */
407static void *
408svga_texture_transfer_map_direct(struct svga_context *svga,
409 struct svga_transfer *st)
410{
411 struct svga_winsys_screen *sws = svga_screen(svga->pipe.screen)->sws;
412 struct pipe_transfer *transfer = &st->base;
413 struct pipe_resource *texture = transfer->resource;
414 struct svga_texture *tex = svga_texture(texture);
415 struct svga_winsys_surface *surf = tex->handle;
416 unsigned level = st->base.level;
Neha Bhende31fe1d12016-10-27 12:35:03 -0700417 unsigned w, h, nblocksx, nblocksy, i;
Charmaine Leea9c4a862016-09-01 17:45:28 -0700418 unsigned usage = st->base.usage;
419
Charmaine Leea9c4a862016-09-01 17:45:28 -0700420 if (need_tex_readback(transfer)) {
421 enum pipe_error ret;
422
423 svga_surfaces_flush(svga);
424
Neha Bhende31fe1d12016-10-27 12:35:03 -0700425 for (i = 0; i < st->base.box.depth; i++) {
426 if (svga_have_vgpu10(svga)) {
427 ret = readback_image_vgpu10(svga, surf, st->slice + i, level,
428 tex->b.b.last_level + 1);
429 } else {
430 ret = readback_image_vgpu9(svga, surf, st->slice + i, level);
431 }
Charmaine Leea9c4a862016-09-01 17:45:28 -0700432 }
Charmaine Leea9c4a862016-09-01 17:45:28 -0700433 svga->hud.num_readbacks++;
434 SVGA_STATS_COUNT_INC(sws, SVGA_STATS_COUNT_TEXREADBACK);
435
436 assert(ret == PIPE_OK);
437 (void) ret;
438
439 svga_context_flush(svga, NULL);
Charmaine Leea9c4a862016-09-01 17:45:28 -0700440 /*
441 * Note: if PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE were specified
442 * we could potentially clear the flag for all faces/layers/mips.
443 */
444 svga_clear_texture_rendered_to(tex, st->slice, level);
445 }
446 else {
447 assert(usage & PIPE_TRANSFER_WRITE);
448 if ((usage & PIPE_TRANSFER_UNSYNCHRONIZED) == 0) {
449 if (svga_is_texture_dirty(tex, st->slice, level)) {
450 /*
451 * do a surface flush if the subresource has been modified
452 * in this command buffer.
453 */
454 svga_surfaces_flush(svga);
455 if (!sws->surface_is_flushed(sws, surf)) {
456 svga->hud.surface_write_flushes++;
457 SVGA_STATS_COUNT_INC(sws, SVGA_STATS_COUNT_SURFACEWRITEFLUSH);
458 svga_context_flush(svga, NULL);
459 }
460 }
461 }
462 }
463
Charmaine Lee3dfb4242016-09-30 15:52:14 -0700464 /* we'll directly access the guest-backed surface */
465 w = u_minify(texture->width0, level);
466 h = u_minify(texture->height0, level);
467 nblocksx = util_format_get_nblocksx(texture->format, w);
468 nblocksy = util_format_get_nblocksy(texture->format, h);
469 st->hw_nblocksy = nblocksy;
470 st->base.stride = nblocksx*util_format_get_blocksize(texture->format);
471 st->base.layer_stride = st->base.stride * nblocksy;
472
Charmaine Leea9c4a862016-09-01 17:45:28 -0700473 /*
474 * Begin mapping code
475 */
476 {
477 SVGA3dSize baseLevelSize;
478 uint8_t *map;
479 boolean retry;
480 unsigned offset, mip_width, mip_height;
481
482 map = svga->swc->surface_map(svga->swc, surf, usage, &retry);
483 if (map == NULL && retry) {
484 /*
485 * At this point, the svga_surfaces_flush() should already have
486 * called in svga_texture_get_transfer().
487 */
488 svga->hud.surface_write_flushes++;
489 svga_context_flush(svga, NULL);
490 map = svga->swc->surface_map(svga->swc, surf, usage, &retry);
491 }
492
493 /*
494 * Make sure we return NULL if the map fails
495 */
496 if (!map) {
497 return NULL;
498 }
499
500 /**
501 * Compute the offset to the specific texture slice in the buffer.
502 */
503 baseLevelSize.width = tex->b.b.width0;
504 baseLevelSize.height = tex->b.b.height0;
505 baseLevelSize.depth = tex->b.b.depth0;
506
507 if ((tex->b.b.target == PIPE_TEXTURE_1D_ARRAY) ||
508 (tex->b.b.target == PIPE_TEXTURE_2D_ARRAY)) {
509 st->base.layer_stride =
510 svga3dsurface_get_image_offset(tex->key.format, baseLevelSize,
511 tex->b.b.last_level + 1, 1, 0);
512 }
513
514 offset = svga3dsurface_get_image_offset(tex->key.format, baseLevelSize,
515 tex->b.b.last_level + 1, /* numMips */
516 st->slice, level);
517 if (level > 0) {
518 assert(offset > 0);
519 }
520
521 mip_width = u_minify(tex->b.b.width0, level);
522 mip_height = u_minify(tex->b.b.height0, level);
523
524 offset += svga3dsurface_get_pixel_offset(tex->key.format,
525 mip_width, mip_height,
526 st->base.box.x,
527 st->base.box.y,
528 st->base.box.z);
Charmaine Leea9c4a862016-09-01 17:45:28 -0700529 return (void *) (map + offset);
530 }
531}
532
533
534/**
535 * Request a transfer map to the texture resource
536 */
Marek Olšák369e4682012-10-08 04:06:42 +0200537static void *
538svga_texture_transfer_map(struct pipe_context *pipe,
Roland Scheidegger4c700142010-12-02 04:33:43 +0100539 struct pipe_resource *texture,
540 unsigned level,
541 unsigned usage,
Marek Olšák369e4682012-10-08 04:06:42 +0200542 const struct pipe_box *box,
543 struct pipe_transfer **ptransfer)
Keith Whitwell287c94e2010-04-10 16:05:54 +0100544{
José Fonsecab8459092010-05-02 23:54:42 +0100545 struct svga_context *svga = svga_context(pipe);
Charmaine Leea9c4a862016-09-01 17:45:28 -0700546 struct svga_winsys_screen *sws = svga_screen(pipe->screen)->sws;
Brian Paule0542512015-08-13 11:00:58 -0700547 struct svga_texture *tex = svga_texture(texture);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100548 struct svga_transfer *st;
Charmaine Leef1b33742016-09-06 11:29:41 -0700549 struct svga_winsys_surface *surf = tex->handle;
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800550 boolean use_direct_map = svga_have_gb_objects(svga) &&
Charmaine Leea9c4a862016-09-01 17:45:28 -0700551 !svga_have_gb_dma(svga);
Charmaine Leef1b33742016-09-06 11:29:41 -0700552 void *map = NULL;
Brian Paulf9341172016-08-02 14:27:33 -0600553 int64_t begin = svga_get_time(svga);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100554
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600555 SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_TEXTRANSFERMAP);
556
Charmaine Leef1b33742016-09-06 11:29:41 -0700557 if (!surf)
558 goto done;
559
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800560 /* We can't map texture storage directly unless we have GB objects */
561 if (usage & PIPE_TRANSFER_MAP_DIRECTLY) {
562 if (svga_have_gb_objects(svga))
563 use_direct_map = TRUE;
564 else
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600565 goto done;
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800566 }
Keith Whitwell287c94e2010-04-10 16:05:54 +0100567
568 st = CALLOC_STRUCT(svga_transfer);
569 if (!st)
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600570 goto done;
Roland Scheidegger4c700142010-12-02 04:33:43 +0100571
Charmaine Lee6397c122016-06-23 09:21:11 -0700572 st->base.level = level;
573 st->base.usage = usage;
574 st->base.box = *box;
575
576 switch (tex->b.b.target) {
577 case PIPE_TEXTURE_CUBE:
578 st->slice = st->base.box.z;
579 st->base.box.z = 0; /* so we don't apply double offsets below */
580 break;
581 case PIPE_TEXTURE_2D_ARRAY:
582 case PIPE_TEXTURE_1D_ARRAY:
583 st->slice = st->base.box.z;
584 st->base.box.z = 0; /* so we don't apply double offsets below */
585
586 /* Force direct map for transfering multiple slices */
587 if (st->base.box.depth > 1)
588 use_direct_map = svga_have_gb_objects(svga);
589
590 break;
591 default:
592 st->slice = 0;
593 break;
594 }
595
Charmaine Leea9c4a862016-09-01 17:45:28 -0700596 st->use_direct_map = use_direct_map;
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800597 pipe_resource_reference(&st->base.resource, texture);
Brian Paule0542512015-08-13 11:00:58 -0700598
Charmaine Leef1b33742016-09-06 11:29:41 -0700599 /* If this is the first time mapping to the surface in this
600 * command buffer, clear the dirty masks of this surface.
601 */
602 if (sws->surface_is_flushed(sws, surf)) {
603 svga_clear_texture_dirty(tex);
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800604 }
Neha Bhende9bc7e312015-10-09 16:10:16 -0600605
Charmaine Leef1b33742016-09-06 11:29:41 -0700606 if (!use_direct_map) {
607 /* upload to the DMA buffer */
608 map = svga_texture_transfer_map_dma(svga, st);
609 }
610 else {
Charmaine Lee59f14562016-09-30 16:41:12 -0700611 boolean can_use_upload = tex->can_use_upload &&
612 !(st->base.usage & PIPE_TRANSFER_READ);
Charmaine Lee3dfb4242016-09-30 15:52:14 -0700613 boolean was_rendered_to = was_tex_rendered_to(texture, &st->base);
614
615 /* If the texture was already rendered to and upload buffer
616 * is supported, then we will use upload buffer to
617 * avoid the need to read back the texture content; otherwise,
618 * we'll first try to map directly to the GB surface, if it is blocked,
619 * then we'll try the upload buffer.
620 */
Charmaine Lee59f14562016-09-30 16:41:12 -0700621 if (was_rendered_to && can_use_upload) {
Charmaine Leef1b33742016-09-06 11:29:41 -0700622 map = svga_texture_transfer_map_upload(svga, st);
623 }
Charmaine Lee3dfb4242016-09-30 15:52:14 -0700624 else {
625 unsigned orig_usage = st->base.usage;
Charmaine Leef1b33742016-09-06 11:29:41 -0700626
Charmaine Lee59f14562016-09-30 16:41:12 -0700627 /* First try directly map to the GB surface */
628 if (can_use_upload)
Charmaine Lee3dfb4242016-09-30 15:52:14 -0700629 st->base.usage |= PIPE_TRANSFER_DONTBLOCK;
630 map = svga_texture_transfer_map_direct(svga, st);
631 st->base.usage = orig_usage;
632
Charmaine Lee59f14562016-09-30 16:41:12 -0700633 if (!map && can_use_upload) {
Charmaine Lee3dfb4242016-09-30 15:52:14 -0700634 /* if direct map with DONTBLOCK fails, then try upload to the
635 * texture upload buffer.
636 */
637 map = svga_texture_transfer_map_upload(svga, st);
638 }
639 }
640
Charmaine Lee59f14562016-09-30 16:41:12 -0700641 /* If upload fails, then try direct map again without forcing it
642 * to DONTBLOCK.
643 */
Charmaine Leef1b33742016-09-06 11:29:41 -0700644 if (!map) {
Charmaine Leef1b33742016-09-06 11:29:41 -0700645 map = svga_texture_transfer_map_direct(svga, st);
646 }
647 }
648
649 if (!map) {
Charmaine Leea9c4a862016-09-01 17:45:28 -0700650 FREE(st);
651 }
652 else {
653 *ptransfer = &st->base;
654 svga->hud.num_textures_mapped++;
655 if (usage & PIPE_TRANSFER_WRITE) {
656 /* record texture upload for HUD */
657 svga->hud.num_bytes_uploaded +=
658 st->base.layer_stride * st->base.box.depth;
Charmaine Leef1b33742016-09-06 11:29:41 -0700659
660 /* mark this texture level as dirty */
661 svga_set_texture_dirty(tex, st->slice, level);
Charmaine Leea9c4a862016-09-01 17:45:28 -0700662 }
663 }
Neha Bhende9bc7e312015-10-09 16:10:16 -0600664
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600665done:
Charmaine Leea9c4a862016-09-01 17:45:28 -0700666 svga->hud.map_buffer_time += (svga_get_time(svga) - begin);
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600667 SVGA_STATS_TIME_POP(sws);
Charmaine Leef1b33742016-09-06 11:29:41 -0700668 (void) sws;
669
670 return map;
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800671}
672
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800673/**
674 * Unmap a GB texture surface.
675 */
676static void
677svga_texture_surface_unmap(struct svga_context *svga,
678 struct pipe_transfer *transfer)
679{
680 struct svga_winsys_surface *surf = svga_texture(transfer->resource)->handle;
681 struct svga_winsys_context *swc = svga->swc;
682 boolean rebind;
683
684 assert(surf);
685
686 swc->surface_unmap(swc, surf, &rebind);
687 if (rebind) {
688 enum pipe_error ret;
689 ret = SVGA3D_BindGBSurface(swc, surf);
690 if (ret != PIPE_OK) {
691 /* flush and retry */
692 svga_context_flush(svga, NULL);
693 ret = SVGA3D_BindGBSurface(swc, surf);
694 assert(ret == PIPE_OK);
695 }
696 }
Keith Whitwell287c94e2010-04-10 16:05:54 +0100697}
698
699
Brian Paule0542512015-08-13 11:00:58 -0700700static enum pipe_error
701update_image_vgpu9(struct svga_context *svga,
702 struct svga_winsys_surface *surf,
703 const SVGA3dBox *box,
704 unsigned slice,
705 unsigned level)
706{
707 enum pipe_error ret;
708
709 ret = SVGA3D_UpdateGBImage(svga->swc, surf, box, slice, level);
710 if (ret != PIPE_OK) {
711 svga_context_flush(svga, NULL);
712 ret = SVGA3D_UpdateGBImage(svga->swc, surf, box, slice, level);
713 }
714 return ret;
715}
716
717
718static enum pipe_error
719update_image_vgpu10(struct svga_context *svga,
720 struct svga_winsys_surface *surf,
721 const SVGA3dBox *box,
722 unsigned slice,
723 unsigned level,
724 unsigned numMipLevels)
725{
726 enum pipe_error ret;
727 unsigned subResource;
728
729 subResource = slice * numMipLevels + level;
730 ret = SVGA3D_vgpu10_UpdateSubResource(svga->swc, surf, box, subResource);
731 if (ret != PIPE_OK) {
732 svga_context_flush(svga, NULL);
733 ret = SVGA3D_vgpu10_UpdateSubResource(svga->swc, surf, box, subResource);
734 }
735 return ret;
736}
737
738
Charmaine Leea9c4a862016-09-01 17:45:28 -0700739/**
740 * unmap DMA transfer request
741 */
Keith Whitwell287c94e2010-04-10 16:05:54 +0100742static void
Charmaine Leea9c4a862016-09-01 17:45:28 -0700743svga_texture_transfer_unmap_dma(struct svga_context *svga,
744 struct svga_transfer *st)
Keith Whitwell287c94e2010-04-10 16:05:54 +0100745{
Charmaine Leea9c4a862016-09-01 17:45:28 -0700746 struct svga_winsys_screen *sws = svga_screen(svga->pipe.screen)->sws;
Marek Olšák369e4682012-10-08 04:06:42 +0200747
Charmaine Leea9c4a862016-09-01 17:45:28 -0700748 if (st->hwbuf)
749 sws->buffer_unmap(sws, st->hwbuf);
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600750
Charmaine Leea9c4a862016-09-01 17:45:28 -0700751 if (st->base.usage & PIPE_TRANSFER_WRITE) {
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800752 /* Use DMA to transfer texture data */
José Fonseca530ad1f2011-03-11 14:49:45 +0000753 SVGA3dSurfaceDMAFlags flags;
754
755 memset(&flags, 0, sizeof flags);
Charmaine Leea9c4a862016-09-01 17:45:28 -0700756 if (st->base.usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
José Fonseca530ad1f2011-03-11 14:49:45 +0000757 flags.discard = TRUE;
758 }
Charmaine Leea9c4a862016-09-01 17:45:28 -0700759 if (st->base.usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
José Fonseca530ad1f2011-03-11 14:49:45 +0000760 flags.unsynchronized = TRUE;
761 }
762
763 svga_transfer_dma(svga, st, SVGA3D_WRITE_HOST_VRAM, flags);
Charmaine Leea9c4a862016-09-01 17:45:28 -0700764 }
765
766 FREE(st->swbuf);
767 sws->buffer_destroy(sws, st->hwbuf);
768}
769
770
771/**
772 * unmap direct map transfer request
773 */
774static void
775svga_texture_transfer_unmap_direct(struct svga_context *svga,
776 struct svga_transfer *st)
777{
778 struct pipe_transfer *transfer = &st->base;
779 struct svga_texture *tex = svga_texture(transfer->resource);
780
781 svga_texture_surface_unmap(svga, transfer);
782
Charmaine Leef1b33742016-09-06 11:29:41 -0700783 /* Now send an update command to update the content in the backend. */
Charmaine Leea9c4a862016-09-01 17:45:28 -0700784 if (st->base.usage & PIPE_TRANSFER_WRITE) {
Brian Paulc6e89fa2016-08-25 16:15:23 -0600785 struct svga_winsys_surface *surf = tex->handle;
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800786 SVGA3dBox box;
787 enum pipe_error ret;
Charmaine Lee2aa9ff02016-06-21 10:12:22 -0700788 unsigned nlayers = 1;
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800789
790 assert(svga_have_gb_objects(svga));
791
792 /* update the effected region */
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800793 box.x = transfer->box.x;
794 box.y = transfer->box.y;
Charmaine Lee2aa9ff02016-06-21 10:12:22 -0700795 box.w = transfer->box.width;
796 box.h = transfer->box.height;
797 box.d = transfer->box.depth;
798
Brian Paule0542512015-08-13 11:00:58 -0700799 switch (tex->b.b.target) {
800 case PIPE_TEXTURE_CUBE:
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800801 box.z = 0;
Brian Paule0542512015-08-13 11:00:58 -0700802 break;
Charmaine Lee2aa9ff02016-06-21 10:12:22 -0700803 case PIPE_TEXTURE_2D_ARRAY:
804 nlayers = box.d;
805 box.z = 0;
806 box.d = 1;
807 break;
Brian Paule0542512015-08-13 11:00:58 -0700808 case PIPE_TEXTURE_1D_ARRAY:
Charmaine Lee2aa9ff02016-06-21 10:12:22 -0700809 nlayers = box.d;
Brian Paule0542512015-08-13 11:00:58 -0700810 box.y = box.z = 0;
Charmaine Lee2aa9ff02016-06-21 10:12:22 -0700811 box.d = 1;
Brian Paule0542512015-08-13 11:00:58 -0700812 break;
813 default:
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800814 box.z = transfer->box.z;
Brian Paule0542512015-08-13 11:00:58 -0700815 break;
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800816 }
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800817
818 if (0)
819 debug_printf("%s %d, %d, %d %d x %d x %d\n",
820 __FUNCTION__,
821 box.x, box.y, box.z,
822 box.w, box.h, box.d);
823
Brian Paule0542512015-08-13 11:00:58 -0700824 if (svga_have_vgpu10(svga)) {
Charmaine Lee2aa9ff02016-06-21 10:12:22 -0700825 unsigned i;
826 for (i = 0; i < nlayers; i++) {
827 ret = update_image_vgpu10(svga, surf, &box,
828 st->slice + i, transfer->level,
829 tex->b.b.last_level + 1);
830 assert(ret == PIPE_OK);
831 }
Brian Paule0542512015-08-13 11:00:58 -0700832 } else {
Charmaine Lee2aa9ff02016-06-21 10:12:22 -0700833 assert(nlayers == 1);
Brian Paule0542512015-08-13 11:00:58 -0700834 ret = update_image_vgpu9(svga, surf, &box, st->slice, transfer->level);
Charmaine Lee2aa9ff02016-06-21 10:12:22 -0700835 assert(ret == PIPE_OK);
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800836 }
Charmaine Leef1b33742016-09-06 11:29:41 -0700837 (void) ret;
Charmaine Leea9c4a862016-09-01 17:45:28 -0700838 }
839}
Brian Paule0542512015-08-13 11:00:58 -0700840
Charmaine Leea9c4a862016-09-01 17:45:28 -0700841static void
842svga_texture_transfer_unmap(struct pipe_context *pipe,
843 struct pipe_transfer *transfer)
844{
845 struct svga_context *svga = svga_context(pipe);
846 struct svga_screen *ss = svga_screen(pipe->screen);
847 struct svga_winsys_screen *sws = ss->sws;
848 struct svga_transfer *st = svga_transfer(transfer);
849 struct svga_texture *tex = svga_texture(transfer->resource);
850
851 SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_TEXTRANSFERUNMAP);
852
Charmaine Leef1b33742016-09-06 11:29:41 -0700853 if (!st->use_direct_map) {
854 svga_texture_transfer_unmap_dma(svga, st);
855 }
856 else if (st->upload.buf) {
857 svga_texture_transfer_unmap_upload(svga, st);
Charmaine Leea9c4a862016-09-01 17:45:28 -0700858 }
859 else {
Charmaine Leef1b33742016-09-06 11:29:41 -0700860 svga_texture_transfer_unmap_direct(svga, st);
Charmaine Leea9c4a862016-09-01 17:45:28 -0700861 }
862
863 if (st->base.usage & PIPE_TRANSFER_WRITE) {
Charmaine Lee0a1d91e2016-03-11 14:33:39 -0800864 svga->hud.num_resource_updates++;
865
Charmaine Leef1b33742016-09-06 11:29:41 -0700866 /* Mark the texture level as dirty */
Charmaine Leea9c4a862016-09-01 17:45:28 -0700867 ss->texture_timestamp++;
868 svga_age_texture_view(tex, transfer->level);
869 if (transfer->resource->target == PIPE_TEXTURE_CUBE)
870 svga_define_texture_level(tex, st->slice, transfer->level);
871 else
872 svga_define_texture_level(tex, 0, transfer->level);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100873 }
874
Brian Paul3d1fd6d2014-02-08 09:51:15 -0800875 pipe_resource_reference(&st->base.resource, NULL);
Keith Whitwell287c94e2010-04-10 16:05:54 +0100876 FREE(st);
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600877 SVGA_STATS_TIME_POP(sws);
Charmaine Leef1b33742016-09-06 11:29:41 -0700878 (void) sws;
Keith Whitwell287c94e2010-04-10 16:05:54 +0100879}
880
881
Brian Paule0542512015-08-13 11:00:58 -0700882/**
883 * Does format store depth values?
884 */
885static inline boolean
886format_has_depth(enum pipe_format format)
887{
888 const struct util_format_description *desc = util_format_description(format);
889 return util_format_has_depth(desc);
890}
891
892
893struct u_resource_vtbl svga_texture_vtbl =
Keith Whitwell287c94e2010-04-10 16:05:54 +0100894{
895 svga_texture_get_handle, /* get_handle */
896 svga_texture_destroy, /* resource_destroy */
Keith Whitwell287c94e2010-04-10 16:05:54 +0100897 svga_texture_transfer_map, /* transfer_map */
898 u_default_transfer_flush_region, /* transfer_flush_region */
899 svga_texture_transfer_unmap, /* transfer_unmap */
Keith Whitwell287c94e2010-04-10 16:05:54 +0100900};
901
902
Keith Whitwell287c94e2010-04-10 16:05:54 +0100903struct pipe_resource *
904svga_texture_create(struct pipe_screen *screen,
905 const struct pipe_resource *template)
906{
907 struct svga_screen *svgascreen = svga_screen(screen);
Brian Paule0542512015-08-13 11:00:58 -0700908 struct svga_texture *tex;
909 unsigned bindings = template->bind;
Roland Scheidegger4c700142010-12-02 04:33:43 +0100910
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600911 SVGA_STATS_TIME_PUSH(svgascreen->sws,
912 SVGA_STATS_TIME_CREATETEXTURE);
913
Brian Paule0542512015-08-13 11:00:58 -0700914 assert(template->last_level < SVGA_MAX_TEXTURE_LEVELS);
915 if (template->last_level >= SVGA_MAX_TEXTURE_LEVELS) {
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600916 goto fail_notex;
Brian Paule0542512015-08-13 11:00:58 -0700917 }
918
Brian Paulf215f422017-06-27 09:51:25 -0600919 /* Verify the number of mipmap levels isn't impossibly large. For example,
920 * if the base 2D image is 16x16, we can't have 8 mipmap levels.
921 * The state tracker should never ask us to create a resource with invalid
922 * parameters.
923 */
924 {
925 unsigned max_dim = template->width0;
926
927 switch (template->target) {
928 case PIPE_TEXTURE_1D:
929 case PIPE_TEXTURE_1D_ARRAY:
930 // nothing
931 break;
932 case PIPE_TEXTURE_2D:
933 case PIPE_TEXTURE_CUBE:
934 case PIPE_TEXTURE_CUBE_ARRAY:
935 case PIPE_TEXTURE_2D_ARRAY:
936 max_dim = MAX2(max_dim, template->height0);
937 break;
938 case PIPE_TEXTURE_3D:
939 max_dim = MAX3(max_dim, template->height0, template->depth0);
940 break;
941 case PIPE_TEXTURE_RECT:
942 case PIPE_BUFFER:
943 assert(template->last_level == 0);
944 /* the assertion below should always pass */
945 break;
946 default:
947 debug_printf("Unexpected texture target type\n");
948 }
949 assert(1 << template->last_level <= max_dim);
950 }
951
Brian Paule0542512015-08-13 11:00:58 -0700952 tex = CALLOC_STRUCT(svga_texture);
953 if (!tex) {
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600954 goto fail_notex;
Brian Paule0542512015-08-13 11:00:58 -0700955 }
956
957 tex->defined = CALLOC(template->depth0 * template->array_size,
958 sizeof(tex->defined[0]));
959 if (!tex->defined) {
960 FREE(tex);
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -0600961 goto fail_notex;
Brian Paule0542512015-08-13 11:00:58 -0700962 }
963
964 tex->rendered_to = CALLOC(template->depth0 * template->array_size,
965 sizeof(tex->rendered_to[0]));
966 if (!tex->rendered_to) {
Charmaine Leed7a6c1a2016-04-14 17:33:32 -0700967 goto fail;
968 }
969
970 tex->dirty = CALLOC(template->depth0 * template->array_size,
971 sizeof(tex->dirty[0]));
972 if (!tex->dirty) {
973 goto fail;
Brian Paule0542512015-08-13 11:00:58 -0700974 }
Keith Whitwell287c94e2010-04-10 16:05:54 +0100975
976 tex->b.b = *template;
977 tex->b.vtbl = &svga_texture_vtbl;
978 pipe_reference_init(&tex->b.b.reference, 1);
979 tex->b.b.screen = screen;
980
Keith Whitwell287c94e2010-04-10 16:05:54 +0100981 tex->key.flags = 0;
982 tex->key.size.width = template->width0;
983 tex->key.size.height = template->height0;
984 tex->key.size.depth = template->depth0;
Brian Paule0542512015-08-13 11:00:58 -0700985 tex->key.arraySize = 1;
986 tex->key.numFaces = 1;
Charmaine Lee2a4b0192016-09-12 14:21:40 -0700987
Brian Paul3e39abf2017-08-03 10:54:18 -0600988 /* nr_samples=1 must be treated as a non-multisample texture */
989 if (tex->b.b.nr_samples == 1) {
990 tex->b.b.nr_samples = 0;
991 }
992 else if (tex->b.b.nr_samples > 1) {
Brian Paule0542512015-08-13 11:00:58 -0700993 tex->key.flags |= SVGA3D_SURFACE_MASKABLE_ANTIALIAS;
994 }
995
Brian Paul3e39abf2017-08-03 10:54:18 -0600996 tex->key.sampleCount = tex->b.b.nr_samples;
997
Brian Paule0542512015-08-13 11:00:58 -0700998 if (svgascreen->sws->have_vgpu10) {
999 switch (template->target) {
1000 case PIPE_TEXTURE_1D:
1001 tex->key.flags |= SVGA3D_SURFACE_1D;
1002 break;
1003 case PIPE_TEXTURE_1D_ARRAY:
1004 tex->key.flags |= SVGA3D_SURFACE_1D;
1005 /* fall-through */
1006 case PIPE_TEXTURE_2D_ARRAY:
1007 tex->key.flags |= SVGA3D_SURFACE_ARRAY;
1008 tex->key.arraySize = template->array_size;
1009 break;
1010 case PIPE_TEXTURE_3D:
1011 tex->key.flags |= SVGA3D_SURFACE_VOLUME;
1012 break;
1013 case PIPE_TEXTURE_CUBE:
1014 tex->key.flags |= (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_ARRAY);
1015 tex->key.numFaces = 6;
1016 break;
1017 default:
1018 break;
1019 }
Keith Whitwell287c94e2010-04-10 16:05:54 +01001020 }
1021 else {
Brian Paule0542512015-08-13 11:00:58 -07001022 switch (template->target) {
1023 case PIPE_TEXTURE_3D:
1024 tex->key.flags |= SVGA3D_SURFACE_VOLUME;
1025 break;
1026 case PIPE_TEXTURE_CUBE:
1027 tex->key.flags |= SVGA3D_SURFACE_CUBEMAP;
1028 tex->key.numFaces = 6;
1029 break;
1030 default:
1031 break;
1032 }
Brian Paul9eff5e92013-01-30 17:43:57 -07001033 }
1034
Brian Paul09d0fa52011-12-07 17:11:00 -07001035 tex->key.cachable = 1;
Keith Whitwell287c94e2010-04-10 16:05:54 +01001036
Brian Paul05abaa62016-05-02 10:29:52 -06001037 if ((bindings & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) &&
1038 !(bindings & PIPE_BIND_SAMPLER_VIEW)) {
1039 /* Also check if the format can be sampled from */
1040 if (screen->is_format_supported(screen, template->format,
1041 template->target,
1042 template->nr_samples,
1043 PIPE_BIND_SAMPLER_VIEW)) {
1044 bindings |= PIPE_BIND_SAMPLER_VIEW;
1045 }
1046 }
1047
Brian Paule0542512015-08-13 11:00:58 -07001048 if (bindings & PIPE_BIND_SAMPLER_VIEW) {
Keith Whitwell287c94e2010-04-10 16:05:54 +01001049 tex->key.flags |= SVGA3D_SURFACE_HINT_TEXTURE;
Brian Paule0542512015-08-13 11:00:58 -07001050 tex->key.flags |= SVGA3D_SURFACE_BIND_SHADER_RESOURCE;
Keith Whitwell287c94e2010-04-10 16:05:54 +01001051
Brian Paule0542512015-08-13 11:00:58 -07001052 if (!(bindings & PIPE_BIND_RENDER_TARGET)) {
Brian Paulc0d7b602016-09-20 17:22:42 -06001053 /* Also check if the format is color renderable */
Brian Paule0542512015-08-13 11:00:58 -07001054 if (screen->is_format_supported(screen, template->format,
1055 template->target,
1056 template->nr_samples,
1057 PIPE_BIND_RENDER_TARGET)) {
1058 bindings |= PIPE_BIND_RENDER_TARGET;
1059 }
1060 }
Brian Paulc0d7b602016-09-20 17:22:42 -06001061
1062 if (!(bindings & PIPE_BIND_DEPTH_STENCIL)) {
1063 /* Also check if the format is depth/stencil renderable */
1064 if (screen->is_format_supported(screen, template->format,
1065 template->target,
1066 template->nr_samples,
1067 PIPE_BIND_DEPTH_STENCIL)) {
1068 bindings |= PIPE_BIND_DEPTH_STENCIL;
1069 }
1070 }
Brian Paule0542512015-08-13 11:00:58 -07001071 }
1072
1073 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
Keith Whitwell287c94e2010-04-10 16:05:54 +01001074 tex->key.cachable = 0;
1075 }
1076
Brian Paule0542512015-08-13 11:00:58 -07001077 if (bindings & PIPE_BIND_SHARED) {
Keith Whitwell287c94e2010-04-10 16:05:54 +01001078 tex->key.cachable = 0;
1079 }
1080
Brian Paule0542512015-08-13 11:00:58 -07001081 if (bindings & (PIPE_BIND_SCANOUT | PIPE_BIND_CURSOR)) {
1082 tex->key.scanout = 1;
Keith Whitwell287c94e2010-04-10 16:05:54 +01001083 tex->key.cachable = 0;
1084 }
Jakob Bornecrantz292c21b2011-11-01 05:10:17 +01001085
Brian Paule0542512015-08-13 11:00:58 -07001086 /*
Thomas Hellstrom4dac89d2012-01-10 14:37:33 +01001087 * Note: Previously we never passed the
1088 * SVGA3D_SURFACE_HINT_RENDERTARGET hint. Mesa cannot
Keith Whitwell287c94e2010-04-10 16:05:54 +01001089 * know beforehand whether a texture will be used as a rendertarget or not
1090 * and it always requests PIPE_BIND_RENDER_TARGET, therefore
1091 * passing the SVGA3D_SURFACE_HINT_RENDERTARGET here defeats its purpose.
Thomas Hellstrom4dac89d2012-01-10 14:37:33 +01001092 *
1093 * However, this was changed since other state trackers
1094 * (XA for example) uses it accurately and certain device versions
1095 * relies on it in certain situations to render correctly.
Keith Whitwell287c94e2010-04-10 16:05:54 +01001096 */
Brian Paule0542512015-08-13 11:00:58 -07001097 if ((bindings & PIPE_BIND_RENDER_TARGET) &&
1098 !util_format_is_s3tc(template->format)) {
Keith Whitwell287c94e2010-04-10 16:05:54 +01001099 tex->key.flags |= SVGA3D_SURFACE_HINT_RENDERTARGET;
Brian Paule0542512015-08-13 11:00:58 -07001100 tex->key.flags |= SVGA3D_SURFACE_BIND_RENDER_TARGET;
1101 }
1102
1103 if (bindings & PIPE_BIND_DEPTH_STENCIL) {
Keith Whitwell287c94e2010-04-10 16:05:54 +01001104 tex->key.flags |= SVGA3D_SURFACE_HINT_DEPTHSTENCIL;
Brian Paule0542512015-08-13 11:00:58 -07001105 tex->key.flags |= SVGA3D_SURFACE_BIND_DEPTH_STENCIL;
1106 }
1107
Keith Whitwell287c94e2010-04-10 16:05:54 +01001108 tex->key.numMipLevels = template->last_level + 1;
Brian Paule0542512015-08-13 11:00:58 -07001109
1110 tex->key.format = svga_translate_format(svgascreen, template->format,
1111 bindings);
1112 if (tex->key.format == SVGA3D_FORMAT_INVALID) {
Charmaine Leed7a6c1a2016-04-14 17:33:32 -07001113 goto fail;
Brian Paule0542512015-08-13 11:00:58 -07001114 }
1115
Charmaine Lee06bba242016-10-26 15:46:49 -07001116 /* Use typeless formats for sRGB and depth resources. Typeless
Brian Paule0542512015-08-13 11:00:58 -07001117 * formats can be reinterpreted as other formats. For example,
1118 * SVGA3D_R8G8B8A8_UNORM_TYPELESS can be interpreted as
1119 * SVGA3D_R8G8B8A8_UNORM_SRGB or SVGA3D_R8G8B8A8_UNORM.
1120 */
Charmaine Lee06bba242016-10-26 15:46:49 -07001121 if (svgascreen->sws->have_vgpu10 &&
1122 (util_format_is_srgb(template->format) ||
1123 format_has_depth(template->format))) {
Brian Paule0542512015-08-13 11:00:58 -07001124 SVGA3dSurfaceFormat typeless = svga_typeless_format(tex->key.format);
1125 if (0) {
1126 debug_printf("Convert resource type %s -> %s (bind 0x%x)\n",
1127 svga_format_name(tex->key.format),
1128 svga_format_name(typeless),
1129 bindings);
1130 }
Brian Paul3a3c3d12016-06-27 11:18:10 -06001131
1132 if (svga_format_is_uncompressed_snorm(tex->key.format)) {
1133 /* We can't normally render to snorm surfaces, but once we
1134 * substitute a typeless format, we can if the rendertarget view
1135 * is unorm. This can happen with GL_ARB_copy_image.
1136 */
1137 tex->key.flags |= SVGA3D_SURFACE_HINT_RENDERTARGET;
1138 tex->key.flags |= SVGA3D_SURFACE_BIND_RENDER_TARGET;
1139 }
1140
Brian Paule0542512015-08-13 11:00:58 -07001141 tex->key.format = typeless;
1142 }
Keith Whitwell287c94e2010-04-10 16:05:54 +01001143
1144 SVGA_DBG(DEBUG_DMA, "surface_create for texture\n", tex->handle);
Brian Paule0542512015-08-13 11:00:58 -07001145 tex->handle = svga_screen_surface_create(svgascreen, bindings,
Charmaine Lee8a195e22016-10-26 16:15:23 -07001146 tex->b.b.usage,
1147 &tex->validated, &tex->key);
Brian Paule0542512015-08-13 11:00:58 -07001148 if (!tex->handle) {
Charmaine Leed7a6c1a2016-04-14 17:33:32 -07001149 goto fail;
Brian Paule0542512015-08-13 11:00:58 -07001150 }
Charmaine Lee0c065272014-08-12 07:37:12 -06001151
1152 SVGA_DBG(DEBUG_DMA, " --> got sid %p (texture)\n", tex->handle);
Keith Whitwell287c94e2010-04-10 16:05:54 +01001153
Jakob Bornecrantz99d95522011-02-17 17:14:44 +00001154 debug_reference(&tex->b.b.reference,
1155 (debug_reference_descriptor)debug_describe_resource, 0);
1156
Brian Paulac114c62013-04-03 10:23:57 -06001157 tex->size = util_resource_size(template);
Charmaine Lee59f14562016-09-30 16:41:12 -07001158
1159 /* Determine if texture upload buffer can be used to upload this texture */
1160 tex->can_use_upload = svga_texture_transfer_map_can_upload(svgascreen,
1161 &tex->b.b);
1162
Charmaine Lee36261122017-04-25 14:32:59 -06001163 /* Initialize the backing resource cache */
1164 tex->backed_handle = NULL;
1165
Neha Bhende9bc7e312015-10-09 16:10:16 -06001166 svgascreen->hud.total_resource_bytes += tex->size;
1167 svgascreen->hud.num_resources++;
Brian Paulac114c62013-04-03 10:23:57 -06001168
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -06001169 SVGA_STATS_TIME_POP(svgascreen->sws);
1170
Keith Whitwell287c94e2010-04-10 16:05:54 +01001171 return &tex->b.b;
Charmaine Leed7a6c1a2016-04-14 17:33:32 -07001172
1173fail:
1174 if (tex->dirty)
1175 FREE(tex->dirty);
1176 if (tex->rendered_to)
1177 FREE(tex->rendered_to);
1178 if (tex->defined)
1179 FREE(tex->defined);
1180 FREE(tex);
Charmaine Lee2e1cfcc2016-08-19 08:49:17 -06001181fail_notex:
1182 SVGA_STATS_TIME_POP(svgascreen->sws);
Charmaine Leed7a6c1a2016-04-14 17:33:32 -07001183 return NULL;
Keith Whitwell287c94e2010-04-10 16:05:54 +01001184}
1185
1186
Keith Whitwell287c94e2010-04-10 16:05:54 +01001187struct pipe_resource *
1188svga_texture_from_handle(struct pipe_screen *screen,
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001189 const struct pipe_resource *template,
1190 struct winsys_handle *whandle)
Keith Whitwell287c94e2010-04-10 16:05:54 +01001191{
1192 struct svga_winsys_screen *sws = svga_winsys_screen(screen);
Neha Bhende9bc7e312015-10-09 16:10:16 -06001193 struct svga_screen *ss = svga_screen(screen);
Keith Whitwell287c94e2010-04-10 16:05:54 +01001194 struct svga_winsys_surface *srf;
1195 struct svga_texture *tex;
1196 enum SVGA3dSurfaceFormat format = 0;
1197 assert(screen);
1198
1199 /* Only supports one type */
Luca Barbieriae0ef6f2010-08-18 17:28:08 +02001200 if ((template->target != PIPE_TEXTURE_2D &&
1201 template->target != PIPE_TEXTURE_RECT) ||
Keith Whitwell287c94e2010-04-10 16:05:54 +01001202 template->last_level != 0 ||
1203 template->depth0 != 1) {
1204 return NULL;
1205 }
1206
1207 srf = sws->surface_from_handle(sws, whandle, &format);
1208
1209 if (!srf)
1210 return NULL;
1211
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001212 if (!svga_format_is_shareable(ss, template->format, format,
1213 template->bind, true))
1214 goto out_unref;
Keith Whitwell287c94e2010-04-10 16:05:54 +01001215
1216 tex = CALLOC_STRUCT(svga_texture);
1217 if (!tex)
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001218 goto out_unref;
Keith Whitwell287c94e2010-04-10 16:05:54 +01001219
Brian Paule0542512015-08-13 11:00:58 -07001220 tex->defined = CALLOC(template->depth0 * template->array_size,
1221 sizeof(tex->defined[0]));
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001222 if (!tex->defined)
1223 goto out_no_defined;
Brian Paule0542512015-08-13 11:00:58 -07001224
Keith Whitwell287c94e2010-04-10 16:05:54 +01001225 tex->b.b = *template;
1226 tex->b.vtbl = &svga_texture_vtbl;
1227 pipe_reference_init(&tex->b.b.reference, 1);
1228 tex->b.b.screen = screen;
1229
Keith Whitwell287c94e2010-04-10 16:05:54 +01001230 SVGA_DBG(DEBUG_DMA, "wrap surface sid %p\n", srf);
1231
1232 tex->key.cachable = 0;
Brian Paule0542512015-08-13 11:00:58 -07001233 tex->key.format = format;
Keith Whitwell287c94e2010-04-10 16:05:54 +01001234 tex->handle = srf;
1235
Brian Paulc1e60a62014-02-08 09:51:14 -08001236 tex->rendered_to = CALLOC(1, sizeof(tex->rendered_to[0]));
Charmaine Leed7a6c1a2016-04-14 17:33:32 -07001237 if (!tex->rendered_to)
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001238 goto out_no_rendered_to;
Charmaine Leed7a6c1a2016-04-14 17:33:32 -07001239
1240 tex->dirty = CALLOC(1, sizeof(tex->dirty[0]));
1241 if (!tex->dirty)
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001242 goto out_no_dirty;
Charmaine Leed7a6c1a2016-04-14 17:33:32 -07001243
Brian Paule0542512015-08-13 11:00:58 -07001244 tex->imported = TRUE;
Brian Paulc1e60a62014-02-08 09:51:14 -08001245
Neha Bhende9bc7e312015-10-09 16:10:16 -06001246 ss->hud.num_resources++;
1247
Keith Whitwell287c94e2010-04-10 16:05:54 +01001248 return &tex->b.b;
Charmaine Leed7a6c1a2016-04-14 17:33:32 -07001249
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001250out_no_dirty:
1251 FREE(tex->rendered_to);
1252out_no_rendered_to:
1253 FREE(tex->defined);
1254out_no_defined:
Charmaine Leed7a6c1a2016-04-14 17:33:32 -07001255 FREE(tex);
Thomas Hellstromca59fd12017-04-07 14:54:56 +02001256out_unref:
1257 sws->surface_reference(sws, &srf, NULL);
Charmaine Leed7a6c1a2016-04-14 17:33:32 -07001258 return NULL;
Keith Whitwell287c94e2010-04-10 16:05:54 +01001259}
Charmaine Lee63032312015-12-22 11:20:41 -08001260
1261boolean
1262svga_texture_generate_mipmap(struct pipe_context *pipe,
1263 struct pipe_resource *pt,
1264 enum pipe_format format,
1265 unsigned base_level,
1266 unsigned last_level,
1267 unsigned first_layer,
1268 unsigned last_layer)
1269{
1270 struct pipe_sampler_view templ, *psv;
1271 struct svga_pipe_sampler_view *sv;
1272 struct svga_context *svga = svga_context(pipe);
1273 struct svga_texture *tex = svga_texture(pt);
1274 enum pipe_error ret;
1275
1276 assert(svga_have_vgpu10(svga));
1277
1278 /* Only support 2D texture for now */
1279 if (pt->target != PIPE_TEXTURE_2D)
1280 return FALSE;
1281
1282 /* Fallback to the mipmap generation utility for those formats that
1283 * do not support hw generate mipmap
1284 */
1285 if (!svga_format_support_gen_mips(format))
1286 return FALSE;
1287
1288 /* Make sure the texture surface was created with
1289 * SVGA3D_SURFACE_BIND_RENDER_TARGET
1290 */
1291 if (!tex->handle || !(tex->key.flags & SVGA3D_SURFACE_BIND_RENDER_TARGET))
1292 return FALSE;
1293
1294 templ.format = format;
1295 templ.u.tex.first_layer = first_layer;
1296 templ.u.tex.last_layer = last_layer;
1297 templ.u.tex.first_level = base_level;
1298 templ.u.tex.last_level = last_level;
1299
1300 psv = pipe->create_sampler_view(pipe, pt, &templ);
1301 if (psv == NULL)
1302 return FALSE;
1303
1304 sv = svga_pipe_sampler_view(psv);
Charmaine Lee83667012016-02-29 12:00:12 -08001305 ret = svga_validate_pipe_sampler_view(svga, sv);
1306 if (ret != PIPE_OK) {
1307 svga_context_flush(svga, NULL);
1308 ret = svga_validate_pipe_sampler_view(svga, sv);
1309 assert(ret == PIPE_OK);
1310 }
Charmaine Lee63032312015-12-22 11:20:41 -08001311
1312 ret = SVGA3D_vgpu10_GenMips(svga->swc, sv->id, tex->handle);
1313 if (ret != PIPE_OK) {
1314 svga_context_flush(svga, NULL);
1315 ret = SVGA3D_vgpu10_GenMips(svga->swc, sv->id, tex->handle);
1316 }
1317 pipe_sampler_view_reference(&psv, NULL);
1318
1319 svga->hud.num_generate_mipmap++;
1320
1321 return TRUE;
1322}
Charmaine Leef1b33742016-09-06 11:29:41 -07001323
1324
1325/* texture upload buffer default size in bytes */
1326#define TEX_UPLOAD_DEFAULT_SIZE (1024 * 1024)
1327
1328/**
1329 * Create a texture upload buffer
1330 */
1331boolean
1332svga_texture_transfer_map_upload_create(struct svga_context *svga)
1333{
1334 svga->tex_upload = u_upload_create(&svga->pipe, TEX_UPLOAD_DEFAULT_SIZE,
1335 0, PIPE_USAGE_STAGING);
1336 return svga->tex_upload != NULL;
1337}
1338
1339
1340/**
1341 * Destroy the texture upload buffer
1342 */
1343void
1344svga_texture_transfer_map_upload_destroy(struct svga_context *svga)
1345{
1346 u_upload_destroy(svga->tex_upload);
1347}
1348
1349
1350/**
1351 * Returns true if this transfer map request can use the upload buffer.
1352 */
1353boolean
Charmaine Lee59f14562016-09-30 16:41:12 -07001354svga_texture_transfer_map_can_upload(const struct svga_screen *svgascreen,
1355 const struct pipe_resource *texture)
Charmaine Leef1b33742016-09-06 11:29:41 -07001356{
Charmaine Lee59f14562016-09-30 16:41:12 -07001357 if (svgascreen->sws->have_transfer_from_buffer_cmd == FALSE)
Charmaine Leef1b33742016-09-06 11:29:41 -07001358 return FALSE;
1359
1360 /* TransferFromBuffer command is not well supported with multi-samples surface */
1361 if (texture->nr_samples > 1)
1362 return FALSE;
1363
Charmaine Lee8a639142016-09-16 09:50:20 -07001364 if (util_format_is_compressed(texture->format)) {
1365 /* XXX Need to take a closer look to see why texture upload
1366 * with 3D texture with compressed format fails
1367 */
1368 if (texture->target == PIPE_TEXTURE_3D)
1369 return FALSE;
Charmaine Lee8a639142016-09-16 09:50:20 -07001370 }
1371 else if (texture->format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
Charmaine Leef1b33742016-09-06 11:29:41 -07001372 return FALSE;
Charmaine Lee8a639142016-09-16 09:50:20 -07001373 }
Charmaine Leef1b33742016-09-06 11:29:41 -07001374
1375 return TRUE;
1376}
1377
1378
1379/**
1380 * Use upload buffer for the transfer map request.
1381 */
1382void *
1383svga_texture_transfer_map_upload(struct svga_context *svga,
1384 struct svga_transfer *st)
1385{
1386 struct pipe_resource *texture = st->base.resource;
1387 struct pipe_resource *tex_buffer = NULL;
1388 void *tex_map;
1389 unsigned nblocksx, nblocksy;
1390 unsigned offset;
1391 unsigned upload_size;
1392
1393 assert(svga->tex_upload);
1394
1395 st->upload.box.x = st->base.box.x;
1396 st->upload.box.y = st->base.box.y;
1397 st->upload.box.z = st->base.box.z;
1398 st->upload.box.w = st->base.box.width;
1399 st->upload.box.h = st->base.box.height;
1400 st->upload.box.d = st->base.box.depth;
1401 st->upload.nlayers = 1;
1402
1403 switch (texture->target) {
1404 case PIPE_TEXTURE_CUBE:
1405 st->upload.box.z = 0;
1406 break;
1407 case PIPE_TEXTURE_2D_ARRAY:
1408 st->upload.nlayers = st->base.box.depth;
1409 st->upload.box.z = 0;
1410 st->upload.box.d = 1;
1411 break;
1412 case PIPE_TEXTURE_1D_ARRAY:
1413 st->upload.nlayers = st->base.box.depth;
1414 st->upload.box.y = st->upload.box.z = 0;
1415 st->upload.box.d = 1;
1416 break;
1417 default:
1418 break;
1419 }
1420
1421 nblocksx = util_format_get_nblocksx(texture->format, st->base.box.width);
1422 nblocksy = util_format_get_nblocksy(texture->format, st->base.box.height);
1423
1424 st->base.stride = nblocksx * util_format_get_blocksize(texture->format);
1425 st->base.layer_stride = st->base.stride * nblocksy;
1426
1427 /* In order to use the TransferFromBuffer command to update the
1428 * texture content from the buffer, the layer stride for a multi-layers
1429 * surface needs to be in multiples of 16 bytes.
1430 */
1431 if (st->upload.nlayers > 1 && st->base.layer_stride & 15)
1432 return NULL;
1433
1434 upload_size = st->base.layer_stride * st->base.box.depth;
1435 upload_size = align(upload_size, 16);
1436
Charmaine Lee59f14562016-09-30 16:41:12 -07001437#ifdef DEBUG
1438 if (util_format_is_compressed(texture->format)) {
1439 struct svga_texture *tex = svga_texture(texture);
1440 unsigned blockw, blockh, bytesPerBlock;
1441
1442 svga_format_size(tex->key.format, &blockw, &blockh, &bytesPerBlock);
1443
1444 /* dest box must start on block boundary */
1445 assert((st->base.box.x % blockw) == 0);
1446 assert((st->base.box.y % blockh) == 0);
1447 }
1448#endif
1449
Charmaine Leef1b33742016-09-06 11:29:41 -07001450 /* If the upload size exceeds the default buffer size, the
1451 * upload buffer manager code will try to allocate a new buffer
1452 * with the new buffer size.
1453 */
1454 u_upload_alloc(svga->tex_upload, 0, upload_size, 16,
1455 &offset, &tex_buffer, &tex_map);
1456
1457 if (!tex_map) {
1458 return NULL;
1459 }
1460
1461 st->upload.buf = tex_buffer;
1462 st->upload.map = tex_map;
1463 st->upload.offset = offset;
1464
1465 return tex_map;
1466}
1467
1468
1469/**
1470 * Unmap upload map transfer request
1471 */
1472void
1473svga_texture_transfer_unmap_upload(struct svga_context *svga,
1474 struct svga_transfer *st)
1475{
1476 struct svga_winsys_surface *srcsurf;
1477 struct svga_winsys_surface *dstsurf;
1478 struct pipe_resource *texture = st->base.resource;
Charmaine Lee4750c4e2016-09-29 16:41:21 -07001479 struct svga_texture *tex = svga_texture(texture);
Charmaine Leef1b33742016-09-06 11:29:41 -07001480 enum pipe_error ret;
1481 unsigned subResource;
1482 unsigned numMipLevels;
1483 unsigned i, layer;
1484 unsigned offset = st->upload.offset;
1485
1486 assert(svga->tex_upload);
1487 assert(st->upload.buf);
1488
1489 /* unmap the texture upload buffer */
1490 u_upload_unmap(svga->tex_upload);
1491
Charmaine Leeb549f5e2017-06-26 17:24:15 -06001492 srcsurf = svga_buffer_handle(svga, st->upload.buf, 0);
Charmaine Leef1b33742016-09-06 11:29:41 -07001493 dstsurf = svga_texture(texture)->handle;
1494 assert(dstsurf);
1495
1496 numMipLevels = texture->last_level + 1;
1497
1498 for (i = 0, layer = st->slice; i < st->upload.nlayers; i++, layer++) {
1499 subResource = layer * numMipLevels + st->base.level;
1500
1501 /* send a transferFromBuffer command to update the host texture surface */
1502 assert((offset & 15) == 0);
1503
1504 ret = SVGA3D_vgpu10_TransferFromBuffer(svga->swc, srcsurf,
1505 offset,
1506 st->base.stride,
1507 st->base.layer_stride,
1508 dstsurf, subResource,
1509 &st->upload.box);
1510 if (ret != PIPE_OK) {
1511 svga_context_flush(svga, NULL);
1512 ret = SVGA3D_vgpu10_TransferFromBuffer(svga->swc, srcsurf,
1513 offset,
1514 st->base.stride,
1515 st->base.layer_stride,
1516 dstsurf, subResource,
1517 &st->upload.box);
1518 assert(ret == PIPE_OK);
1519 }
1520 offset += st->base.layer_stride;
Charmaine Lee4750c4e2016-09-29 16:41:21 -07001521
1522 /* Set rendered-to flag */
1523 svga_set_texture_rendered_to(tex, layer, st->base.level);
Charmaine Leef1b33742016-09-06 11:29:41 -07001524 }
1525
1526 pipe_resource_reference(&st->upload.buf, NULL);
1527}
Thomas Hellstromdf4d6002017-05-30 15:51:06 +02001528
1529/**
1530 * Does the device format backing this surface have an
1531 * alpha channel?
1532 *
1533 * \param texture[in] The texture whose format we're querying
1534 * \return TRUE if the format has an alpha channel, FALSE otherwise
1535 *
1536 * For locally created textures, the device (svga) format is typically
1537 * identical to svga_format(texture->format), and we can use the gallium
1538 * format tests to determine whether the device format has an alpha channel
1539 * or not. However, for textures backed by imported svga surfaces that is
1540 * not always true, and we have to look at the SVGA3D utilities.
1541 */
1542boolean
1543svga_texture_device_format_has_alpha(struct pipe_resource *texture)
1544{
Brian Paul6158c0b2017-06-30 14:11:01 -07001545 /* the svga_texture() call below is invalid for PIPE_BUFFER resources */
1546 assert(texture->target != PIPE_BUFFER);
1547
Thomas Hellstromdf4d6002017-05-30 15:51:06 +02001548 enum svga3d_block_desc block_desc =
1549 svga3dsurface_get_desc(svga_texture(texture)->key.format)->block_desc;
1550
1551 return !!(block_desc & SVGA3DBLOCKDESC_ALPHA);
1552}