Marek Olšák | ac72a6b | 2018-08-02 17:40:05 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2018 Advanced Micro Devices, Inc. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * on the rights to use, copy, modify, merge, publish, distribute, sub |
| 9 | * license, and/or sell copies of the Software, and to permit persons to whom |
| 10 | * the Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 20 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 21 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 22 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "si_pipe.h" |
| 26 | #include "tgsi/tgsi_text.h" |
| 27 | #include "tgsi/tgsi_ureg.h" |
| 28 | |
| 29 | void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type, |
| 30 | unsigned num_layers) |
| 31 | { |
| 32 | unsigned vs_blit_property; |
| 33 | void **vs; |
| 34 | |
| 35 | switch (type) { |
| 36 | case UTIL_BLITTER_ATTRIB_NONE: |
| 37 | vs = num_layers > 1 ? &sctx->vs_blit_pos_layered : |
| 38 | &sctx->vs_blit_pos; |
| 39 | vs_blit_property = SI_VS_BLIT_SGPRS_POS; |
| 40 | break; |
| 41 | case UTIL_BLITTER_ATTRIB_COLOR: |
| 42 | vs = num_layers > 1 ? &sctx->vs_blit_color_layered : |
| 43 | &sctx->vs_blit_color; |
| 44 | vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR; |
| 45 | break; |
| 46 | case UTIL_BLITTER_ATTRIB_TEXCOORD_XY: |
| 47 | case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW: |
| 48 | assert(num_layers == 1); |
| 49 | vs = &sctx->vs_blit_texcoord; |
| 50 | vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD; |
| 51 | break; |
| 52 | default: |
| 53 | assert(0); |
| 54 | return NULL; |
| 55 | } |
| 56 | if (*vs) |
| 57 | return *vs; |
| 58 | |
| 59 | struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX); |
| 60 | if (!ureg) |
| 61 | return NULL; |
| 62 | |
| 63 | /* Tell the shader to load VS inputs from SGPRs: */ |
| 64 | ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property); |
| 65 | ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true); |
| 66 | |
| 67 | /* This is just a pass-through shader with 1-3 MOV instructions. */ |
| 68 | ureg_MOV(ureg, |
| 69 | ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0), |
| 70 | ureg_DECL_vs_input(ureg, 0)); |
| 71 | |
| 72 | if (type != UTIL_BLITTER_ATTRIB_NONE) { |
| 73 | ureg_MOV(ureg, |
| 74 | ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0), |
| 75 | ureg_DECL_vs_input(ureg, 1)); |
| 76 | } |
| 77 | |
| 78 | if (num_layers > 1) { |
| 79 | struct ureg_src instance_id = |
| 80 | ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0); |
| 81 | struct ureg_dst layer = |
| 82 | ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0); |
| 83 | |
| 84 | ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X), |
| 85 | ureg_scalar(instance_id, TGSI_SWIZZLE_X)); |
| 86 | } |
| 87 | ureg_END(ureg); |
| 88 | |
| 89 | *vs = ureg_create_shader_and_destroy(ureg, &sctx->b); |
| 90 | return *vs; |
| 91 | } |
| 92 | |
| 93 | /** |
| 94 | * This is used when TCS is NULL in the VS->TCS->TES chain. In this case, |
| 95 | * VS passes its outputs to TES directly, so the fixed-function shader only |
| 96 | * has to write TESSOUTER and TESSINNER. |
| 97 | */ |
| 98 | void *si_create_fixed_func_tcs(struct si_context *sctx) |
| 99 | { |
| 100 | struct ureg_src outer, inner; |
| 101 | struct ureg_dst tessouter, tessinner; |
| 102 | struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL); |
| 103 | |
| 104 | if (!ureg) |
| 105 | return NULL; |
| 106 | |
| 107 | outer = ureg_DECL_system_value(ureg, |
| 108 | TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0); |
| 109 | inner = ureg_DECL_system_value(ureg, |
| 110 | TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0); |
| 111 | |
| 112 | tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0); |
| 113 | tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0); |
| 114 | |
| 115 | ureg_MOV(ureg, tessouter, outer); |
| 116 | ureg_MOV(ureg, tessinner, inner); |
| 117 | ureg_END(ureg); |
| 118 | |
| 119 | return ureg_create_shader_and_destroy(ureg, &sctx->b); |
| 120 | } |
| 121 | |
Marek Olšák | 93b8b98 | 2018-08-02 18:15:48 -0400 | [diff] [blame^] | 122 | /* Create a compute shader implementing clear_buffer or copy_buffer. */ |
| 123 | void *si_create_dma_compute_shader(struct pipe_context *ctx, |
| 124 | unsigned num_dwords_per_thread, |
| 125 | bool dst_stream_cache_policy, bool is_copy) |
| 126 | { |
| 127 | assert(util_is_power_of_two_nonzero(num_dwords_per_thread)); |
| 128 | |
| 129 | unsigned store_qualifier = TGSI_MEMORY_COHERENT | TGSI_MEMORY_RESTRICT; |
| 130 | if (dst_stream_cache_policy) |
| 131 | store_qualifier |= TGSI_MEMORY_STREAM_CACHE_POLICY; |
| 132 | |
| 133 | /* Don't cache loads, because there is no reuse. */ |
| 134 | unsigned load_qualifier = store_qualifier | TGSI_MEMORY_STREAM_CACHE_POLICY; |
| 135 | |
| 136 | unsigned num_mem_ops = MAX2(1, num_dwords_per_thread / 4); |
| 137 | unsigned *inst_dwords = alloca(num_mem_ops * sizeof(unsigned)); |
| 138 | |
| 139 | for (unsigned i = 0; i < num_mem_ops; i++) { |
| 140 | if (i*4 < num_dwords_per_thread) |
| 141 | inst_dwords[i] = MIN2(4, num_dwords_per_thread - i*4); |
| 142 | } |
| 143 | |
| 144 | struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE); |
| 145 | if (!ureg) |
| 146 | return NULL; |
| 147 | |
| 148 | ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 64); |
| 149 | ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 1); |
| 150 | ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1); |
| 151 | |
| 152 | struct ureg_src value; |
| 153 | if (!is_copy) { |
| 154 | ureg_property(ureg, TGSI_PROPERTY_CS_USER_DATA_DWORDS, inst_dwords[0]); |
| 155 | value = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_CS_USER_DATA, 0); |
| 156 | } |
| 157 | |
| 158 | struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0); |
| 159 | struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0); |
| 160 | struct ureg_dst store_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X); |
| 161 | struct ureg_dst load_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X); |
| 162 | struct ureg_dst dstbuf = ureg_dst(ureg_DECL_buffer(ureg, 0, false)); |
| 163 | struct ureg_src srcbuf; |
| 164 | struct ureg_src *values = NULL; |
| 165 | |
| 166 | if (is_copy) { |
| 167 | srcbuf = ureg_DECL_buffer(ureg, 1, false); |
| 168 | values = malloc(num_mem_ops * sizeof(struct ureg_src)); |
| 169 | } |
| 170 | |
| 171 | /* If there are multiple stores, the first store writes into 0+tid, |
| 172 | * the 2nd store writes into 64+tid, the 3rd store writes into 128+tid, etc. |
| 173 | */ |
| 174 | ureg_UMAD(ureg, store_addr, blk, ureg_imm1u(ureg, 64 * num_mem_ops), tid); |
| 175 | /* Convert from a "store size unit" into bytes. */ |
| 176 | ureg_UMUL(ureg, store_addr, ureg_src(store_addr), |
| 177 | ureg_imm1u(ureg, 4 * inst_dwords[0])); |
| 178 | ureg_MOV(ureg, load_addr, ureg_src(store_addr)); |
| 179 | |
| 180 | /* Distance between a load and a store for latency hiding. */ |
| 181 | unsigned load_store_distance = is_copy ? 8 : 0; |
| 182 | |
| 183 | for (unsigned i = 0; i < num_mem_ops + load_store_distance; i++) { |
| 184 | int d = i - load_store_distance; |
| 185 | |
| 186 | if (is_copy && i < num_mem_ops) { |
| 187 | if (i) { |
| 188 | ureg_UADD(ureg, load_addr, ureg_src(load_addr), |
| 189 | ureg_imm1u(ureg, 4 * inst_dwords[i] * 64)); |
| 190 | } |
| 191 | |
| 192 | values[i] = ureg_src(ureg_DECL_temporary(ureg)); |
| 193 | struct ureg_dst dst = |
| 194 | ureg_writemask(ureg_dst(values[i]), |
| 195 | u_bit_consecutive(0, inst_dwords[i])); |
| 196 | struct ureg_src srcs[] = {srcbuf, ureg_src(load_addr)}; |
| 197 | ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dst, 1, srcs, 2, |
| 198 | load_qualifier, TGSI_TEXTURE_BUFFER, 0); |
| 199 | } |
| 200 | |
| 201 | if (d >= 0) { |
| 202 | if (d) { |
| 203 | ureg_UADD(ureg, store_addr, ureg_src(store_addr), |
| 204 | ureg_imm1u(ureg, 4 * inst_dwords[d] * 64)); |
| 205 | } |
| 206 | |
| 207 | struct ureg_dst dst = |
| 208 | ureg_writemask(dstbuf, u_bit_consecutive(0, inst_dwords[d])); |
| 209 | struct ureg_src srcs[] = |
| 210 | {ureg_src(store_addr), is_copy ? values[d] : value}; |
| 211 | ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst, 1, srcs, 2, |
| 212 | store_qualifier, TGSI_TEXTURE_BUFFER, 0); |
| 213 | } |
| 214 | } |
| 215 | ureg_END(ureg); |
| 216 | |
| 217 | struct pipe_compute_state state = {}; |
| 218 | state.ir_type = PIPE_SHADER_IR_TGSI; |
| 219 | state.prog = ureg_get_tokens(ureg, NULL); |
| 220 | |
| 221 | void *cs = ctx->create_compute_state(ctx, &state); |
| 222 | ureg_destroy(ureg); |
| 223 | free(values); |
| 224 | return cs; |
| 225 | } |
| 226 | |
Marek Olšák | ac72a6b | 2018-08-02 17:40:05 -0400 | [diff] [blame] | 227 | /* Create the compute shader that is used to collect the results. |
| 228 | * |
| 229 | * One compute grid with a single thread is launched for every query result |
| 230 | * buffer. The thread (optionally) reads a previous summary buffer, then |
| 231 | * accumulates data from the query result buffer, and writes the result either |
| 232 | * to a summary buffer to be consumed by the next grid invocation or to the |
| 233 | * user-supplied buffer. |
| 234 | * |
| 235 | * Data layout: |
| 236 | * |
| 237 | * CONST |
| 238 | * 0.x = end_offset |
| 239 | * 0.y = result_stride |
| 240 | * 0.z = result_count |
| 241 | * 0.w = bit field: |
| 242 | * 1: read previously accumulated values |
| 243 | * 2: write accumulated values for chaining |
| 244 | * 4: write result available |
| 245 | * 8: convert result to boolean (0/1) |
| 246 | * 16: only read one dword and use that as result |
| 247 | * 32: apply timestamp conversion |
| 248 | * 64: store full 64 bits result |
| 249 | * 128: store signed 32 bits result |
| 250 | * 256: SO_OVERFLOW mode: take the difference of two successive half-pairs |
| 251 | * 1.x = fence_offset |
| 252 | * 1.y = pair_stride |
| 253 | * 1.z = pair_count |
| 254 | * |
| 255 | * BUFFER[0] = query result buffer |
| 256 | * BUFFER[1] = previous summary buffer |
| 257 | * BUFFER[2] = next summary buffer or user-supplied buffer |
| 258 | */ |
| 259 | void *si_create_query_result_cs(struct si_context *sctx) |
| 260 | { |
| 261 | /* TEMP[0].xy = accumulated result so far |
| 262 | * TEMP[0].z = result not available |
| 263 | * |
| 264 | * TEMP[1].x = current result index |
| 265 | * TEMP[1].y = current pair index |
| 266 | */ |
| 267 | static const char text_tmpl[] = |
| 268 | "COMP\n" |
| 269 | "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n" |
| 270 | "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n" |
| 271 | "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n" |
| 272 | "DCL BUFFER[0]\n" |
| 273 | "DCL BUFFER[1]\n" |
| 274 | "DCL BUFFER[2]\n" |
| 275 | "DCL CONST[0][0..1]\n" |
| 276 | "DCL TEMP[0..5]\n" |
| 277 | "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n" |
| 278 | "IMM[1] UINT32 {1, 2, 4, 8}\n" |
| 279 | "IMM[2] UINT32 {16, 32, 64, 128}\n" |
| 280 | "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */ |
| 281 | "IMM[4] UINT32 {256, 0, 0, 0}\n" |
| 282 | |
| 283 | "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n" |
| 284 | "UIF TEMP[5]\n" |
| 285 | /* Check result availability. */ |
| 286 | "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n" |
| 287 | "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n" |
| 288 | "MOV TEMP[1], TEMP[0].zzzz\n" |
| 289 | "NOT TEMP[0].z, TEMP[0].zzzz\n" |
| 290 | |
| 291 | /* Load result if available. */ |
| 292 | "UIF TEMP[1]\n" |
| 293 | "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n" |
| 294 | "ENDIF\n" |
| 295 | "ELSE\n" |
| 296 | /* Load previously accumulated result if requested. */ |
| 297 | "MOV TEMP[0], IMM[0].xxxx\n" |
| 298 | "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n" |
| 299 | "UIF TEMP[4]\n" |
| 300 | "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n" |
| 301 | "ENDIF\n" |
| 302 | |
| 303 | "MOV TEMP[1].x, IMM[0].xxxx\n" |
| 304 | "BGNLOOP\n" |
| 305 | /* Break if accumulated result so far is not available. */ |
| 306 | "UIF TEMP[0].zzzz\n" |
| 307 | "BRK\n" |
| 308 | "ENDIF\n" |
| 309 | |
| 310 | /* Break if result_index >= result_count. */ |
| 311 | "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n" |
| 312 | "UIF TEMP[5]\n" |
| 313 | "BRK\n" |
| 314 | "ENDIF\n" |
| 315 | |
| 316 | /* Load fence and check result availability */ |
| 317 | "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n" |
| 318 | "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n" |
| 319 | "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n" |
| 320 | "NOT TEMP[0].z, TEMP[0].zzzz\n" |
| 321 | "UIF TEMP[0].zzzz\n" |
| 322 | "BRK\n" |
| 323 | "ENDIF\n" |
| 324 | |
| 325 | "MOV TEMP[1].y, IMM[0].xxxx\n" |
| 326 | "BGNLOOP\n" |
| 327 | /* Load start and end. */ |
| 328 | "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n" |
| 329 | "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n" |
| 330 | "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n" |
| 331 | |
| 332 | "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n" |
| 333 | "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n" |
| 334 | |
| 335 | "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n" |
| 336 | |
| 337 | "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n" |
| 338 | "UIF TEMP[5].zzzz\n" |
| 339 | /* Load second start/end half-pair and |
| 340 | * take the difference |
| 341 | */ |
| 342 | "UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n" |
| 343 | "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n" |
| 344 | "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n" |
| 345 | |
| 346 | "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n" |
| 347 | "U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n" |
| 348 | "ENDIF\n" |
| 349 | |
| 350 | "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n" |
| 351 | |
| 352 | /* Increment pair index */ |
| 353 | "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n" |
| 354 | "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n" |
| 355 | "UIF TEMP[5]\n" |
| 356 | "BRK\n" |
| 357 | "ENDIF\n" |
| 358 | "ENDLOOP\n" |
| 359 | |
| 360 | /* Increment result index */ |
| 361 | "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n" |
| 362 | "ENDLOOP\n" |
| 363 | "ENDIF\n" |
| 364 | |
| 365 | "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n" |
| 366 | "UIF TEMP[4]\n" |
| 367 | /* Store accumulated data for chaining. */ |
| 368 | "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n" |
| 369 | "ELSE\n" |
| 370 | "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n" |
| 371 | "UIF TEMP[4]\n" |
| 372 | /* Store result availability. */ |
| 373 | "NOT TEMP[0].z, TEMP[0]\n" |
| 374 | "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n" |
| 375 | "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n" |
| 376 | |
| 377 | "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n" |
| 378 | "UIF TEMP[4]\n" |
| 379 | "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n" |
| 380 | "ENDIF\n" |
| 381 | "ELSE\n" |
| 382 | /* Store result if it is available. */ |
| 383 | "NOT TEMP[4], TEMP[0].zzzz\n" |
| 384 | "UIF TEMP[4]\n" |
| 385 | /* Apply timestamp conversion */ |
| 386 | "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n" |
| 387 | "UIF TEMP[4]\n" |
| 388 | "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n" |
| 389 | "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n" |
| 390 | "ENDIF\n" |
| 391 | |
| 392 | /* Convert to boolean */ |
| 393 | "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n" |
| 394 | "UIF TEMP[4]\n" |
| 395 | "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n" |
| 396 | "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n" |
| 397 | "MOV TEMP[0].y, IMM[0].xxxx\n" |
| 398 | "ENDIF\n" |
| 399 | |
| 400 | "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n" |
| 401 | "UIF TEMP[4]\n" |
| 402 | "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n" |
| 403 | "ELSE\n" |
| 404 | /* Clamping */ |
| 405 | "UIF TEMP[0].yyyy\n" |
| 406 | "MOV TEMP[0].x, IMM[0].wwww\n" |
| 407 | "ENDIF\n" |
| 408 | |
| 409 | "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n" |
| 410 | "UIF TEMP[4]\n" |
| 411 | "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n" |
| 412 | "ENDIF\n" |
| 413 | |
| 414 | "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n" |
| 415 | "ENDIF\n" |
| 416 | "ENDIF\n" |
| 417 | "ENDIF\n" |
| 418 | "ENDIF\n" |
| 419 | |
| 420 | "END\n"; |
| 421 | |
| 422 | char text[sizeof(text_tmpl) + 32]; |
| 423 | struct tgsi_token tokens[1024]; |
| 424 | struct pipe_compute_state state = {}; |
| 425 | |
| 426 | /* Hard code the frequency into the shader so that the backend can |
| 427 | * use the full range of optimizations for divide-by-constant. |
| 428 | */ |
| 429 | snprintf(text, sizeof(text), text_tmpl, |
| 430 | sctx->screen->info.clock_crystal_freq); |
| 431 | |
| 432 | if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) { |
| 433 | assert(false); |
| 434 | return NULL; |
| 435 | } |
| 436 | |
| 437 | state.ir_type = PIPE_SHADER_IR_TGSI; |
| 438 | state.prog = tokens; |
| 439 | |
| 440 | return sctx->b.create_compute_state(&sctx->b, &state); |
| 441 | } |