Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
Kenneth Graunke | ec44d56 | 2013-09-17 23:32:10 -0700 | [diff] [blame] | 24 | /** @file brw_fs_generator.cpp |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 25 | * |
Kenneth Graunke | ec44d56 | 2013-09-17 23:32:10 -0700 | [diff] [blame] | 26 | * This file supports generating code from the FS LIR to the actual |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 27 | * native instructions. |
| 28 | */ |
| 29 | |
| 30 | extern "C" { |
| 31 | #include "main/macros.h" |
| 32 | #include "brw_context.h" |
| 33 | #include "brw_eu.h" |
| 34 | } /* extern "C" */ |
| 35 | |
| 36 | #include "brw_fs.h" |
Eric Anholt | 5ed57d9 | 2012-10-03 13:03:12 -0700 | [diff] [blame] | 37 | #include "brw_cfg.h" |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 38 | |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 39 | fs_generator::fs_generator(struct brw_context *brw, |
Kenneth Graunke | 2d4ac9b | 2014-05-14 01:21:02 -0700 | [diff] [blame] | 40 | void *mem_ctx, |
Kenneth Graunke | cca6dc9 | 2014-05-14 00:41:41 -0700 | [diff] [blame] | 41 | const struct brw_wm_prog_key *key, |
| 42 | struct brw_wm_prog_data *prog_data, |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 43 | struct gl_shader_program *prog, |
| 44 | struct gl_fragment_program *fp, |
Matt Turner | cd1c1d3 | 2014-05-14 15:05:09 -0700 | [diff] [blame] | 45 | bool dual_source_output, |
| 46 | bool debug_flag) |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 47 | |
Kenneth Graunke | cca6dc9 | 2014-05-14 00:41:41 -0700 | [diff] [blame] | 48 | : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp), |
Matt Turner | cd1c1d3 | 2014-05-14 15:05:09 -0700 | [diff] [blame] | 49 | dual_source_output(dual_source_output), debug_flag(debug_flag), |
| 50 | mem_ctx(mem_ctx) |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 51 | { |
Kenneth Graunke | 8c9a54e | 2013-07-06 00:46:38 -0700 | [diff] [blame] | 52 | ctx = &brw->ctx; |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 53 | |
Kenneth Graunke | 9136723 | 2012-11-20 19:26:52 -0800 | [diff] [blame] | 54 | p = rzalloc(mem_ctx, struct brw_compile); |
| 55 | brw_init_compile(brw, p, mem_ctx); |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 56 | } |
| 57 | |
| 58 | fs_generator::~fs_generator() |
| 59 | { |
| 60 | } |
| 61 | |
Matt Turner | b5fd762 | 2014-05-16 13:06:45 -0700 | [diff] [blame^] | 62 | bool |
Eric Anholt | beafced | 2012-12-06 10:15:08 -0800 | [diff] [blame] | 63 | fs_generator::patch_discard_jumps_to_fb_writes() |
| 64 | { |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 65 | if (brw->gen < 6 || this->discard_halt_patches.is_empty()) |
Matt Turner | b5fd762 | 2014-05-16 13:06:45 -0700 | [diff] [blame^] | 66 | return false; |
Eric Anholt | beafced | 2012-12-06 10:15:08 -0800 | [diff] [blame] | 67 | |
| 68 | /* There is a somewhat strange undocumented requirement of using |
| 69 | * HALT, according to the simulator. If some channel has HALTed to |
| 70 | * a particular UIP, then by the end of the program, every channel |
| 71 | * must have HALTed to that UIP. Furthermore, the tracking is a |
| 72 | * stack, so you can't do the final halt of a UIP after starting |
| 73 | * halting to a new UIP. |
| 74 | * |
| 75 | * Symptoms of not emitting this instruction on actual hardware |
| 76 | * included GPU hangs and sparkly rendering on the piglit discard |
| 77 | * tests. |
| 78 | */ |
| 79 | struct brw_instruction *last_halt = gen6_HALT(p); |
| 80 | last_halt->bits3.break_cont.uip = 2; |
| 81 | last_halt->bits3.break_cont.jip = 2; |
| 82 | |
| 83 | int ip = p->nr_insn; |
| 84 | |
| 85 | foreach_list(node, &this->discard_halt_patches) { |
| 86 | ip_record *patch_ip = (ip_record *)node; |
| 87 | struct brw_instruction *patch = &p->store[patch_ip->ip]; |
| 88 | |
| 89 | assert(patch->header.opcode == BRW_OPCODE_HALT); |
| 90 | /* HALT takes a half-instruction distance from the pre-incremented IP. */ |
| 91 | patch->bits3.break_cont.uip = (ip - patch_ip->ip) * 2; |
| 92 | } |
| 93 | |
| 94 | this->discard_halt_patches.make_empty(); |
Matt Turner | b5fd762 | 2014-05-16 13:06:45 -0700 | [diff] [blame^] | 95 | return true; |
Eric Anholt | beafced | 2012-12-06 10:15:08 -0800 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 99 | fs_generator::generate_fb_write(fs_inst *inst) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 100 | { |
Kenneth Graunke | 2e5a1a2 | 2011-10-07 12:26:50 -0700 | [diff] [blame] | 101 | bool eot = inst->eot; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 102 | struct brw_reg implied_header; |
Eric Anholt | 2936287 | 2012-04-25 13:58:07 -0700 | [diff] [blame] | 103 | uint32_t msg_control; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 104 | |
| 105 | /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied |
| 106 | * move, here's g1. |
| 107 | */ |
| 108 | brw_push_insn_state(p); |
| 109 | brw_set_mask_control(p, BRW_MASK_DISABLE); |
Eric Anholt | 171ec95 | 2014-03-04 15:12:40 -0800 | [diff] [blame] | 110 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 111 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 112 | |
| 113 | if (inst->header_present) { |
Eric Anholt | d92f593 | 2014-02-13 21:37:50 -0800 | [diff] [blame] | 114 | /* On HSW, the GPU will use the predicate on SENDC, unless the header is |
| 115 | * present. |
| 116 | */ |
Kenneth Graunke | c96fdeb | 2014-05-14 00:24:50 -0700 | [diff] [blame] | 117 | if ((fp && fp->UsesKill) || key->alpha_test_func) { |
Eric Anholt | d92f593 | 2014-02-13 21:37:50 -0800 | [diff] [blame] | 118 | struct brw_reg pixel_mask; |
| 119 | |
| 120 | if (brw->gen >= 6) |
| 121 | pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW); |
| 122 | else |
| 123 | pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); |
| 124 | |
| 125 | brw_MOV(p, pixel_mask, brw_flag_reg(0, 1)); |
| 126 | } |
| 127 | |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 128 | if (brw->gen >= 6) { |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 129 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
| 130 | brw_MOV(p, |
| 131 | retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD), |
| 132 | retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); |
| 133 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 134 | |
Kenneth Graunke | c96fdeb | 2014-05-14 00:24:50 -0700 | [diff] [blame] | 135 | if (inst->target > 0 && key->replicate_alpha) { |
Anuj Phogat | e592f7d | 2012-08-01 16:32:06 -0700 | [diff] [blame] | 136 | /* Set "Source0 Alpha Present to RenderTarget" bit in message |
| 137 | * header. |
| 138 | */ |
| 139 | brw_OR(p, |
| 140 | vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)), |
| 141 | vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)), |
| 142 | brw_imm_ud(0x1 << 11)); |
| 143 | } |
| 144 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 145 | if (inst->target > 0) { |
| 146 | /* Set the render target index for choosing BLEND_STATE. */ |
Eric Anholt | 3daa2d9 | 2011-07-25 15:39:03 -0700 | [diff] [blame] | 147 | brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, |
| 148 | inst->base_mrf, 2), |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 149 | BRW_REGISTER_TYPE_UD), |
| 150 | brw_imm_ud(inst->target)); |
| 151 | } |
| 152 | |
| 153 | implied_header = brw_null_reg(); |
| 154 | } else { |
| 155 | implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW); |
| 156 | |
| 157 | brw_MOV(p, |
| 158 | brw_message_reg(inst->base_mrf + 1), |
| 159 | brw_vec8_grf(1, 0)); |
| 160 | } |
| 161 | } else { |
| 162 | implied_header = brw_null_reg(); |
| 163 | } |
| 164 | |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 165 | if (this->dual_source_output) |
Eric Anholt | 2936287 | 2012-04-25 13:58:07 -0700 | [diff] [blame] | 166 | msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01; |
Kenneth Graunke | a303df8 | 2012-11-20 13:50:52 -0800 | [diff] [blame] | 167 | else if (dispatch_width == 16) |
Eric Anholt | 2936287 | 2012-04-25 13:58:07 -0700 | [diff] [blame] | 168 | msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE; |
| 169 | else |
| 170 | msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01; |
| 171 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 172 | brw_pop_insn_state(p); |
| 173 | |
Eric Anholt | 3c9dc2d | 2013-10-02 14:07:40 -0700 | [diff] [blame] | 174 | uint32_t surf_index = |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 175 | prog_data->binding_table.render_target_start + inst->target; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 176 | brw_fb_WRITE(p, |
Kenneth Graunke | a303df8 | 2012-11-20 13:50:52 -0800 | [diff] [blame] | 177 | dispatch_width, |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 178 | inst->base_mrf, |
| 179 | implied_header, |
Eric Anholt | 2936287 | 2012-04-25 13:58:07 -0700 | [diff] [blame] | 180 | msg_control, |
Eric Anholt | 3c9dc2d | 2013-10-02 14:07:40 -0700 | [diff] [blame] | 181 | surf_index, |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 182 | inst->mlen, |
| 183 | 0, |
| 184 | eot, |
| 185 | inst->header_present); |
Kenneth Graunke | 6d89bc8 | 2013-08-14 19:49:33 -0700 | [diff] [blame] | 186 | |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 187 | brw_mark_surface_used(&prog_data->base, surf_index); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 188 | } |
| 189 | |
Topi Pohjolainen | 9927d7a | 2013-12-17 14:00:50 +0200 | [diff] [blame] | 190 | void |
| 191 | fs_generator::generate_blorp_fb_write(fs_inst *inst) |
| 192 | { |
| 193 | brw_fb_WRITE(p, |
| 194 | 16 /* dispatch_width */, |
| 195 | inst->base_mrf, |
| 196 | brw_reg_from_fs_reg(&inst->src[0]), |
| 197 | BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE, |
| 198 | inst->target, |
| 199 | inst->mlen, |
| 200 | 0, |
| 201 | true, |
| 202 | inst->header_present); |
| 203 | } |
| 204 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 205 | /* Computes the integer pixel x,y values from the origin. |
| 206 | * |
| 207 | * This is the basis of gl_FragCoord computation, but is also used |
| 208 | * pre-gen6 for computing the deltas from v0 for computing |
| 209 | * interpolation. |
| 210 | */ |
| 211 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 212 | fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 213 | { |
| 214 | struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); |
| 215 | struct brw_reg src; |
| 216 | struct brw_reg deltas; |
| 217 | |
| 218 | if (is_x) { |
| 219 | src = stride(suboffset(g1_uw, 4), 2, 4, 0); |
| 220 | deltas = brw_imm_v(0x10101010); |
| 221 | } else { |
| 222 | src = stride(suboffset(g1_uw, 5), 2, 4, 0); |
| 223 | deltas = brw_imm_v(0x11001100); |
| 224 | } |
| 225 | |
Kenneth Graunke | a303df8 | 2012-11-20 13:50:52 -0800 | [diff] [blame] | 226 | if (dispatch_width == 16) { |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 227 | dst = vec16(dst); |
| 228 | } |
| 229 | |
Eric Anholt | 746e3e3 | 2013-11-12 15:33:27 -0800 | [diff] [blame] | 230 | /* We do this SIMD8 or SIMD16, but since the destination is UW we |
| 231 | * don't do compression in the SIMD16 case. |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 232 | */ |
| 233 | brw_push_insn_state(p); |
| 234 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 235 | brw_ADD(p, dst, src, deltas); |
| 236 | brw_pop_insn_state(p); |
| 237 | } |
| 238 | |
| 239 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 240 | fs_generator::generate_linterp(fs_inst *inst, |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 241 | struct brw_reg dst, struct brw_reg *src) |
| 242 | { |
| 243 | struct brw_reg delta_x = src[0]; |
| 244 | struct brw_reg delta_y = src[1]; |
| 245 | struct brw_reg interp = src[2]; |
| 246 | |
| 247 | if (brw->has_pln && |
| 248 | delta_y.nr == delta_x.nr + 1 && |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 249 | (brw->gen >= 6 || (delta_x.nr & 1) == 0)) { |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 250 | brw_PLN(p, dst, interp, delta_x); |
| 251 | } else { |
| 252 | brw_LINE(p, brw_null_reg(), interp, delta_x); |
| 253 | brw_MAC(p, dst, suboffset(interp, 1), delta_y); |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 258 | fs_generator::generate_math1_gen7(fs_inst *inst, |
Kenneth Graunke | a73c65c | 2011-10-18 12:24:47 -0700 | [diff] [blame] | 259 | struct brw_reg dst, |
| 260 | struct brw_reg src0) |
| 261 | { |
| 262 | assert(inst->mlen == 0); |
| 263 | brw_math(p, dst, |
| 264 | brw_math_function(inst->opcode), |
Kenneth Graunke | a73c65c | 2011-10-18 12:24:47 -0700 | [diff] [blame] | 265 | 0, src0, |
| 266 | BRW_MATH_DATA_VECTOR, |
| 267 | BRW_MATH_PRECISION_FULL); |
| 268 | } |
| 269 | |
| 270 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 271 | fs_generator::generate_math2_gen7(fs_inst *inst, |
Kenneth Graunke | a73c65c | 2011-10-18 12:24:47 -0700 | [diff] [blame] | 272 | struct brw_reg dst, |
| 273 | struct brw_reg src0, |
| 274 | struct brw_reg src1) |
| 275 | { |
| 276 | assert(inst->mlen == 0); |
| 277 | brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1); |
| 278 | } |
| 279 | |
| 280 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 281 | fs_generator::generate_math1_gen6(fs_inst *inst, |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 282 | struct brw_reg dst, |
| 283 | struct brw_reg src0) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 284 | { |
Eric Anholt | af3c980 | 2011-05-02 09:45:40 -0700 | [diff] [blame] | 285 | int op = brw_math_function(inst->opcode); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 286 | |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 287 | assert(inst->mlen == 0); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 288 | |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 289 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 290 | brw_math(p, dst, |
| 291 | op, |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 292 | 0, src0, |
| 293 | BRW_MATH_DATA_VECTOR, |
| 294 | BRW_MATH_PRECISION_FULL); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 295 | |
Kenneth Graunke | a303df8 | 2012-11-20 13:50:52 -0800 | [diff] [blame] | 296 | if (dispatch_width == 16) { |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 297 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |
| 298 | brw_math(p, sechalf(dst), |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 299 | op, |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 300 | 0, sechalf(src0), |
| 301 | BRW_MATH_DATA_VECTOR, |
| 302 | BRW_MATH_PRECISION_FULL); |
| 303 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
| 304 | } |
| 305 | } |
| 306 | |
| 307 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 308 | fs_generator::generate_math2_gen6(fs_inst *inst, |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 309 | struct brw_reg dst, |
| 310 | struct brw_reg src0, |
| 311 | struct brw_reg src1) |
| 312 | { |
| 313 | int op = brw_math_function(inst->opcode); |
| 314 | |
| 315 | assert(inst->mlen == 0); |
| 316 | |
| 317 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 318 | brw_math2(p, dst, op, src0, src1); |
| 319 | |
Kenneth Graunke | a303df8 | 2012-11-20 13:50:52 -0800 | [diff] [blame] | 320 | if (dispatch_width == 16) { |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 321 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |
| 322 | brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1)); |
| 323 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 328 | fs_generator::generate_math_gen4(fs_inst *inst, |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 329 | struct brw_reg dst, |
| 330 | struct brw_reg src) |
| 331 | { |
| 332 | int op = brw_math_function(inst->opcode); |
| 333 | |
| 334 | assert(inst->mlen >= 1); |
| 335 | |
| 336 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 337 | brw_math(p, dst, |
| 338 | op, |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 339 | inst->base_mrf, src, |
| 340 | BRW_MATH_DATA_VECTOR, |
| 341 | BRW_MATH_PRECISION_FULL); |
| 342 | |
Kenneth Graunke | a303df8 | 2012-11-20 13:50:52 -0800 | [diff] [blame] | 343 | if (dispatch_width == 16) { |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 344 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |
| 345 | brw_math(p, sechalf(dst), |
| 346 | op, |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 347 | inst->base_mrf + 1, sechalf(src), |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 348 | BRW_MATH_DATA_VECTOR, |
| 349 | BRW_MATH_PRECISION_FULL); |
| 350 | |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 351 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 352 | } |
| 353 | } |
| 354 | |
| 355 | void |
Kenneth Graunke | 1b77d21 | 2013-03-30 00:15:54 -0700 | [diff] [blame] | 356 | fs_generator::generate_math_g45(fs_inst *inst, |
| 357 | struct brw_reg dst, |
| 358 | struct brw_reg src) |
| 359 | { |
| 360 | if (inst->opcode == SHADER_OPCODE_POW || |
| 361 | inst->opcode == SHADER_OPCODE_INT_QUOTIENT || |
| 362 | inst->opcode == SHADER_OPCODE_INT_REMAINDER) { |
| 363 | generate_math_gen4(inst, dst, src); |
| 364 | return; |
| 365 | } |
| 366 | |
| 367 | int op = brw_math_function(inst->opcode); |
| 368 | |
| 369 | assert(inst->mlen >= 1); |
| 370 | |
| 371 | brw_math(p, dst, |
| 372 | op, |
| 373 | inst->base_mrf, src, |
| 374 | BRW_MATH_DATA_VECTOR, |
| 375 | BRW_MATH_PRECISION_FULL); |
| 376 | } |
| 377 | |
| 378 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 379 | fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 380 | { |
| 381 | int msg_type = -1; |
| 382 | int rlen = 4; |
| 383 | uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; |
Eric Anholt | 7e84a64 | 2011-11-09 16:07:57 -0800 | [diff] [blame] | 384 | uint32_t return_format; |
| 385 | |
| 386 | switch (dst.type) { |
| 387 | case BRW_REGISTER_TYPE_D: |
| 388 | return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32; |
| 389 | break; |
| 390 | case BRW_REGISTER_TYPE_UD: |
| 391 | return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32; |
| 392 | break; |
| 393 | default: |
| 394 | return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; |
| 395 | break; |
| 396 | } |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 397 | |
Chia-I Wu | 3db52b6 | 2013-09-30 14:12:19 +0800 | [diff] [blame] | 398 | if (dispatch_width == 16 && |
| 399 | !inst->force_uncompressed && !inst->force_sechalf) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 400 | simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; |
| 401 | |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 402 | if (brw->gen >= 5) { |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 403 | switch (inst->opcode) { |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 404 | case SHADER_OPCODE_TEX: |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 405 | if (inst->shadow_compare) { |
| 406 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE; |
| 407 | } else { |
| 408 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE; |
| 409 | } |
| 410 | break; |
| 411 | case FS_OPCODE_TXB: |
| 412 | if (inst->shadow_compare) { |
| 413 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE; |
| 414 | } else { |
| 415 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS; |
| 416 | } |
| 417 | break; |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 418 | case SHADER_OPCODE_TXL: |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 419 | if (inst->shadow_compare) { |
| 420 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; |
| 421 | } else { |
| 422 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; |
| 423 | } |
| 424 | break; |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 425 | case SHADER_OPCODE_TXS: |
Kenneth Graunke | ecf8963 | 2011-06-19 01:47:50 -0700 | [diff] [blame] | 426 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO; |
| 427 | break; |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 428 | case SHADER_OPCODE_TXD: |
Kenneth Graunke | 899017f | 2013-01-04 07:53:09 -0800 | [diff] [blame] | 429 | if (inst->shadow_compare) { |
| 430 | /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */ |
Kenneth Graunke | 794de2f | 2013-07-06 00:15:44 -0700 | [diff] [blame] | 431 | assert(brw->is_haswell); |
Kenneth Graunke | 899017f | 2013-01-04 07:53:09 -0800 | [diff] [blame] | 432 | msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE; |
| 433 | } else { |
| 434 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS; |
| 435 | } |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 436 | break; |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 437 | case SHADER_OPCODE_TXF: |
Kenneth Graunke | 30be2cc | 2011-08-25 17:13:37 -0700 | [diff] [blame] | 438 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; |
| 439 | break; |
Topi Pohjolainen | ce527a6 | 2013-12-10 16:36:31 +0200 | [diff] [blame] | 440 | case SHADER_OPCODE_TXF_CMS: |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 441 | if (brw->gen >= 7) |
Chris Forbes | f52ce6a | 2013-01-24 21:35:15 +1300 | [diff] [blame] | 442 | msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS; |
| 443 | else |
| 444 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; |
| 445 | break; |
Topi Pohjolainen | 41d397f | 2013-12-10 16:38:15 +0200 | [diff] [blame] | 446 | case SHADER_OPCODE_TXF_UMS: |
| 447 | assert(brw->gen >= 7); |
| 448 | msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS; |
| 449 | break; |
Chris Forbes | 7629c48 | 2013-11-30 10:32:16 +1300 | [diff] [blame] | 450 | case SHADER_OPCODE_TXF_MCS: |
| 451 | assert(brw->gen >= 7); |
| 452 | msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS; |
| 453 | break; |
Matt Turner | b8aa9f7 | 2013-03-06 14:47:01 -0800 | [diff] [blame] | 454 | case SHADER_OPCODE_LOD: |
| 455 | msg_type = GEN5_SAMPLER_MESSAGE_LOD; |
| 456 | break; |
Chris Forbes | fb45550 | 2013-03-31 21:31:12 +1300 | [diff] [blame] | 457 | case SHADER_OPCODE_TG4: |
Chris Forbes | 3c98d77 | 2013-10-10 19:57:29 +1300 | [diff] [blame] | 458 | if (inst->shadow_compare) { |
| 459 | assert(brw->gen >= 7); |
| 460 | msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C; |
| 461 | } else { |
| 462 | assert(brw->gen >= 6); |
| 463 | msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4; |
| 464 | } |
Chris Forbes | fb45550 | 2013-03-31 21:31:12 +1300 | [diff] [blame] | 465 | break; |
Chris Forbes | 6bb2cf2 | 2013-10-08 21:42:10 +1300 | [diff] [blame] | 466 | case SHADER_OPCODE_TG4_OFFSET: |
| 467 | assert(brw->gen >= 7); |
Chris Forbes | 3c98d77 | 2013-10-10 19:57:29 +1300 | [diff] [blame] | 468 | if (inst->shadow_compare) { |
| 469 | msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C; |
| 470 | } else { |
| 471 | msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO; |
| 472 | } |
Chris Forbes | 6bb2cf2 | 2013-10-08 21:42:10 +1300 | [diff] [blame] | 473 | break; |
Eric Anholt | 6034b9a | 2011-05-03 10:55:50 -0700 | [diff] [blame] | 474 | default: |
| 475 | assert(!"not reached"); |
| 476 | break; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 477 | } |
| 478 | } else { |
| 479 | switch (inst->opcode) { |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 480 | case SHADER_OPCODE_TEX: |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 481 | /* Note that G45 and older determines shadow compare and dispatch width |
| 482 | * from message length for most messages. |
| 483 | */ |
Kenneth Graunke | a303df8 | 2012-11-20 13:50:52 -0800 | [diff] [blame] | 484 | assert(dispatch_width == 8); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 485 | msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE; |
| 486 | if (inst->shadow_compare) { |
| 487 | assert(inst->mlen == 6); |
| 488 | } else { |
| 489 | assert(inst->mlen <= 4); |
| 490 | } |
| 491 | break; |
| 492 | case FS_OPCODE_TXB: |
| 493 | if (inst->shadow_compare) { |
| 494 | assert(inst->mlen == 6); |
| 495 | msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE; |
| 496 | } else { |
| 497 | assert(inst->mlen == 9); |
| 498 | msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; |
| 499 | simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; |
| 500 | } |
| 501 | break; |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 502 | case SHADER_OPCODE_TXL: |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 503 | if (inst->shadow_compare) { |
| 504 | assert(inst->mlen == 6); |
| 505 | msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE; |
| 506 | } else { |
| 507 | assert(inst->mlen == 9); |
| 508 | msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD; |
| 509 | simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; |
| 510 | } |
| 511 | break; |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 512 | case SHADER_OPCODE_TXD: |
Kenneth Graunke | 6430df3 | 2011-06-10 14:48:46 -0700 | [diff] [blame] | 513 | /* There is no sample_d_c message; comparisons are done manually */ |
Kenneth Graunke | 6c947cf | 2011-06-08 16:05:34 -0700 | [diff] [blame] | 514 | assert(inst->mlen == 7 || inst->mlen == 10); |
| 515 | msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 516 | break; |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 517 | case SHADER_OPCODE_TXF: |
Kenneth Graunke | 47b556f | 2011-09-06 16:39:01 -0700 | [diff] [blame] | 518 | assert(inst->mlen == 9); |
| 519 | msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD; |
| 520 | simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; |
| 521 | break; |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 522 | case SHADER_OPCODE_TXS: |
Kenneth Graunke | 4eeb4c1 | 2011-08-17 10:45:47 -0700 | [diff] [blame] | 523 | assert(inst->mlen == 3); |
| 524 | msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO; |
| 525 | simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; |
| 526 | break; |
Eric Anholt | 6034b9a | 2011-05-03 10:55:50 -0700 | [diff] [blame] | 527 | default: |
| 528 | assert(!"not reached"); |
| 529 | break; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 530 | } |
| 531 | } |
| 532 | assert(msg_type != -1); |
| 533 | |
| 534 | if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) { |
| 535 | rlen = 8; |
| 536 | dst = vec16(dst); |
| 537 | } |
| 538 | |
Eric Anholt | 36fbe66 | 2013-10-09 17:17:59 -0700 | [diff] [blame] | 539 | if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) { |
Eric Anholt | 746e3e3 | 2013-11-12 15:33:27 -0800 | [diff] [blame] | 540 | /* The send-from-GRF for SIMD16 texturing with a header has an extra |
Eric Anholt | 36fbe66 | 2013-10-09 17:17:59 -0700 | [diff] [blame] | 541 | * hardware register allocated to it, which we need to skip over (since |
| 542 | * our coordinates in the payload are in the even-numbered registers, |
| 543 | * and the header comes right before the first one). |
| 544 | */ |
| 545 | assert(src.file == BRW_GENERAL_REGISTER_FILE); |
| 546 | src.nr++; |
| 547 | } |
| 548 | |
Kenneth Graunke | 82bfb4b | 2012-08-04 20:33:13 -0700 | [diff] [blame] | 549 | /* Load the message header if present. If there's a texture offset, |
| 550 | * we need to set it up explicitly and load the offset bitfield. |
| 551 | * Otherwise, we can use an implied move from g0 to the first message reg. |
| 552 | */ |
Kenneth Graunke | ebfe43d | 2014-01-18 12:48:18 -0800 | [diff] [blame] | 553 | if (inst->header_present) { |
| 554 | if (brw->gen < 6 && !inst->texture_offset) { |
| 555 | /* Set up an implied move from g0 to the MRF. */ |
| 556 | src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW); |
Eric Anholt | 36fbe66 | 2013-10-09 17:17:59 -0700 | [diff] [blame] | 557 | } else { |
Kenneth Graunke | ebfe43d | 2014-01-18 12:48:18 -0800 | [diff] [blame] | 558 | struct brw_reg header_reg; |
Kenneth Graunke | 82bfb4b | 2012-08-04 20:33:13 -0700 | [diff] [blame] | 559 | |
Kenneth Graunke | ebfe43d | 2014-01-18 12:48:18 -0800 | [diff] [blame] | 560 | if (brw->gen >= 7) { |
| 561 | header_reg = src; |
| 562 | } else { |
| 563 | assert(inst->base_mrf != -1); |
| 564 | header_reg = brw_message_reg(inst->base_mrf); |
| 565 | } |
| 566 | |
Chris Forbes | b38af01 | 2013-10-13 12:20:03 +1300 | [diff] [blame] | 567 | brw_push_insn_state(p); |
| 568 | brw_set_mask_control(p, BRW_MASK_DISABLE); |
| 569 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
Kenneth Graunke | ebfe43d | 2014-01-18 12:48:18 -0800 | [diff] [blame] | 570 | /* Explicitly set up the message header by copying g0 to the MRF. */ |
| 571 | brw_MOV(p, header_reg, brw_vec8_grf(0, 0)); |
| 572 | |
| 573 | if (inst->texture_offset) { |
| 574 | /* Set the offset bits in DWord 2. */ |
| 575 | brw_MOV(p, get_element_ud(header_reg, 2), |
| 576 | brw_imm_ud(inst->texture_offset)); |
| 577 | } |
Kenneth Graunke | 6943ac0 | 2014-01-18 13:29:39 -0800 | [diff] [blame] | 578 | |
| 579 | if (inst->sampler >= 16) { |
| 580 | /* The "Sampler Index" field can only store values between 0 and 15. |
| 581 | * However, we can add an offset to the "Sampler State Pointer" |
| 582 | * field, effectively selecting a different set of 16 samplers. |
| 583 | * |
| 584 | * The "Sampler State Pointer" needs to be aligned to a 32-byte |
| 585 | * offset, and each sampler state is only 16-bytes, so we can't |
| 586 | * exclusively use the offset - we have to use both. |
| 587 | */ |
| 588 | assert(brw->is_haswell); /* field only exists on Haswell */ |
| 589 | brw_ADD(p, |
| 590 | get_element_ud(header_reg, 3), |
| 591 | get_element_ud(brw_vec8_grf(0, 0), 3), |
| 592 | brw_imm_ud(16 * (inst->sampler / 16) * |
| 593 | sizeof(gen7_sampler_state))); |
| 594 | } |
Chris Forbes | b38af01 | 2013-10-13 12:20:03 +1300 | [diff] [blame] | 595 | brw_pop_insn_state(p); |
Chris Forbes | b38af01 | 2013-10-13 12:20:03 +1300 | [diff] [blame] | 596 | } |
Kenneth Graunke | 82bfb4b | 2012-08-04 20:33:13 -0700 | [diff] [blame] | 597 | } |
| 598 | |
Chris Forbes | 6bb2cf2 | 2013-10-08 21:42:10 +1300 | [diff] [blame] | 599 | uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 || |
| 600 | inst->opcode == SHADER_OPCODE_TG4_OFFSET) |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 601 | ? prog_data->base.binding_table.gather_texture_start |
| 602 | : prog_data->base.binding_table.texture_start) + inst->sampler; |
Chris Forbes | dd4c2a5 | 2013-09-15 18:23:14 +1200 | [diff] [blame] | 603 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 604 | brw_SAMPLE(p, |
| 605 | retype(dst, BRW_REGISTER_TYPE_UW), |
| 606 | inst->base_mrf, |
| 607 | src, |
Chris Forbes | dd4c2a5 | 2013-09-15 18:23:14 +1200 | [diff] [blame] | 608 | surface_index, |
Kenneth Graunke | 6943ac0 | 2014-01-18 13:29:39 -0800 | [diff] [blame] | 609 | inst->sampler % 16, |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 610 | msg_type, |
| 611 | rlen, |
| 612 | inst->mlen, |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 613 | inst->header_present, |
Eric Anholt | 7e84a64 | 2011-11-09 16:07:57 -0800 | [diff] [blame] | 614 | simd_mode, |
| 615 | return_format); |
Kenneth Graunke | 6d89bc8 | 2013-08-14 19:49:33 -0700 | [diff] [blame] | 616 | |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 617 | brw_mark_surface_used(&prog_data->base, surface_index); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | |
| 621 | /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input |
| 622 | * looking like: |
| 623 | * |
| 624 | * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br |
| 625 | * |
Chia-I Wu | 848c0e7 | 2013-09-12 13:00:52 +0800 | [diff] [blame] | 626 | * Ideally, we want to produce: |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 627 | * |
| 628 | * DDX DDY |
| 629 | * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl) |
| 630 | * (ss0.tr - ss0.tl) (ss0.tr - ss0.br) |
| 631 | * (ss0.br - ss0.bl) (ss0.tl - ss0.bl) |
| 632 | * (ss0.br - ss0.bl) (ss0.tr - ss0.br) |
| 633 | * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl) |
| 634 | * (ss1.tr - ss1.tl) (ss1.tr - ss1.br) |
| 635 | * (ss1.br - ss1.bl) (ss1.tl - ss1.bl) |
| 636 | * (ss1.br - ss1.bl) (ss1.tr - ss1.br) |
| 637 | * |
| 638 | * and add another set of two more subspans if in 16-pixel dispatch mode. |
| 639 | * |
| 640 | * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result |
| 641 | * for each pair, and vertstride = 2 jumps us 2 elements after processing a |
Chia-I Wu | 848c0e7 | 2013-09-12 13:00:52 +0800 | [diff] [blame] | 642 | * pair. But the ideal approximation may impose a huge performance cost on |
| 643 | * sample_d. On at least Haswell, sample_d instruction does some |
| 644 | * optimizations if the same LOD is used for all pixels in the subspan. |
| 645 | * |
Paul Berry | 800610f | 2013-09-20 09:04:31 -0700 | [diff] [blame] | 646 | * For DDY, we need to use ALIGN16 mode since it's capable of doing the |
| 647 | * appropriate swizzling. |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 648 | */ |
| 649 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 650 | fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 651 | { |
Chia-I Wu | 848c0e7 | 2013-09-12 13:00:52 +0800 | [diff] [blame] | 652 | unsigned vstride, width; |
| 653 | |
Kenneth Graunke | c96fdeb | 2014-05-14 00:24:50 -0700 | [diff] [blame] | 654 | if (key->high_quality_derivatives) { |
Chia-I Wu | 848c0e7 | 2013-09-12 13:00:52 +0800 | [diff] [blame] | 655 | /* produce accurate derivatives */ |
| 656 | vstride = BRW_VERTICAL_STRIDE_2; |
| 657 | width = BRW_WIDTH_2; |
| 658 | } |
| 659 | else { |
| 660 | /* replicate the derivative at the top-left pixel to other pixels */ |
| 661 | vstride = BRW_VERTICAL_STRIDE_4; |
| 662 | width = BRW_WIDTH_4; |
| 663 | } |
| 664 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 665 | struct brw_reg src0 = brw_reg(src.file, src.nr, 1, |
| 666 | BRW_REGISTER_TYPE_F, |
Chia-I Wu | 848c0e7 | 2013-09-12 13:00:52 +0800 | [diff] [blame] | 667 | vstride, |
| 668 | width, |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 669 | BRW_HORIZONTAL_STRIDE_0, |
| 670 | BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); |
| 671 | struct brw_reg src1 = brw_reg(src.file, src.nr, 0, |
| 672 | BRW_REGISTER_TYPE_F, |
Chia-I Wu | 848c0e7 | 2013-09-12 13:00:52 +0800 | [diff] [blame] | 673 | vstride, |
| 674 | width, |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 675 | BRW_HORIZONTAL_STRIDE_0, |
| 676 | BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); |
| 677 | brw_ADD(p, dst, src0, negate(src1)); |
| 678 | } |
| 679 | |
Paul Berry | 82d2596 | 2012-06-20 13:40:45 -0700 | [diff] [blame] | 680 | /* The negate_value boolean is used to negate the derivative computation for |
| 681 | * FBOs, since they place the origin at the upper left instead of the lower |
| 682 | * left. |
| 683 | */ |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 684 | void |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 685 | fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src, |
Paul Berry | 82d2596 | 2012-06-20 13:40:45 -0700 | [diff] [blame] | 686 | bool negate_value) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 687 | { |
Kenneth Graunke | c96fdeb | 2014-05-14 00:24:50 -0700 | [diff] [blame] | 688 | if (key->high_quality_derivatives) { |
Paul Berry | 4df5617 | 2013-10-22 05:56:37 -0700 | [diff] [blame] | 689 | /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register |
| 690 | * Region Restrictions): |
| 691 | * |
| 692 | * In Align16 access mode, SIMD16 is not allowed for DW operations |
| 693 | * and SIMD8 is not allowed for DF operations. |
| 694 | * |
| 695 | * In this context, "DW operations" means "operations acting on 32-bit |
| 696 | * values", so it includes operations on floats. |
| 697 | * |
| 698 | * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3 |
| 699 | * (Instruction Compression -> Rules and Restrictions): |
| 700 | * |
| 701 | * A compressed instruction must be in Align1 access mode. Align16 |
| 702 | * mode instructions cannot be compressed. |
| 703 | * |
| 704 | * Similar text exists in the g45 PRM. |
| 705 | * |
| 706 | * On these platforms, if we're building a SIMD16 shader, we need to |
| 707 | * manually unroll to a pair of SIMD8 instructions. |
| 708 | */ |
| 709 | bool unroll_to_simd8 = |
| 710 | (dispatch_width == 16 && |
| 711 | (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell))); |
| 712 | |
Paul Berry | 800610f | 2013-09-20 09:04:31 -0700 | [diff] [blame] | 713 | /* produce accurate derivatives */ |
| 714 | struct brw_reg src0 = brw_reg(src.file, src.nr, 0, |
| 715 | BRW_REGISTER_TYPE_F, |
| 716 | BRW_VERTICAL_STRIDE_4, |
| 717 | BRW_WIDTH_4, |
| 718 | BRW_HORIZONTAL_STRIDE_1, |
| 719 | BRW_SWIZZLE_XYXY, WRITEMASK_XYZW); |
| 720 | struct brw_reg src1 = brw_reg(src.file, src.nr, 0, |
| 721 | BRW_REGISTER_TYPE_F, |
| 722 | BRW_VERTICAL_STRIDE_4, |
| 723 | BRW_WIDTH_4, |
| 724 | BRW_HORIZONTAL_STRIDE_1, |
| 725 | BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW); |
| 726 | brw_push_insn_state(p); |
| 727 | brw_set_access_mode(p, BRW_ALIGN_16); |
Paul Berry | 4df5617 | 2013-10-22 05:56:37 -0700 | [diff] [blame] | 728 | if (unroll_to_simd8) |
| 729 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
Paul Berry | 800610f | 2013-09-20 09:04:31 -0700 | [diff] [blame] | 730 | if (negate_value) |
| 731 | brw_ADD(p, dst, src1, negate(src0)); |
| 732 | else |
| 733 | brw_ADD(p, dst, src0, negate(src1)); |
Paul Berry | 4df5617 | 2013-10-22 05:56:37 -0700 | [diff] [blame] | 734 | if (unroll_to_simd8) { |
Paul Berry | 800610f | 2013-09-20 09:04:31 -0700 | [diff] [blame] | 735 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |
| 736 | src0 = sechalf(src0); |
| 737 | src1 = sechalf(src1); |
| 738 | dst = sechalf(dst); |
| 739 | if (negate_value) |
| 740 | brw_ADD(p, dst, src1, negate(src0)); |
| 741 | else |
| 742 | brw_ADD(p, dst, src0, negate(src1)); |
| 743 | } |
| 744 | brw_pop_insn_state(p); |
| 745 | } else { |
| 746 | /* replicate the derivative at the top-left pixel to other pixels */ |
| 747 | struct brw_reg src0 = brw_reg(src.file, src.nr, 0, |
| 748 | BRW_REGISTER_TYPE_F, |
| 749 | BRW_VERTICAL_STRIDE_4, |
| 750 | BRW_WIDTH_4, |
| 751 | BRW_HORIZONTAL_STRIDE_0, |
| 752 | BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); |
| 753 | struct brw_reg src1 = brw_reg(src.file, src.nr, 2, |
| 754 | BRW_REGISTER_TYPE_F, |
| 755 | BRW_VERTICAL_STRIDE_4, |
| 756 | BRW_WIDTH_4, |
| 757 | BRW_HORIZONTAL_STRIDE_0, |
| 758 | BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); |
| 759 | if (negate_value) |
| 760 | brw_ADD(p, dst, src1, negate(src0)); |
| 761 | else |
| 762 | brw_ADD(p, dst, src0, negate(src1)); |
| 763 | } |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 764 | } |
| 765 | |
| 766 | void |
Eric Anholt | beafced | 2012-12-06 10:15:08 -0800 | [diff] [blame] | 767 | fs_generator::generate_discard_jump(fs_inst *inst) |
| 768 | { |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 769 | assert(brw->gen >= 6); |
Eric Anholt | beafced | 2012-12-06 10:15:08 -0800 | [diff] [blame] | 770 | |
| 771 | /* This HALT will be patched up at FB write time to point UIP at the end of |
| 772 | * the program, and at brw_uip_jip() JIP will be set to the end of the |
| 773 | * current block (or the program). |
| 774 | */ |
| 775 | this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn)); |
| 776 | |
| 777 | brw_push_insn_state(p); |
| 778 | brw_set_mask_control(p, BRW_MASK_DISABLE); |
| 779 | gen6_HALT(p); |
| 780 | brw_pop_insn_state(p); |
| 781 | } |
| 782 | |
| 783 | void |
Eric Anholt | 6032261 | 2013-10-16 11:45:06 -0700 | [diff] [blame] | 784 | fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 785 | { |
| 786 | assert(inst->mlen != 0); |
| 787 | |
| 788 | brw_MOV(p, |
| 789 | retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD), |
| 790 | retype(src, BRW_REGISTER_TYPE_UD)); |
Eric Anholt | 0e20051 | 2013-10-16 12:16:51 -0700 | [diff] [blame] | 791 | brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf), |
Eric Anholt | 7c90947 | 2013-11-04 22:56:33 -0800 | [diff] [blame] | 792 | dispatch_width / 8, inst->offset); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 793 | } |
| 794 | |
| 795 | void |
Eric Anholt | 6032261 | 2013-10-16 11:45:06 -0700 | [diff] [blame] | 796 | fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 797 | { |
| 798 | assert(inst->mlen != 0); |
| 799 | |
Eric Anholt | 0e20051 | 2013-10-16 12:16:51 -0700 | [diff] [blame] | 800 | brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf), |
| 801 | dispatch_width / 8, inst->offset); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 802 | } |
| 803 | |
| 804 | void |
Eric Anholt | 8dfc9f0 | 2013-10-16 11:51:22 -0700 | [diff] [blame] | 805 | fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst) |
| 806 | { |
| 807 | gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset); |
| 808 | } |
| 809 | |
| 810 | void |
Eric Anholt | 29340d0 | 2012-11-07 10:42:34 -0800 | [diff] [blame] | 811 | fs_generator::generate_uniform_pull_constant_load(fs_inst *inst, |
| 812 | struct brw_reg dst, |
| 813 | struct brw_reg index, |
| 814 | struct brw_reg offset) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 815 | { |
| 816 | assert(inst->mlen != 0); |
| 817 | |
Eric Anholt | 454dc83 | 2012-06-20 15:41:14 -0700 | [diff] [blame] | 818 | assert(index.file == BRW_IMMEDIATE_VALUE && |
| 819 | index.type == BRW_REGISTER_TYPE_UD); |
| 820 | uint32_t surf_index = index.dw1.ud; |
| 821 | |
| 822 | assert(offset.file == BRW_IMMEDIATE_VALUE && |
| 823 | offset.type == BRW_REGISTER_TYPE_UD); |
| 824 | uint32_t read_offset = offset.dw1.ud; |
| 825 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 826 | brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf), |
Eric Anholt | 454dc83 | 2012-06-20 15:41:14 -0700 | [diff] [blame] | 827 | read_offset, surf_index); |
Kenneth Graunke | 6d89bc8 | 2013-08-14 19:49:33 -0700 | [diff] [blame] | 828 | |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 829 | brw_mark_surface_used(&prog_data->base, surf_index); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 830 | } |
| 831 | |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 832 | void |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 833 | fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst, |
| 834 | struct brw_reg dst, |
| 835 | struct brw_reg index, |
| 836 | struct brw_reg offset) |
| 837 | { |
| 838 | assert(inst->mlen == 0); |
| 839 | |
| 840 | assert(index.file == BRW_IMMEDIATE_VALUE && |
| 841 | index.type == BRW_REGISTER_TYPE_UD); |
| 842 | uint32_t surf_index = index.dw1.ud; |
| 843 | |
| 844 | assert(offset.file == BRW_GENERAL_REGISTER_FILE); |
Eric Anholt | 4c1fdae | 2013-03-06 14:47:22 -0800 | [diff] [blame] | 845 | /* Reference just the dword we need, to avoid angering validate_reg(). */ |
| 846 | offset = brw_vec1_grf(offset.nr, 0); |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 847 | |
| 848 | brw_push_insn_state(p); |
| 849 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 850 | brw_set_mask_control(p, BRW_MASK_DISABLE); |
| 851 | struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); |
| 852 | brw_pop_insn_state(p); |
| 853 | |
Eric Anholt | 4c1fdae | 2013-03-06 14:47:22 -0800 | [diff] [blame] | 854 | /* We use the SIMD4x2 mode because we want to end up with 4 components in |
| 855 | * the destination loaded consecutively from the same offset (which appears |
| 856 | * in the first component, and the rest are ignored). |
| 857 | */ |
| 858 | dst.width = BRW_WIDTH_4; |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 859 | brw_set_dest(p, send, dst); |
| 860 | brw_set_src0(p, send, offset); |
Eric Anholt | 4c1fdae | 2013-03-06 14:47:22 -0800 | [diff] [blame] | 861 | brw_set_sampler_message(p, send, |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 862 | surf_index, |
Eric Anholt | 4c1fdae | 2013-03-06 14:47:22 -0800 | [diff] [blame] | 863 | 0, /* LD message ignores sampler unit */ |
| 864 | GEN5_SAMPLER_MESSAGE_SAMPLE_LD, |
| 865 | 1, /* rlen */ |
| 866 | 1, /* mlen */ |
| 867 | false, /* no header */ |
| 868 | BRW_SAMPLER_SIMD_MODE_SIMD4X2, |
| 869 | 0); |
Kenneth Graunke | 6d89bc8 | 2013-08-14 19:49:33 -0700 | [diff] [blame] | 870 | |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 871 | brw_mark_surface_used(&prog_data->base, surf_index); |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 872 | } |
| 873 | |
| 874 | void |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 875 | fs_generator::generate_varying_pull_constant_load(fs_inst *inst, |
| 876 | struct brw_reg dst, |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 877 | struct brw_reg index, |
| 878 | struct brw_reg offset) |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 879 | { |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 880 | assert(brw->gen < 7); /* Should use the gen7 variant. */ |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 881 | assert(inst->header_present); |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 882 | assert(inst->mlen); |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 883 | |
| 884 | assert(index.file == BRW_IMMEDIATE_VALUE && |
| 885 | index.type == BRW_REGISTER_TYPE_UD); |
| 886 | uint32_t surf_index = index.dw1.ud; |
| 887 | |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 888 | uint32_t simd_mode, rlen, msg_type; |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 889 | if (dispatch_width == 16) { |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 890 | simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; |
| 891 | rlen = 8; |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 892 | } else { |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 893 | simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; |
| 894 | rlen = 4; |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 895 | } |
| 896 | |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 897 | if (brw->gen >= 5) |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 898 | msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; |
| 899 | else { |
| 900 | /* We always use the SIMD16 message so that we only have to load U, and |
| 901 | * not V or R. |
| 902 | */ |
| 903 | msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD; |
| 904 | assert(inst->mlen == 3); |
| 905 | assert(inst->regs_written == 8); |
| 906 | rlen = 8; |
| 907 | simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; |
| 908 | } |
| 909 | |
| 910 | struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1), |
| 911 | BRW_REGISTER_TYPE_D); |
| 912 | brw_MOV(p, offset_mrf, offset); |
| 913 | |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 914 | struct brw_reg header = brw_vec8_grf(0, 0); |
| 915 | gen6_resolve_implied_move(p, &header, inst->base_mrf); |
| 916 | |
| 917 | struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 918 | send->header.compression_control = BRW_COMPRESSION_NONE; |
Kenneth Graunke | 71846a9 | 2014-04-16 20:15:23 -0700 | [diff] [blame] | 919 | brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW)); |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 920 | brw_set_src0(p, send, header); |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 921 | if (brw->gen < 6) |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 922 | send->header.destreg__conditionalmod = inst->base_mrf; |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 923 | |
| 924 | /* Our surface is set up as floats, regardless of what actual data is |
| 925 | * stored in it. |
| 926 | */ |
| 927 | uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; |
| 928 | brw_set_sampler_message(p, send, |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 929 | surf_index, |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 930 | 0, /* sampler (unused) */ |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 931 | msg_type, |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 932 | rlen, |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 933 | inst->mlen, |
| 934 | inst->header_present, |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 935 | simd_mode, |
| 936 | return_format); |
Kenneth Graunke | 6d89bc8 | 2013-08-14 19:49:33 -0700 | [diff] [blame] | 937 | |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 938 | brw_mark_surface_used(&prog_data->base, surf_index); |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 939 | } |
| 940 | |
| 941 | void |
| 942 | fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst, |
| 943 | struct brw_reg dst, |
| 944 | struct brw_reg index, |
| 945 | struct brw_reg offset) |
| 946 | { |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 947 | assert(brw->gen >= 7); |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 948 | /* Varying-offset pull constant loads are treated as a normal expression on |
| 949 | * gen7, so the fact that it's a send message is hidden at the IR level. |
| 950 | */ |
| 951 | assert(!inst->header_present); |
| 952 | assert(!inst->mlen); |
| 953 | |
| 954 | assert(index.file == BRW_IMMEDIATE_VALUE && |
| 955 | index.type == BRW_REGISTER_TYPE_UD); |
| 956 | uint32_t surf_index = index.dw1.ud; |
| 957 | |
Eric Anholt | dca5fc1 | 2013-03-13 14:48:55 -0700 | [diff] [blame] | 958 | uint32_t simd_mode, rlen, mlen; |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 959 | if (dispatch_width == 16) { |
Eric Anholt | dca5fc1 | 2013-03-13 14:48:55 -0700 | [diff] [blame] | 960 | mlen = 2; |
| 961 | rlen = 8; |
| 962 | simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 963 | } else { |
Eric Anholt | dca5fc1 | 2013-03-13 14:48:55 -0700 | [diff] [blame] | 964 | mlen = 1; |
| 965 | rlen = 4; |
| 966 | simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 967 | } |
| 968 | |
| 969 | struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); |
| 970 | brw_set_dest(p, send, dst); |
| 971 | brw_set_src0(p, send, offset); |
Eric Anholt | dca5fc1 | 2013-03-13 14:48:55 -0700 | [diff] [blame] | 972 | brw_set_sampler_message(p, send, |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 973 | surf_index, |
Eric Anholt | dca5fc1 | 2013-03-13 14:48:55 -0700 | [diff] [blame] | 974 | 0, /* LD message ignores sampler unit */ |
| 975 | GEN5_SAMPLER_MESSAGE_SAMPLE_LD, |
| 976 | rlen, |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 977 | mlen, |
Eric Anholt | dca5fc1 | 2013-03-13 14:48:55 -0700 | [diff] [blame] | 978 | false, /* no header */ |
| 979 | simd_mode, |
| 980 | 0); |
Kenneth Graunke | 6d89bc8 | 2013-08-14 19:49:33 -0700 | [diff] [blame] | 981 | |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 982 | brw_mark_surface_used(&prog_data->base, surf_index); |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 983 | } |
Paul Berry | 3f929ef | 2012-06-18 14:50:04 -0700 | [diff] [blame] | 984 | |
| 985 | /** |
| 986 | * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred |
| 987 | * into the flags register (f0.0). |
| 988 | * |
| 989 | * Used only on Gen6 and above. |
| 990 | */ |
| 991 | void |
Eric Anholt | b278f65 | 2012-12-06 10:36:11 -0800 | [diff] [blame] | 992 | fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst) |
Paul Berry | 3f929ef | 2012-06-18 14:50:04 -0700 | [diff] [blame] | 993 | { |
Eric Anholt | b278f65 | 2012-12-06 10:36:11 -0800 | [diff] [blame] | 994 | struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg); |
Eric Anholt | d501649 | 2012-12-06 12:15:13 -0800 | [diff] [blame] | 995 | struct brw_reg dispatch_mask; |
Paul Berry | 3f929ef | 2012-06-18 14:50:04 -0700 | [diff] [blame] | 996 | |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 997 | if (brw->gen >= 6) |
Eric Anholt | d501649 | 2012-12-06 12:15:13 -0800 | [diff] [blame] | 998 | dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW); |
| 999 | else |
| 1000 | dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); |
| 1001 | |
Paul Berry | 3f929ef | 2012-06-18 14:50:04 -0700 | [diff] [blame] | 1002 | brw_push_insn_state(p); |
| 1003 | brw_set_mask_control(p, BRW_MASK_DISABLE); |
Eric Anholt | d501649 | 2012-12-06 12:15:13 -0800 | [diff] [blame] | 1004 | brw_MOV(p, flags, dispatch_mask); |
Paul Berry | 3f929ef | 2012-06-18 14:50:04 -0700 | [diff] [blame] | 1005 | brw_pop_insn_state(p); |
| 1006 | } |
| 1007 | |
| 1008 | |
Eric Anholt | a3b8c5e | 2011-11-23 10:13:39 -0800 | [diff] [blame] | 1009 | static uint32_t brw_file_from_reg(fs_reg *reg) |
| 1010 | { |
| 1011 | switch (reg->file) { |
Eric Anholt | a3b8c5e | 2011-11-23 10:13:39 -0800 | [diff] [blame] | 1012 | case GRF: |
| 1013 | return BRW_GENERAL_REGISTER_FILE; |
| 1014 | case MRF: |
| 1015 | return BRW_MESSAGE_REGISTER_FILE; |
| 1016 | case IMM: |
| 1017 | return BRW_IMMEDIATE_VALUE; |
| 1018 | default: |
| 1019 | assert(!"not reached"); |
| 1020 | return BRW_GENERAL_REGISTER_FILE; |
| 1021 | } |
| 1022 | } |
| 1023 | |
Kenneth Graunke | 7b4b94a | 2013-11-01 13:29:37 -0700 | [diff] [blame] | 1024 | struct brw_reg |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1025 | brw_reg_from_fs_reg(fs_reg *reg) |
| 1026 | { |
| 1027 | struct brw_reg brw_reg; |
| 1028 | |
| 1029 | switch (reg->file) { |
| 1030 | case GRF: |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1031 | case MRF: |
Francisco Jerez | 019bf6e | 2014-01-15 22:21:30 +0100 | [diff] [blame] | 1032 | if (reg->stride == 0) { |
| 1033 | brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1034 | } else { |
Francisco Jerez | 756d37b | 2013-12-08 04:57:35 +0100 | [diff] [blame] | 1035 | brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0); |
| 1036 | brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1037 | } |
Francisco Jerez | 756d37b | 2013-12-08 04:57:35 +0100 | [diff] [blame] | 1038 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1039 | brw_reg = retype(brw_reg, reg->type); |
Francisco Jerez | 4c7206b | 2013-12-08 04:57:08 +0100 | [diff] [blame] | 1040 | brw_reg = byte_offset(brw_reg, reg->subreg_offset); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1041 | break; |
| 1042 | case IMM: |
| 1043 | switch (reg->type) { |
| 1044 | case BRW_REGISTER_TYPE_F: |
| 1045 | brw_reg = brw_imm_f(reg->imm.f); |
| 1046 | break; |
| 1047 | case BRW_REGISTER_TYPE_D: |
| 1048 | brw_reg = brw_imm_d(reg->imm.i); |
| 1049 | break; |
| 1050 | case BRW_REGISTER_TYPE_UD: |
| 1051 | brw_reg = brw_imm_ud(reg->imm.u); |
| 1052 | break; |
| 1053 | default: |
| 1054 | assert(!"not reached"); |
| 1055 | brw_reg = brw_null_reg(); |
| 1056 | break; |
| 1057 | } |
| 1058 | break; |
Eric Anholt | ab04f3b | 2013-04-29 16:05:05 -0700 | [diff] [blame] | 1059 | case HW_REG: |
Francisco Jerez | 42b226e | 2014-02-19 15:21:07 +0100 | [diff] [blame] | 1060 | assert(reg->type == reg->fixed_hw_reg.type); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1061 | brw_reg = reg->fixed_hw_reg; |
| 1062 | break; |
| 1063 | case BAD_FILE: |
| 1064 | /* Probably unused. */ |
| 1065 | brw_reg = brw_null_reg(); |
| 1066 | break; |
| 1067 | case UNIFORM: |
| 1068 | assert(!"not reached"); |
| 1069 | brw_reg = brw_null_reg(); |
| 1070 | break; |
| 1071 | default: |
| 1072 | assert(!"not reached"); |
| 1073 | brw_reg = brw_null_reg(); |
| 1074 | break; |
| 1075 | } |
| 1076 | if (reg->abs) |
| 1077 | brw_reg = brw_abs(brw_reg); |
| 1078 | if (reg->negate) |
| 1079 | brw_reg = negate(brw_reg); |
| 1080 | |
| 1081 | return brw_reg; |
| 1082 | } |
| 1083 | |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 1084 | /** |
Eric Anholt | 4c1fdae | 2013-03-06 14:47:22 -0800 | [diff] [blame] | 1085 | * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant |
| 1086 | * sampler LD messages. |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 1087 | * |
Eric Anholt | 4c1fdae | 2013-03-06 14:47:22 -0800 | [diff] [blame] | 1088 | * We don't want to bake it into the send message's code generation because |
| 1089 | * that means we don't get a chance to schedule the instructions. |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 1090 | */ |
| 1091 | void |
Eric Anholt | 4c1fdae | 2013-03-06 14:47:22 -0800 | [diff] [blame] | 1092 | fs_generator::generate_set_simd4x2_offset(fs_inst *inst, |
| 1093 | struct brw_reg dst, |
| 1094 | struct brw_reg value) |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 1095 | { |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 1096 | assert(value.file == BRW_IMMEDIATE_VALUE); |
| 1097 | |
| 1098 | brw_push_insn_state(p); |
| 1099 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 1100 | brw_set_mask_control(p, BRW_MASK_DISABLE); |
Eric Anholt | 4c1fdae | 2013-03-06 14:47:22 -0800 | [diff] [blame] | 1101 | brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value); |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 1102 | brw_pop_insn_state(p); |
| 1103 | } |
| 1104 | |
Anuj Phogat | e26bdf5 | 2013-10-24 16:21:13 -0700 | [diff] [blame] | 1105 | /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0 |
| 1106 | * (when mask is passed as a uniform) of register mask before moving it |
| 1107 | * to register dst. |
| 1108 | */ |
| 1109 | void |
| 1110 | fs_generator::generate_set_omask(fs_inst *inst, |
| 1111 | struct brw_reg dst, |
| 1112 | struct brw_reg mask) |
| 1113 | { |
| 1114 | bool stride_8_8_1 = |
| 1115 | (mask.vstride == BRW_VERTICAL_STRIDE_8 && |
| 1116 | mask.width == BRW_WIDTH_8 && |
| 1117 | mask.hstride == BRW_HORIZONTAL_STRIDE_1); |
| 1118 | |
| 1119 | bool stride_0_1_0 = |
| 1120 | (mask.vstride == BRW_VERTICAL_STRIDE_0 && |
| 1121 | mask.width == BRW_WIDTH_1 && |
| 1122 | mask.hstride == BRW_HORIZONTAL_STRIDE_0); |
| 1123 | |
| 1124 | assert(stride_8_8_1 || stride_0_1_0); |
| 1125 | assert(dst.type == BRW_REGISTER_TYPE_UW); |
| 1126 | |
| 1127 | if (dispatch_width == 16) |
| 1128 | dst = vec16(dst); |
| 1129 | brw_push_insn_state(p); |
| 1130 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 1131 | brw_set_mask_control(p, BRW_MASK_DISABLE); |
| 1132 | |
| 1133 | if (stride_8_8_1) { |
Kenneth Graunke | e95a4ed | 2014-02-10 15:37:09 -0800 | [diff] [blame] | 1134 | brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type)); |
Anuj Phogat | e26bdf5 | 2013-10-24 16:21:13 -0700 | [diff] [blame] | 1135 | } else if (stride_0_1_0) { |
Kenneth Graunke | e95a4ed | 2014-02-10 15:37:09 -0800 | [diff] [blame] | 1136 | brw_MOV(p, dst, retype(mask, dst.type)); |
Anuj Phogat | e26bdf5 | 2013-10-24 16:21:13 -0700 | [diff] [blame] | 1137 | } |
| 1138 | brw_pop_insn_state(p); |
| 1139 | } |
| 1140 | |
Anuj Phogat | e12bbb5 | 2013-10-24 16:17:08 -0700 | [diff] [blame] | 1141 | /* Sets vstride=1, width=4, hstride=0 of register src1 during |
| 1142 | * the ADD instruction. |
| 1143 | */ |
| 1144 | void |
| 1145 | fs_generator::generate_set_sample_id(fs_inst *inst, |
| 1146 | struct brw_reg dst, |
| 1147 | struct brw_reg src0, |
| 1148 | struct brw_reg src1) |
| 1149 | { |
| 1150 | assert(dst.type == BRW_REGISTER_TYPE_D || |
| 1151 | dst.type == BRW_REGISTER_TYPE_UD); |
| 1152 | assert(src0.type == BRW_REGISTER_TYPE_D || |
| 1153 | src0.type == BRW_REGISTER_TYPE_UD); |
| 1154 | |
| 1155 | brw_push_insn_state(p); |
| 1156 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 1157 | brw_set_mask_control(p, BRW_MASK_DISABLE); |
Kenneth Graunke | f948ad2 | 2014-02-10 14:46:49 -0800 | [diff] [blame] | 1158 | struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW); |
Anuj Phogat | e12bbb5 | 2013-10-24 16:17:08 -0700 | [diff] [blame] | 1159 | brw_ADD(p, dst, src0, reg); |
| 1160 | if (dispatch_width == 16) |
| 1161 | brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2)); |
| 1162 | brw_pop_insn_state(p); |
| 1163 | } |
| 1164 | |
Chad Versace | 20dfa50 | 2013-01-09 11:46:42 -0800 | [diff] [blame] | 1165 | /** |
| 1166 | * Change the register's data type from UD to W, doubling the strides in order |
| 1167 | * to compensate for halving the data type width. |
| 1168 | */ |
| 1169 | static struct brw_reg |
| 1170 | ud_reg_to_w(struct brw_reg r) |
| 1171 | { |
| 1172 | assert(r.type == BRW_REGISTER_TYPE_UD); |
| 1173 | r.type = BRW_REGISTER_TYPE_W; |
| 1174 | |
| 1175 | /* The BRW_*_STRIDE enums are defined so that incrementing the field |
| 1176 | * doubles the real stride. |
| 1177 | */ |
| 1178 | if (r.hstride != 0) |
| 1179 | ++r.hstride; |
| 1180 | if (r.vstride != 0) |
| 1181 | ++r.vstride; |
| 1182 | |
| 1183 | return r; |
| 1184 | } |
| 1185 | |
| 1186 | void |
| 1187 | fs_generator::generate_pack_half_2x16_split(fs_inst *inst, |
| 1188 | struct brw_reg dst, |
| 1189 | struct brw_reg x, |
| 1190 | struct brw_reg y) |
| 1191 | { |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 1192 | assert(brw->gen >= 7); |
Chad Versace | 20dfa50 | 2013-01-09 11:46:42 -0800 | [diff] [blame] | 1193 | assert(dst.type == BRW_REGISTER_TYPE_UD); |
Vinson Lee | 1559994 | 2013-01-26 08:27:50 +0100 | [diff] [blame] | 1194 | assert(x.type == BRW_REGISTER_TYPE_F); |
| 1195 | assert(y.type == BRW_REGISTER_TYPE_F); |
Chad Versace | 20dfa50 | 2013-01-09 11:46:42 -0800 | [diff] [blame] | 1196 | |
| 1197 | /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16: |
| 1198 | * |
| 1199 | * Because this instruction does not have a 16-bit floating-point type, |
| 1200 | * the destination data type must be Word (W). |
| 1201 | * |
| 1202 | * The destination must be DWord-aligned and specify a horizontal stride |
| 1203 | * (HorzStride) of 2. The 16-bit result is stored in the lower word of |
| 1204 | * each destination channel and the upper word is not modified. |
| 1205 | */ |
| 1206 | struct brw_reg dst_w = ud_reg_to_w(dst); |
| 1207 | |
| 1208 | /* Give each 32-bit channel of dst the form below , where "." means |
| 1209 | * unchanged. |
| 1210 | * 0x....hhhh |
| 1211 | */ |
| 1212 | brw_F32TO16(p, dst_w, y); |
| 1213 | |
| 1214 | /* Now the form: |
| 1215 | * 0xhhhh0000 |
| 1216 | */ |
| 1217 | brw_SHL(p, dst, dst, brw_imm_ud(16u)); |
| 1218 | |
| 1219 | /* And, finally the form of packHalf2x16's output: |
| 1220 | * 0xhhhhllll |
| 1221 | */ |
| 1222 | brw_F32TO16(p, dst_w, x); |
| 1223 | } |
| 1224 | |
| 1225 | void |
| 1226 | fs_generator::generate_unpack_half_2x16_split(fs_inst *inst, |
| 1227 | struct brw_reg dst, |
| 1228 | struct brw_reg src) |
| 1229 | { |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 1230 | assert(brw->gen >= 7); |
Chad Versace | 20dfa50 | 2013-01-09 11:46:42 -0800 | [diff] [blame] | 1231 | assert(dst.type == BRW_REGISTER_TYPE_F); |
| 1232 | assert(src.type == BRW_REGISTER_TYPE_UD); |
| 1233 | |
| 1234 | /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32: |
| 1235 | * |
| 1236 | * Because this instruction does not have a 16-bit floating-point type, |
| 1237 | * the source data type must be Word (W). The destination type must be |
| 1238 | * F (Float). |
| 1239 | */ |
| 1240 | struct brw_reg src_w = ud_reg_to_w(src); |
| 1241 | |
| 1242 | /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll. |
| 1243 | * For the Y case, we wish to access only the upper word; therefore |
| 1244 | * a 16-bit subregister offset is needed. |
| 1245 | */ |
| 1246 | assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X || |
| 1247 | inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y); |
| 1248 | if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y) |
Chad Versace | 0974031 | 2013-01-24 21:48:40 -0800 | [diff] [blame] | 1249 | src_w.subnr += 2; |
Chad Versace | 20dfa50 | 2013-01-09 11:46:42 -0800 | [diff] [blame] | 1250 | |
| 1251 | brw_F16TO32(p, dst, src_w); |
| 1252 | } |
| 1253 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1254 | void |
Eric Anholt | 5c5218e | 2013-03-19 15:28:11 -0700 | [diff] [blame] | 1255 | fs_generator::generate_shader_time_add(fs_inst *inst, |
| 1256 | struct brw_reg payload, |
| 1257 | struct brw_reg offset, |
| 1258 | struct brw_reg value) |
| 1259 | { |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 1260 | assert(brw->gen >= 7); |
Eric Anholt | 5c5218e | 2013-03-19 15:28:11 -0700 | [diff] [blame] | 1261 | brw_push_insn_state(p); |
| 1262 | brw_set_mask_control(p, true); |
| 1263 | |
| 1264 | assert(payload.file == BRW_GENERAL_REGISTER_FILE); |
| 1265 | struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0), |
| 1266 | offset.type); |
| 1267 | struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0), |
| 1268 | value.type); |
| 1269 | |
| 1270 | assert(offset.file == BRW_IMMEDIATE_VALUE); |
| 1271 | if (value.file == BRW_GENERAL_REGISTER_FILE) { |
| 1272 | value.width = BRW_WIDTH_1; |
| 1273 | value.hstride = BRW_HORIZONTAL_STRIDE_0; |
| 1274 | value.vstride = BRW_VERTICAL_STRIDE_0; |
| 1275 | } else { |
| 1276 | assert(value.file == BRW_IMMEDIATE_VALUE); |
| 1277 | } |
| 1278 | |
| 1279 | /* Trying to deal with setup of the params from the IR is crazy in the FS8 |
| 1280 | * case, and we don't really care about squeezing every bit of performance |
| 1281 | * out of this path, so we just emit the MOVs from here. |
| 1282 | */ |
| 1283 | brw_MOV(p, payload_offset, offset); |
| 1284 | brw_MOV(p, payload_value, value); |
Eric Anholt | 3c9dc2d | 2013-10-02 14:07:40 -0700 | [diff] [blame] | 1285 | brw_shader_time_add(p, payload, |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 1286 | prog_data->base.binding_table.shader_time_start); |
Eric Anholt | 5c5218e | 2013-03-19 15:28:11 -0700 | [diff] [blame] | 1287 | brw_pop_insn_state(p); |
Kenneth Graunke | 6d89bc8 | 2013-08-14 19:49:33 -0700 | [diff] [blame] | 1288 | |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 1289 | brw_mark_surface_used(&prog_data->base, |
| 1290 | prog_data->base.binding_table.shader_time_start); |
Eric Anholt | 5c5218e | 2013-03-19 15:28:11 -0700 | [diff] [blame] | 1291 | } |
| 1292 | |
| 1293 | void |
Francisco Jerez | cfaaa9b | 2013-09-11 14:01:50 -0700 | [diff] [blame] | 1294 | fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst, |
| 1295 | struct brw_reg atomic_op, |
| 1296 | struct brw_reg surf_index) |
| 1297 | { |
| 1298 | assert(atomic_op.file == BRW_IMMEDIATE_VALUE && |
| 1299 | atomic_op.type == BRW_REGISTER_TYPE_UD && |
| 1300 | surf_index.file == BRW_IMMEDIATE_VALUE && |
| 1301 | surf_index.type == BRW_REGISTER_TYPE_UD); |
| 1302 | |
| 1303 | brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf), |
| 1304 | atomic_op.dw1.ud, surf_index.dw1.ud, |
| 1305 | inst->mlen, dispatch_width / 8); |
| 1306 | |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 1307 | brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud); |
Francisco Jerez | cfaaa9b | 2013-09-11 14:01:50 -0700 | [diff] [blame] | 1308 | } |
| 1309 | |
| 1310 | void |
Francisco Jerez | 5e621cb | 2013-09-11 14:03:13 -0700 | [diff] [blame] | 1311 | fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst, |
| 1312 | struct brw_reg surf_index) |
| 1313 | { |
| 1314 | assert(surf_index.file == BRW_IMMEDIATE_VALUE && |
| 1315 | surf_index.type == BRW_REGISTER_TYPE_UD); |
| 1316 | |
| 1317 | brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf), |
| 1318 | surf_index.dw1.ud, |
| 1319 | inst->mlen, dispatch_width / 8); |
| 1320 | |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 1321 | brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud); |
Francisco Jerez | 5e621cb | 2013-09-11 14:03:13 -0700 | [diff] [blame] | 1322 | } |
| 1323 | |
| 1324 | void |
Matt Turner | 59f4e80 | 2014-05-17 13:25:15 -0700 | [diff] [blame] | 1325 | fs_generator::generate_code(exec_list *instructions) |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1326 | { |
Eric Anholt | f2bd3e7 | 2012-02-03 11:50:42 +0100 | [diff] [blame] | 1327 | int last_native_insn_offset = p->next_insn_offset; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1328 | const char *last_annotation_string = NULL; |
Eric Anholt | 97615b2 | 2012-08-27 14:35:01 -0700 | [diff] [blame] | 1329 | const void *last_annotation_ir = NULL; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1330 | |
Matt Turner | cd1c1d3 | 2014-05-14 15:05:09 -0700 | [diff] [blame] | 1331 | if (unlikely(debug_flag)) { |
Paul Berry | 9cee3ff | 2014-01-22 11:45:39 -0800 | [diff] [blame] | 1332 | if (prog) { |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1333 | fprintf(stderr, |
| 1334 | "Native code for %s fragment shader %d (SIMD%d dispatch):\n", |
| 1335 | prog->Label ? prog->Label : "unnamed", |
| 1336 | prog->Name, dispatch_width); |
Topi Pohjolainen | 1958a9b | 2013-11-27 16:21:11 +0200 | [diff] [blame] | 1337 | } else if (fp) { |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1338 | fprintf(stderr, |
| 1339 | "Native code for fragment program %d (SIMD%d dispatch):\n", |
| 1340 | fp->Base.Id, dispatch_width); |
Topi Pohjolainen | 1958a9b | 2013-11-27 16:21:11 +0200 | [diff] [blame] | 1341 | } else { |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1342 | fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n", |
| 1343 | dispatch_width); |
Eric Anholt | 97615b2 | 2012-08-27 14:35:01 -0700 | [diff] [blame] | 1344 | } |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1345 | } |
| 1346 | |
Eric Anholt | 7abfb67 | 2012-10-03 13:16:09 -0700 | [diff] [blame] | 1347 | cfg_t *cfg = NULL; |
Matt Turner | cd1c1d3 | 2014-05-14 15:05:09 -0700 | [diff] [blame] | 1348 | if (unlikely(debug_flag)) |
Matt Turner | d2fcdd0 | 2013-11-28 23:24:44 -0800 | [diff] [blame] | 1349 | cfg = new(mem_ctx) cfg_t(instructions); |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1350 | |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 1351 | foreach_list(node, instructions) { |
Eric Anholt | 44ffb4a | 2011-07-29 11:52:39 -0700 | [diff] [blame] | 1352 | fs_inst *inst = (fs_inst *)node; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1353 | struct brw_reg src[3], dst; |
| 1354 | |
Matt Turner | cd1c1d3 | 2014-05-14 15:05:09 -0700 | [diff] [blame] | 1355 | if (unlikely(debug_flag)) { |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1356 | foreach_list(node, &cfg->block_list) { |
Eric Anholt | 7abfb67 | 2012-10-03 13:16:09 -0700 | [diff] [blame] | 1357 | bblock_link *link = (bblock_link *)node; |
| 1358 | bblock_t *block = link->block; |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1359 | |
| 1360 | if (block->start == inst) { |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1361 | fprintf(stderr, " START B%d", block->block_num); |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1362 | foreach_list(predecessor_node, &block->parents) { |
Eric Anholt | 7abfb67 | 2012-10-03 13:16:09 -0700 | [diff] [blame] | 1363 | bblock_link *predecessor_link = |
| 1364 | (bblock_link *)predecessor_node; |
| 1365 | bblock_t *predecessor_block = predecessor_link->block; |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1366 | fprintf(stderr, " <-B%d", predecessor_block->block_num); |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1367 | } |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1368 | fprintf(stderr, "\n"); |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1369 | } |
| 1370 | } |
| 1371 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1372 | if (last_annotation_ir != inst->ir) { |
| 1373 | last_annotation_ir = inst->ir; |
| 1374 | if (last_annotation_ir) { |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1375 | fprintf(stderr, " "); |
Paul Berry | 9cee3ff | 2014-01-22 11:45:39 -0800 | [diff] [blame] | 1376 | if (prog) |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1377 | ((ir_instruction *)inst->ir)->fprint(stderr); |
Eric Anholt | 97615b2 | 2012-08-27 14:35:01 -0700 | [diff] [blame] | 1378 | else { |
| 1379 | const prog_instruction *fpi; |
| 1380 | fpi = (const prog_instruction *)inst->ir; |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1381 | fprintf(stderr, "%d: ", |
| 1382 | (int)(fpi - (fp ? fp->Base.Instructions : 0))); |
| 1383 | _mesa_fprint_instruction_opt(stderr, |
Eric Anholt | 97615b2 | 2012-08-27 14:35:01 -0700 | [diff] [blame] | 1384 | fpi, |
| 1385 | 0, PROG_PRINT_DEBUG, NULL); |
| 1386 | } |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1387 | fprintf(stderr, "\n"); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1388 | } |
| 1389 | } |
| 1390 | if (last_annotation_string != inst->annotation) { |
| 1391 | last_annotation_string = inst->annotation; |
| 1392 | if (last_annotation_string) |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1393 | fprintf(stderr, " %s\n", last_annotation_string); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1394 | } |
| 1395 | } |
| 1396 | |
| 1397 | for (unsigned int i = 0; i < 3; i++) { |
| 1398 | src[i] = brw_reg_from_fs_reg(&inst->src[i]); |
Eric Anholt | 73b0a28 | 2011-10-03 15:12:10 -0700 | [diff] [blame] | 1399 | |
| 1400 | /* The accumulator result appears to get used for the |
| 1401 | * conditional modifier generation. When negating a UD |
| 1402 | * value, there is a 33rd bit generated for the sign in the |
| 1403 | * accumulator value, so now you can't check, for example, |
| 1404 | * equality with a 32-bit value. See piglit fs-op-neg-uvec4. |
| 1405 | */ |
| 1406 | assert(!inst->conditional_mod || |
| 1407 | inst->src[i].type != BRW_REGISTER_TYPE_UD || |
| 1408 | !inst->src[i].negate); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1409 | } |
| 1410 | dst = brw_reg_from_fs_reg(&inst->dst); |
| 1411 | |
| 1412 | brw_set_conditionalmod(p, inst->conditional_mod); |
Eric Anholt | 54679fc | 2012-10-03 13:23:05 -0700 | [diff] [blame] | 1413 | brw_set_predicate_control(p, inst->predicate); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1414 | brw_set_predicate_inverse(p, inst->predicate_inverse); |
Eric Anholt | b278f65 | 2012-12-06 10:36:11 -0800 | [diff] [blame] | 1415 | brw_set_flag_reg(p, 0, inst->flag_subreg); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1416 | brw_set_saturate(p, inst->saturate); |
Eric Anholt | ef2fbf6 | 2012-11-28 14:16:03 -0800 | [diff] [blame] | 1417 | brw_set_mask_control(p, inst->force_writemask_all); |
Juha-Pekka Heikkila | 306ed81 | 2014-04-04 16:51:59 +0300 | [diff] [blame] | 1418 | brw_set_acc_write_control(p, inst->writes_accumulator); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1419 | |
Kenneth Graunke | a303df8 | 2012-11-20 13:50:52 -0800 | [diff] [blame] | 1420 | if (inst->force_uncompressed || dispatch_width == 8) { |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1421 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 1422 | } else if (inst->force_sechalf) { |
| 1423 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |
| 1424 | } else { |
| 1425 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
| 1426 | } |
| 1427 | |
| 1428 | switch (inst->opcode) { |
| 1429 | case BRW_OPCODE_MOV: |
| 1430 | brw_MOV(p, dst, src[0]); |
| 1431 | break; |
| 1432 | case BRW_OPCODE_ADD: |
| 1433 | brw_ADD(p, dst, src[0], src[1]); |
| 1434 | break; |
| 1435 | case BRW_OPCODE_MUL: |
| 1436 | brw_MUL(p, dst, src[0], src[1]); |
| 1437 | break; |
Topi Pohjolainen | 8f3e536 | 2013-12-17 16:39:16 +0200 | [diff] [blame] | 1438 | case BRW_OPCODE_AVG: |
| 1439 | brw_AVG(p, dst, src[0], src[1]); |
| 1440 | break; |
Eric Anholt | 3f78f71 | 2011-08-15 22:36:18 -0700 | [diff] [blame] | 1441 | case BRW_OPCODE_MACH: |
Eric Anholt | 3f78f71 | 2011-08-15 22:36:18 -0700 | [diff] [blame] | 1442 | brw_MACH(p, dst, src[0], src[1]); |
Eric Anholt | 3f78f71 | 2011-08-15 22:36:18 -0700 | [diff] [blame] | 1443 | break; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1444 | |
Eric Anholt | 7d55f37 | 2012-02-07 00:59:11 +0100 | [diff] [blame] | 1445 | case BRW_OPCODE_MAD: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1446 | assert(brw->gen >= 6); |
Eric Anholt | 7d55f37 | 2012-02-07 00:59:11 +0100 | [diff] [blame] | 1447 | brw_set_access_mode(p, BRW_ALIGN_16); |
Matt Turner | 9bbedf6 | 2013-11-16 12:31:26 -0800 | [diff] [blame] | 1448 | if (dispatch_width == 16 && !brw->is_haswell) { |
Eric Anholt | 7d55f37 | 2012-02-07 00:59:11 +0100 | [diff] [blame] | 1449 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 1450 | brw_MAD(p, dst, src[0], src[1], src[2]); |
| 1451 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |
| 1452 | brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2])); |
| 1453 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
| 1454 | } else { |
| 1455 | brw_MAD(p, dst, src[0], src[1], src[2]); |
| 1456 | } |
| 1457 | brw_set_access_mode(p, BRW_ALIGN_1); |
| 1458 | break; |
| 1459 | |
Kenneth Graunke | 0a1d145 | 2012-12-02 00:08:15 -0800 | [diff] [blame] | 1460 | case BRW_OPCODE_LRP: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1461 | assert(brw->gen >= 6); |
Kenneth Graunke | 0a1d145 | 2012-12-02 00:08:15 -0800 | [diff] [blame] | 1462 | brw_set_access_mode(p, BRW_ALIGN_16); |
Matt Turner | 9bbedf6 | 2013-11-16 12:31:26 -0800 | [diff] [blame] | 1463 | if (dispatch_width == 16 && !brw->is_haswell) { |
Kenneth Graunke | 0a1d145 | 2012-12-02 00:08:15 -0800 | [diff] [blame] | 1464 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 1465 | brw_LRP(p, dst, src[0], src[1], src[2]); |
| 1466 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |
| 1467 | brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2])); |
| 1468 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
| 1469 | } else { |
| 1470 | brw_LRP(p, dst, src[0], src[1], src[2]); |
| 1471 | } |
| 1472 | brw_set_access_mode(p, BRW_ALIGN_1); |
| 1473 | break; |
| 1474 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1475 | case BRW_OPCODE_FRC: |
| 1476 | brw_FRC(p, dst, src[0]); |
| 1477 | break; |
| 1478 | case BRW_OPCODE_RNDD: |
| 1479 | brw_RNDD(p, dst, src[0]); |
| 1480 | break; |
| 1481 | case BRW_OPCODE_RNDE: |
| 1482 | brw_RNDE(p, dst, src[0]); |
| 1483 | break; |
| 1484 | case BRW_OPCODE_RNDZ: |
| 1485 | brw_RNDZ(p, dst, src[0]); |
| 1486 | break; |
| 1487 | |
| 1488 | case BRW_OPCODE_AND: |
| 1489 | brw_AND(p, dst, src[0], src[1]); |
| 1490 | break; |
| 1491 | case BRW_OPCODE_OR: |
| 1492 | brw_OR(p, dst, src[0], src[1]); |
| 1493 | break; |
| 1494 | case BRW_OPCODE_XOR: |
| 1495 | brw_XOR(p, dst, src[0], src[1]); |
| 1496 | break; |
| 1497 | case BRW_OPCODE_NOT: |
| 1498 | brw_NOT(p, dst, src[0]); |
| 1499 | break; |
| 1500 | case BRW_OPCODE_ASR: |
| 1501 | brw_ASR(p, dst, src[0], src[1]); |
| 1502 | break; |
| 1503 | case BRW_OPCODE_SHR: |
| 1504 | brw_SHR(p, dst, src[0], src[1]); |
| 1505 | break; |
| 1506 | case BRW_OPCODE_SHL: |
| 1507 | brw_SHL(p, dst, src[0], src[1]); |
| 1508 | break; |
Chad Versace | 20dfa50 | 2013-01-09 11:46:42 -0800 | [diff] [blame] | 1509 | case BRW_OPCODE_F32TO16: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1510 | assert(brw->gen >= 7); |
Chad Versace | 20dfa50 | 2013-01-09 11:46:42 -0800 | [diff] [blame] | 1511 | brw_F32TO16(p, dst, src[0]); |
| 1512 | break; |
| 1513 | case BRW_OPCODE_F16TO32: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1514 | assert(brw->gen >= 7); |
Chad Versace | 20dfa50 | 2013-01-09 11:46:42 -0800 | [diff] [blame] | 1515 | brw_F16TO32(p, dst, src[0]); |
| 1516 | break; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1517 | case BRW_OPCODE_CMP: |
| 1518 | brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); |
| 1519 | break; |
| 1520 | case BRW_OPCODE_SEL: |
| 1521 | brw_SEL(p, dst, src[0], src[1]); |
| 1522 | break; |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1523 | case BRW_OPCODE_BFREV: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1524 | assert(brw->gen >= 7); |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1525 | /* BFREV only supports UD type for src and dst. */ |
| 1526 | brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD), |
| 1527 | retype(src[0], BRW_REGISTER_TYPE_UD)); |
| 1528 | break; |
| 1529 | case BRW_OPCODE_FBH: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1530 | assert(brw->gen >= 7); |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1531 | /* FBH only supports UD type for dst. */ |
| 1532 | brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]); |
| 1533 | break; |
| 1534 | case BRW_OPCODE_FBL: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1535 | assert(brw->gen >= 7); |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1536 | /* FBL only supports UD type for dst. */ |
| 1537 | brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]); |
| 1538 | break; |
| 1539 | case BRW_OPCODE_CBIT: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1540 | assert(brw->gen >= 7); |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1541 | /* CBIT only supports UD type for dst. */ |
| 1542 | brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]); |
| 1543 | break; |
Matt Turner | 014cce3 | 2013-09-19 13:01:08 -0700 | [diff] [blame] | 1544 | case BRW_OPCODE_ADDC: |
| 1545 | assert(brw->gen >= 7); |
Matt Turner | 014cce3 | 2013-09-19 13:01:08 -0700 | [diff] [blame] | 1546 | brw_ADDC(p, dst, src[0], src[1]); |
Matt Turner | 014cce3 | 2013-09-19 13:01:08 -0700 | [diff] [blame] | 1547 | break; |
| 1548 | case BRW_OPCODE_SUBB: |
| 1549 | assert(brw->gen >= 7); |
Matt Turner | 014cce3 | 2013-09-19 13:01:08 -0700 | [diff] [blame] | 1550 | brw_SUBB(p, dst, src[0], src[1]); |
Matt Turner | 014cce3 | 2013-09-19 13:01:08 -0700 | [diff] [blame] | 1551 | break; |
Juha-Pekka Heikkila | da0c3b0 | 2014-03-28 15:28:32 +0200 | [diff] [blame] | 1552 | case BRW_OPCODE_MAC: |
| 1553 | brw_MAC(p, dst, src[0], src[1]); |
| 1554 | break; |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1555 | |
| 1556 | case BRW_OPCODE_BFE: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1557 | assert(brw->gen >= 7); |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1558 | brw_set_access_mode(p, BRW_ALIGN_16); |
Matt Turner | 9bbedf6 | 2013-11-16 12:31:26 -0800 | [diff] [blame] | 1559 | if (dispatch_width == 16 && !brw->is_haswell) { |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1560 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 1561 | brw_BFE(p, dst, src[0], src[1], src[2]); |
| 1562 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |
| 1563 | brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2])); |
| 1564 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
| 1565 | } else { |
| 1566 | brw_BFE(p, dst, src[0], src[1], src[2]); |
| 1567 | } |
| 1568 | brw_set_access_mode(p, BRW_ALIGN_1); |
| 1569 | break; |
| 1570 | |
| 1571 | case BRW_OPCODE_BFI1: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1572 | assert(brw->gen >= 7); |
Matt Turner | c4464c9 | 2013-11-16 13:16:50 -0800 | [diff] [blame] | 1573 | /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we |
| 1574 | * should |
| 1575 | * |
| 1576 | * "Force BFI instructions to be executed always in SIMD8." |
| 1577 | */ |
| 1578 | if (dispatch_width == 16 && brw->is_haswell) { |
| 1579 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 1580 | brw_BFI1(p, dst, src[0], src[1]); |
| 1581 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |
| 1582 | brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1])); |
| 1583 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
| 1584 | } else { |
| 1585 | brw_BFI1(p, dst, src[0], src[1]); |
| 1586 | } |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1587 | break; |
| 1588 | case BRW_OPCODE_BFI2: |
Matt Turner | 69909c8 | 2013-09-19 22:55:24 -0700 | [diff] [blame] | 1589 | assert(brw->gen >= 7); |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1590 | brw_set_access_mode(p, BRW_ALIGN_16); |
Matt Turner | c4464c9 | 2013-11-16 13:16:50 -0800 | [diff] [blame] | 1591 | /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we |
| 1592 | * should |
| 1593 | * |
| 1594 | * "Force BFI instructions to be executed always in SIMD8." |
| 1595 | * |
| 1596 | * Otherwise we would be able to emit compressed instructions like we |
| 1597 | * do for the other three-source instructions. |
| 1598 | */ |
Matt Turner | 1f0f26d | 2013-04-09 19:22:34 -0700 | [diff] [blame] | 1599 | if (dispatch_width == 16) { |
| 1600 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 1601 | brw_BFI2(p, dst, src[0], src[1], src[2]); |
| 1602 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |
| 1603 | brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2])); |
| 1604 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
| 1605 | } else { |
| 1606 | brw_BFI2(p, dst, src[0], src[1], src[2]); |
| 1607 | } |
| 1608 | brw_set_access_mode(p, BRW_ALIGN_1); |
| 1609 | break; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1610 | |
| 1611 | case BRW_OPCODE_IF: |
| 1612 | if (inst->src[0].file != BAD_FILE) { |
| 1613 | /* The instruction has an embedded compare (only allowed on gen6) */ |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 1614 | assert(brw->gen == 6); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1615 | gen6_IF(p, inst->conditional_mod, src[0], src[1]); |
| 1616 | } else { |
Kenneth Graunke | a303df8 | 2012-11-20 13:50:52 -0800 | [diff] [blame] | 1617 | brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1618 | } |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1619 | break; |
| 1620 | |
| 1621 | case BRW_OPCODE_ELSE: |
| 1622 | brw_ELSE(p); |
| 1623 | break; |
| 1624 | case BRW_OPCODE_ENDIF: |
| 1625 | brw_ENDIF(p); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1626 | break; |
| 1627 | |
| 1628 | case BRW_OPCODE_DO: |
Eric Anholt | ce6be33 | 2011-12-06 12:30:03 -0800 | [diff] [blame] | 1629 | brw_DO(p, BRW_EXECUTE_8); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1630 | break; |
| 1631 | |
| 1632 | case BRW_OPCODE_BREAK: |
Eric Anholt | f1d8963 | 2011-12-06 12:44:41 -0800 | [diff] [blame] | 1633 | brw_BREAK(p); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1634 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); |
| 1635 | break; |
| 1636 | case BRW_OPCODE_CONTINUE: |
| 1637 | /* FINISHME: We need to write the loop instruction support still. */ |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 1638 | if (brw->gen >= 6) |
Eric Anholt | 9f88147 | 2011-12-06 12:09:58 -0800 | [diff] [blame] | 1639 | gen6_CONT(p); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1640 | else |
Eric Anholt | f1d8963 | 2011-12-06 12:44:41 -0800 | [diff] [blame] | 1641 | brw_CONT(p); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1642 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); |
| 1643 | break; |
| 1644 | |
Eric Anholt | ce6be33 | 2011-12-06 12:30:03 -0800 | [diff] [blame] | 1645 | case BRW_OPCODE_WHILE: |
Eric Anholt | ce6be33 | 2011-12-06 12:30:03 -0800 | [diff] [blame] | 1646 | brw_WHILE(p); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1647 | break; |
| 1648 | |
Eric Anholt | 65b5cbb | 2011-08-05 12:38:58 -0700 | [diff] [blame] | 1649 | case SHADER_OPCODE_RCP: |
| 1650 | case SHADER_OPCODE_RSQ: |
| 1651 | case SHADER_OPCODE_SQRT: |
| 1652 | case SHADER_OPCODE_EXP2: |
| 1653 | case SHADER_OPCODE_LOG2: |
Eric Anholt | 65b5cbb | 2011-08-05 12:38:58 -0700 | [diff] [blame] | 1654 | case SHADER_OPCODE_SIN: |
| 1655 | case SHADER_OPCODE_COS: |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 1656 | if (brw->gen >= 7) { |
Kenneth Graunke | a73c65c | 2011-10-18 12:24:47 -0700 | [diff] [blame] | 1657 | generate_math1_gen7(inst, dst, src[0]); |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 1658 | } else if (brw->gen == 6) { |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 1659 | generate_math1_gen6(inst, dst, src[0]); |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 1660 | } else if (brw->gen == 5 || brw->is_g4x) { |
Kenneth Graunke | 1b77d21 | 2013-03-30 00:15:54 -0700 | [diff] [blame] | 1661 | generate_math_g45(inst, dst, src[0]); |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 1662 | } else { |
| 1663 | generate_math_gen4(inst, dst, src[0]); |
| 1664 | } |
| 1665 | break; |
Kenneth Graunke | ff8f272 | 2011-09-28 17:37:54 -0700 | [diff] [blame] | 1666 | case SHADER_OPCODE_INT_QUOTIENT: |
| 1667 | case SHADER_OPCODE_INT_REMAINDER: |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 1668 | case SHADER_OPCODE_POW: |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 1669 | if (brw->gen >= 7) { |
Kenneth Graunke | a73c65c | 2011-10-18 12:24:47 -0700 | [diff] [blame] | 1670 | generate_math2_gen7(inst, dst, src[0], src[1]); |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 1671 | } else if (brw->gen == 6) { |
Kenneth Graunke | 74e927b | 2011-08-18 11:55:42 -0700 | [diff] [blame] | 1672 | generate_math2_gen6(inst, dst, src[0], src[1]); |
| 1673 | } else { |
| 1674 | generate_math_gen4(inst, dst, src[0]); |
| 1675 | } |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1676 | break; |
| 1677 | case FS_OPCODE_PIXEL_X: |
| 1678 | generate_pixel_xy(dst, true); |
| 1679 | break; |
| 1680 | case FS_OPCODE_PIXEL_Y: |
| 1681 | generate_pixel_xy(dst, false); |
| 1682 | break; |
| 1683 | case FS_OPCODE_CINTERP: |
| 1684 | brw_MOV(p, dst, src[0]); |
| 1685 | break; |
| 1686 | case FS_OPCODE_LINTERP: |
| 1687 | generate_linterp(inst, dst, src); |
| 1688 | break; |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 1689 | case SHADER_OPCODE_TEX: |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1690 | case FS_OPCODE_TXB: |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 1691 | case SHADER_OPCODE_TXD: |
| 1692 | case SHADER_OPCODE_TXF: |
Topi Pohjolainen | ce527a6 | 2013-12-10 16:36:31 +0200 | [diff] [blame] | 1693 | case SHADER_OPCODE_TXF_CMS: |
Topi Pohjolainen | 41d397f | 2013-12-10 16:38:15 +0200 | [diff] [blame] | 1694 | case SHADER_OPCODE_TXF_UMS: |
Chris Forbes | 7629c48 | 2013-11-30 10:32:16 +1300 | [diff] [blame] | 1695 | case SHADER_OPCODE_TXF_MCS: |
Kenneth Graunke | febad17 | 2011-10-26 12:58:37 -0700 | [diff] [blame] | 1696 | case SHADER_OPCODE_TXL: |
| 1697 | case SHADER_OPCODE_TXS: |
Matt Turner | b8aa9f7 | 2013-03-06 14:47:01 -0800 | [diff] [blame] | 1698 | case SHADER_OPCODE_LOD: |
Chris Forbes | fb45550 | 2013-03-31 21:31:12 +1300 | [diff] [blame] | 1699 | case SHADER_OPCODE_TG4: |
Chris Forbes | 6bb2cf2 | 2013-10-08 21:42:10 +1300 | [diff] [blame] | 1700 | case SHADER_OPCODE_TG4_OFFSET: |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1701 | generate_tex(inst, dst, src[0]); |
| 1702 | break; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1703 | case FS_OPCODE_DDX: |
| 1704 | generate_ddx(inst, dst, src[0]); |
| 1705 | break; |
| 1706 | case FS_OPCODE_DDY: |
Paul Berry | d08fdac | 2012-06-20 13:40:45 -0700 | [diff] [blame] | 1707 | /* Make sure fp->UsesDFdy flag got set (otherwise there's no |
Kenneth Graunke | c96fdeb | 2014-05-14 00:24:50 -0700 | [diff] [blame] | 1708 | * guarantee that key->render_to_fbo is set). |
Paul Berry | d08fdac | 2012-06-20 13:40:45 -0700 | [diff] [blame] | 1709 | */ |
| 1710 | assert(fp->UsesDFdy); |
Kenneth Graunke | c96fdeb | 2014-05-14 00:24:50 -0700 | [diff] [blame] | 1711 | generate_ddy(inst, dst, src[0], key->render_to_fbo); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1712 | break; |
| 1713 | |
Eric Anholt | 6032261 | 2013-10-16 11:45:06 -0700 | [diff] [blame] | 1714 | case SHADER_OPCODE_GEN4_SCRATCH_WRITE: |
| 1715 | generate_scratch_write(inst, src[0]); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1716 | break; |
| 1717 | |
Eric Anholt | 6032261 | 2013-10-16 11:45:06 -0700 | [diff] [blame] | 1718 | case SHADER_OPCODE_GEN4_SCRATCH_READ: |
| 1719 | generate_scratch_read(inst, dst); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1720 | break; |
| 1721 | |
Eric Anholt | 8dfc9f0 | 2013-10-16 11:51:22 -0700 | [diff] [blame] | 1722 | case SHADER_OPCODE_GEN7_SCRATCH_READ: |
| 1723 | generate_scratch_read_gen7(inst, dst); |
| 1724 | break; |
| 1725 | |
Eric Anholt | 29340d0 | 2012-11-07 10:42:34 -0800 | [diff] [blame] | 1726 | case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: |
| 1727 | generate_uniform_pull_constant_load(inst, dst, src[0], src[1]); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1728 | break; |
| 1729 | |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 1730 | case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: |
| 1731 | generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]); |
| 1732 | break; |
| 1733 | |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 1734 | case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD: |
Eric Anholt | 70b27e0 | 2013-03-18 10:16:42 -0700 | [diff] [blame] | 1735 | generate_varying_pull_constant_load(inst, dst, src[0], src[1]); |
Eric Anholt | d8214e4 | 2012-11-07 11:18:34 -0800 | [diff] [blame] | 1736 | break; |
| 1737 | |
| 1738 | case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7: |
| 1739 | generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]); |
| 1740 | break; |
| 1741 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1742 | case FS_OPCODE_FB_WRITE: |
| 1743 | generate_fb_write(inst); |
| 1744 | break; |
Paul Berry | 3f929ef | 2012-06-18 14:50:04 -0700 | [diff] [blame] | 1745 | |
Topi Pohjolainen | 9927d7a | 2013-12-17 14:00:50 +0200 | [diff] [blame] | 1746 | case FS_OPCODE_BLORP_FB_WRITE: |
| 1747 | generate_blorp_fb_write(inst); |
| 1748 | break; |
| 1749 | |
Paul Berry | 3f929ef | 2012-06-18 14:50:04 -0700 | [diff] [blame] | 1750 | case FS_OPCODE_MOV_DISPATCH_TO_FLAGS: |
Eric Anholt | b278f65 | 2012-12-06 10:36:11 -0800 | [diff] [blame] | 1751 | generate_mov_dispatch_to_flags(inst); |
Paul Berry | 3f929ef | 2012-06-18 14:50:04 -0700 | [diff] [blame] | 1752 | break; |
| 1753 | |
Eric Anholt | beafced | 2012-12-06 10:15:08 -0800 | [diff] [blame] | 1754 | case FS_OPCODE_DISCARD_JUMP: |
| 1755 | generate_discard_jump(inst); |
| 1756 | break; |
| 1757 | |
Eric Anholt | 71f0634 | 2012-11-27 14:10:52 -0800 | [diff] [blame] | 1758 | case SHADER_OPCODE_SHADER_TIME_ADD: |
Eric Anholt | 5c5218e | 2013-03-19 15:28:11 -0700 | [diff] [blame] | 1759 | generate_shader_time_add(inst, src[0], src[1], src[2]); |
Eric Anholt | 71f0634 | 2012-11-27 14:10:52 -0800 | [diff] [blame] | 1760 | break; |
| 1761 | |
Francisco Jerez | cfaaa9b | 2013-09-11 14:01:50 -0700 | [diff] [blame] | 1762 | case SHADER_OPCODE_UNTYPED_ATOMIC: |
| 1763 | generate_untyped_atomic(inst, dst, src[0], src[1]); |
| 1764 | break; |
| 1765 | |
Francisco Jerez | 5e621cb | 2013-09-11 14:03:13 -0700 | [diff] [blame] | 1766 | case SHADER_OPCODE_UNTYPED_SURFACE_READ: |
| 1767 | generate_untyped_surface_read(inst, dst, src[0]); |
| 1768 | break; |
| 1769 | |
Eric Anholt | 4c1fdae | 2013-03-06 14:47:22 -0800 | [diff] [blame] | 1770 | case FS_OPCODE_SET_SIMD4X2_OFFSET: |
| 1771 | generate_set_simd4x2_offset(inst, dst, src[0]); |
Eric Anholt | 461a297 | 2012-12-05 00:06:30 -0800 | [diff] [blame] | 1772 | break; |
| 1773 | |
Anuj Phogat | e26bdf5 | 2013-10-24 16:21:13 -0700 | [diff] [blame] | 1774 | case FS_OPCODE_SET_OMASK: |
| 1775 | generate_set_omask(inst, dst, src[0]); |
| 1776 | break; |
| 1777 | |
Anuj Phogat | e12bbb5 | 2013-10-24 16:17:08 -0700 | [diff] [blame] | 1778 | case FS_OPCODE_SET_SAMPLE_ID: |
| 1779 | generate_set_sample_id(inst, dst, src[0], src[1]); |
| 1780 | break; |
| 1781 | |
Chad Versace | 20dfa50 | 2013-01-09 11:46:42 -0800 | [diff] [blame] | 1782 | case FS_OPCODE_PACK_HALF_2x16_SPLIT: |
| 1783 | generate_pack_half_2x16_split(inst, dst, src[0], src[1]); |
| 1784 | break; |
| 1785 | |
| 1786 | case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X: |
| 1787 | case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y: |
| 1788 | generate_unpack_half_2x16_split(inst, dst, src[0]); |
| 1789 | break; |
| 1790 | |
Kenneth Graunke | 57a5025 | 2013-03-27 23:19:39 -0700 | [diff] [blame] | 1791 | case FS_OPCODE_PLACEHOLDER_HALT: |
| 1792 | /* This is the place where the final HALT needs to be inserted if |
| 1793 | * we've emitted any discards. If not, this will emit no code. |
| 1794 | */ |
| 1795 | patch_discard_jumps_to_fb_writes(); |
| 1796 | break; |
| 1797 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1798 | default: |
Kenneth Graunke | b02492f | 2012-11-14 14:24:31 -0800 | [diff] [blame] | 1799 | if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) { |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1800 | _mesa_problem(ctx, "Unsupported opcode `%s' in FS", |
Kenneth Graunke | b02492f | 2012-11-14 14:24:31 -0800 | [diff] [blame] | 1801 | opcode_descs[inst->opcode].name); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1802 | } else { |
| 1803 | _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode); |
| 1804 | } |
Kenneth Graunke | dd1fd30 | 2012-11-20 17:02:23 -0800 | [diff] [blame] | 1805 | abort(); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1806 | } |
| 1807 | |
Matt Turner | cd1c1d3 | 2014-05-14 15:05:09 -0700 | [diff] [blame] | 1808 | if (unlikely(debug_flag)) { |
Kenneth Graunke | db1449b | 2014-05-15 16:10:09 -0700 | [diff] [blame] | 1809 | brw_disassemble(brw, p->store, last_native_insn_offset, p->next_insn_offset, stderr); |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1810 | |
| 1811 | foreach_list(node, &cfg->block_list) { |
Eric Anholt | 7abfb67 | 2012-10-03 13:16:09 -0700 | [diff] [blame] | 1812 | bblock_link *link = (bblock_link *)node; |
| 1813 | bblock_t *block = link->block; |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1814 | |
| 1815 | if (block->end == inst) { |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1816 | fprintf(stderr, " END B%d", block->block_num); |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1817 | foreach_list(successor_node, &block->children) { |
Eric Anholt | 7abfb67 | 2012-10-03 13:16:09 -0700 | [diff] [blame] | 1818 | bblock_link *successor_link = |
| 1819 | (bblock_link *)successor_node; |
| 1820 | bblock_t *successor_block = successor_link->block; |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1821 | fprintf(stderr, " ->B%d", successor_block->block_num); |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1822 | } |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1823 | fprintf(stderr, "\n"); |
Eric Anholt | 080b125 | 2012-04-10 12:01:50 -0700 | [diff] [blame] | 1824 | } |
| 1825 | } |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1826 | } |
| 1827 | |
Eric Anholt | f2bd3e7 | 2012-02-03 11:50:42 +0100 | [diff] [blame] | 1828 | last_native_insn_offset = p->next_insn_offset; |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1829 | } |
| 1830 | |
Matt Turner | cd1c1d3 | 2014-05-14 15:05:09 -0700 | [diff] [blame] | 1831 | if (unlikely(debug_flag)) { |
Eric Anholt | a76e5dc | 2013-12-22 23:29:31 -0800 | [diff] [blame] | 1832 | fprintf(stderr, "\n"); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1833 | } |
| 1834 | |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1835 | brw_set_uip_jip(p); |
| 1836 | |
| 1837 | /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS |
| 1838 | * emit issues, it doesn't get the jump distances into the output, |
| 1839 | * which is often something we want to debug. So this is here in |
| 1840 | * case you're doing that. |
| 1841 | */ |
Matt Turner | 59f4e80 | 2014-05-17 13:25:15 -0700 | [diff] [blame] | 1842 | if (0) { |
| 1843 | brw_disassemble(brw, p->store, 0, p->next_insn_offset, stderr); |
Eric Anholt | 11dd9e9 | 2011-05-24 16:34:27 -0700 | [diff] [blame] | 1844 | } |
| 1845 | } |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 1846 | |
| 1847 | const unsigned * |
| 1848 | fs_generator::generate_assembly(exec_list *simd8_instructions, |
| 1849 | exec_list *simd16_instructions, |
Matt Turner | 59f4e80 | 2014-05-17 13:25:15 -0700 | [diff] [blame] | 1850 | unsigned *assembly_size) |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 1851 | { |
Topi Pohjolainen | ca53704 | 2013-11-27 14:32:41 +0200 | [diff] [blame] | 1852 | assert(simd8_instructions || simd16_instructions); |
| 1853 | |
| 1854 | if (simd8_instructions) { |
| 1855 | dispatch_width = 8; |
Matt Turner | 59f4e80 | 2014-05-17 13:25:15 -0700 | [diff] [blame] | 1856 | generate_code(simd8_instructions); |
Matt Turner | a35b9cb | 2014-05-19 10:17:51 -0700 | [diff] [blame] | 1857 | brw_compact_instructions(p, 0, 0, NULL); |
Topi Pohjolainen | ca53704 | 2013-11-27 14:32:41 +0200 | [diff] [blame] | 1858 | } |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 1859 | |
| 1860 | if (simd16_instructions) { |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 1861 | /* align to 64 byte boundary. */ |
| 1862 | while ((p->nr_insn * sizeof(struct brw_instruction)) % 64) { |
| 1863 | brw_NOP(p); |
| 1864 | } |
| 1865 | |
Eric Anholt | 746e3e3 | 2013-11-12 15:33:27 -0800 | [diff] [blame] | 1866 | /* Save off the start of this SIMD16 program */ |
Kenneth Graunke | b61d055 | 2014-05-14 00:20:24 -0700 | [diff] [blame] | 1867 | prog_data->prog_offset_16 = p->nr_insn * sizeof(struct brw_instruction); |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 1868 | |
| 1869 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); |
| 1870 | |
| 1871 | dispatch_width = 16; |
Matt Turner | 59f4e80 | 2014-05-17 13:25:15 -0700 | [diff] [blame] | 1872 | generate_code(simd16_instructions); |
Matt Turner | a35b9cb | 2014-05-19 10:17:51 -0700 | [diff] [blame] | 1873 | brw_compact_instructions(p, prog_data->prog_offset_16, 0, NULL); |
Kenneth Graunke | ea681a0 | 2012-11-09 01:05:47 -0800 | [diff] [blame] | 1874 | } |
| 1875 | |
| 1876 | return brw_get_program(p, assembly_size); |
| 1877 | } |