Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1 | /* |
Alyssa Rosenzweig | 1155446 | 2019-05-19 23:20:34 +0000 | [diff] [blame] | 2 | * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io> |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include <sys/types.h> |
| 25 | #include <sys/stat.h> |
| 26 | #include <sys/mman.h> |
| 27 | #include <fcntl.h> |
| 28 | #include <stdint.h> |
| 29 | #include <stdlib.h> |
| 30 | #include <stdio.h> |
| 31 | #include <err.h> |
| 32 | |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 33 | #include "main/mtypes.h" |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 34 | #include "compiler/glsl/glsl_to_nir.h" |
| 35 | #include "compiler/nir_types.h" |
| 36 | #include "main/imports.h" |
| 37 | #include "compiler/nir/nir_builder.h" |
| 38 | #include "util/half_float.h" |
Alyssa Rosenzweig | 213b628 | 2019-06-18 09:02:20 -0700 | [diff] [blame] | 39 | #include "util/u_math.h" |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 40 | #include "util/u_debug.h" |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 41 | #include "util/u_dynarray.h" |
| 42 | #include "util/list.h" |
| 43 | #include "main/mtypes.h" |
| 44 | |
| 45 | #include "midgard.h" |
| 46 | #include "midgard_nir.h" |
| 47 | #include "midgard_compile.h" |
Alyssa Rosenzweig | 1155446 | 2019-05-19 23:20:34 +0000 | [diff] [blame] | 48 | #include "midgard_ops.h" |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 49 | #include "helpers.h" |
Alyssa Rosenzweig | 1155446 | 2019-05-19 23:20:34 +0000 | [diff] [blame] | 50 | #include "compiler.h" |
Alyssa Rosenzweig | fcf144d | 2019-11-19 20:55:42 -0500 | [diff] [blame] | 51 | #include "midgard_quirks.h" |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 52 | |
| 53 | #include "disassemble.h" |
| 54 | |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 55 | static const struct debug_named_value debug_options[] = { |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 56 | {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"}, |
| 57 | {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"}, |
Alyssa Rosenzweig | 138e40d | 2019-07-08 16:42:29 -0700 | [diff] [blame] | 58 | {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"}, |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 59 | DEBUG_NAMED_VALUE_END |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 60 | }; |
| 61 | |
| 62 | DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0) |
| 63 | |
Alyssa Rosenzweig | 138e40d | 2019-07-08 16:42:29 -0700 | [diff] [blame] | 64 | unsigned SHADER_DB_COUNT = 0; |
| 65 | |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 66 | int midgard_debug = 0; |
| 67 | |
| 68 | #define DBG(fmt, ...) \ |
| 69 | do { if (midgard_debug & MIDGARD_DBG_MSGS) \ |
| 70 | fprintf(stderr, "%s:%d: "fmt, \ |
| 71 | __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0) |
Alyssa Rosenzweig | cc2ba8e | 2019-08-30 10:53:13 -0700 | [diff] [blame] | 72 | static midgard_block * |
| 73 | create_empty_block(compiler_context *ctx) |
| 74 | { |
| 75 | midgard_block *blk = rzalloc(ctx, midgard_block); |
| 76 | |
| 77 | blk->predecessors = _mesa_set_create(blk, |
| 78 | _mesa_hash_pointer, |
| 79 | _mesa_key_pointer_equal); |
| 80 | |
| 81 | blk->source_id = ctx->block_source_count++; |
| 82 | |
| 83 | return blk; |
| 84 | } |
| 85 | |
Alyssa Rosenzweig | c0fb260 | 2019-04-21 03:29:47 +0000 | [diff] [blame] | 86 | static void |
| 87 | midgard_block_add_successor(midgard_block *block, midgard_block *successor) |
| 88 | { |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 89 | assert(block); |
| 90 | assert(successor); |
| 91 | |
| 92 | /* Deduplicate */ |
| 93 | for (unsigned i = 0; i < block->nr_successors; ++i) { |
| 94 | if (block->successors[i] == successor) |
| 95 | return; |
| 96 | } |
| 97 | |
Alyssa Rosenzweig | c0fb260 | 2019-04-21 03:29:47 +0000 | [diff] [blame] | 98 | block->successors[block->nr_successors++] = successor; |
| 99 | assert(block->nr_successors <= ARRAY_SIZE(block->successors)); |
Alyssa Rosenzweig | aeeeef1 | 2019-08-15 08:11:10 -0700 | [diff] [blame] | 100 | |
| 101 | /* Note the predecessor in the other direction */ |
| 102 | _mesa_set_add(successor->predecessors, block); |
Alyssa Rosenzweig | c0fb260 | 2019-04-21 03:29:47 +0000 | [diff] [blame] | 103 | } |
| 104 | |
Alyssa Rosenzweig | cc2ba8e | 2019-08-30 10:53:13 -0700 | [diff] [blame] | 105 | static void |
| 106 | schedule_barrier(compiler_context *ctx) |
| 107 | { |
| 108 | midgard_block *temp = ctx->after_block; |
| 109 | ctx->after_block = create_empty_block(ctx); |
| 110 | ctx->block_count++; |
| 111 | list_addtail(&ctx->after_block->link, &ctx->blocks); |
| 112 | list_inithead(&ctx->after_block->instructions); |
| 113 | midgard_block_add_successor(ctx->current_block, ctx->after_block); |
| 114 | ctx->current_block = ctx->after_block; |
| 115 | ctx->after_block = temp; |
| 116 | } |
| 117 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 118 | /* Helpers to generate midgard_instruction's using macro magic, since every |
| 119 | * driver seems to do it that way */ |
| 120 | |
| 121 | #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__)); |
Alyssa Rosenzweig | 56f9b47 | 2019-06-14 16:03:01 -0700 | [diff] [blame] | 122 | |
Alyssa Rosenzweig | d4bcca1 | 2019-08-02 15:25:02 -0700 | [diff] [blame] | 123 | #define M_LOAD_STORE(name, store) \ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 124 | static midgard_instruction m_##name(unsigned ssa, unsigned address) { \ |
| 125 | midgard_instruction i = { \ |
| 126 | .type = TAG_LOAD_STORE_4, \ |
Alyssa Rosenzweig | f8b18a4 | 2019-07-01 18:51:48 -0700 | [diff] [blame] | 127 | .mask = 0xF, \ |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 128 | .dest = ~0, \ |
Alyssa Rosenzweig | ccbc9a4 | 2019-12-19 10:35:18 -0500 | [diff] [blame] | 129 | .src = { ~0, ~0, ~0, ~0 }, \ |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 130 | .swizzle = SWIZZLE_IDENTITY_4, \ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 131 | .load_store = { \ |
| 132 | .op = midgard_op_##name, \ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 133 | .address = address \ |
| 134 | } \ |
| 135 | }; \ |
Alyssa Rosenzweig | d4bcca1 | 2019-08-02 15:25:02 -0700 | [diff] [blame] | 136 | \ |
| 137 | if (store) \ |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 138 | i.src[0] = ssa; \ |
Alyssa Rosenzweig | d4bcca1 | 2019-08-02 15:25:02 -0700 | [diff] [blame] | 139 | else \ |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 140 | i.dest = ssa; \ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 141 | \ |
| 142 | return i; \ |
| 143 | } |
| 144 | |
Alyssa Rosenzweig | d4bcca1 | 2019-08-02 15:25:02 -0700 | [diff] [blame] | 145 | #define M_LOAD(name) M_LOAD_STORE(name, false) |
| 146 | #define M_STORE(name) M_LOAD_STORE(name, true) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 147 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 148 | /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs |
| 149 | * the corresponding Midgard source */ |
| 150 | |
| 151 | static midgard_vector_alu_src |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 152 | vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count, |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 153 | bool half, bool sext) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 154 | { |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 155 | /* Figure out how many components there are so we can adjust. |
| 156 | * Specifically we want to broadcast the last channel so things like |
| 157 | * ball2/3 work. |
Alyssa Rosenzweig | 195e297 | 2019-06-19 07:23:27 -0700 | [diff] [blame] | 158 | */ |
| 159 | |
Alyssa Rosenzweig | c3a46e7 | 2019-10-30 16:29:28 -0400 | [diff] [blame] | 160 | if (broadcast_count && src) { |
Alyssa Rosenzweig | 195e297 | 2019-06-19 07:23:27 -0700 | [diff] [blame] | 161 | uint8_t last_component = src->swizzle[broadcast_count - 1]; |
| 162 | |
| 163 | for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) { |
| 164 | src->swizzle[c] = last_component; |
| 165 | } |
| 166 | } |
| 167 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 168 | midgard_vector_alu_src alu_src = { |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 169 | .rep_low = 0, |
| 170 | .rep_high = 0, |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 171 | .half = half |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 172 | }; |
| 173 | |
Alyssa Rosenzweig | fcdfb67 | 2019-04-22 03:25:42 +0000 | [diff] [blame] | 174 | if (is_int) { |
Alyssa Rosenzweig | fcdfb67 | 2019-04-22 03:25:42 +0000 | [diff] [blame] | 175 | alu_src.mod = midgard_int_normal; |
| 176 | |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 177 | /* Sign/zero-extend if needed */ |
| 178 | |
| 179 | if (half) { |
| 180 | alu_src.mod = sext ? |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 181 | midgard_int_sign_extend |
| 182 | : midgard_int_zero_extend; |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 183 | } |
| 184 | |
Alyssa Rosenzweig | fcdfb67 | 2019-04-22 03:25:42 +0000 | [diff] [blame] | 185 | /* These should have been lowered away */ |
Alyssa Rosenzweig | c3a46e7 | 2019-10-30 16:29:28 -0400 | [diff] [blame] | 186 | if (src) |
| 187 | assert(!(src->abs || src->negate)); |
Alyssa Rosenzweig | fcdfb67 | 2019-04-22 03:25:42 +0000 | [diff] [blame] | 188 | } else { |
Alyssa Rosenzweig | c3a46e7 | 2019-10-30 16:29:28 -0400 | [diff] [blame] | 189 | if (src) |
| 190 | alu_src.mod = (src->abs << 0) | (src->negate << 1); |
Alyssa Rosenzweig | fcdfb67 | 2019-04-22 03:25:42 +0000 | [diff] [blame] | 191 | } |
| 192 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 193 | return alu_src; |
| 194 | } |
| 195 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 196 | /* load/store instructions have both 32-bit and 16-bit variants, depending on |
| 197 | * whether we are using vectors composed of highp or mediump. At the moment, we |
| 198 | * don't support half-floats -- this requires changes in other parts of the |
| 199 | * compiler -- therefore the 16-bit versions are commented out. */ |
| 200 | |
Alyssa Rosenzweig | 74ab80b | 2019-05-14 04:11:36 +0000 | [diff] [blame] | 201 | //M_LOAD(ld_attr_16); |
| 202 | M_LOAD(ld_attr_32); |
| 203 | //M_LOAD(ld_vary_16); |
| 204 | M_LOAD(ld_vary_32); |
Alyssa Rosenzweig | ec2f0b5 | 2019-08-13 08:51:40 -0700 | [diff] [blame] | 205 | M_LOAD(ld_ubo_int4); |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 206 | M_LOAD(ld_int4); |
| 207 | M_STORE(st_int4); |
Alyssa Rosenzweig | 2d1e18e | 2020-01-02 12:28:54 -0500 | [diff] [blame] | 208 | M_LOAD(ld_color_buffer_32u); |
Alyssa Rosenzweig | 74ab80b | 2019-05-14 04:11:36 +0000 | [diff] [blame] | 209 | //M_STORE(st_vary_16); |
| 210 | M_STORE(st_vary_32); |
Alyssa Rosenzweig | 9ae4d36 | 2019-08-16 07:50:12 -0700 | [diff] [blame] | 211 | M_LOAD(ld_cubemap_coords); |
Alyssa Rosenzweig | 7229af7 | 2019-08-06 13:47:17 -0700 | [diff] [blame] | 212 | M_LOAD(ld_compute_id); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 213 | |
| 214 | static midgard_instruction |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 215 | v_branch(bool conditional, bool invert) |
| 216 | { |
| 217 | midgard_instruction ins = { |
| 218 | .type = TAG_ALU_4, |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 219 | .unit = ALU_ENAB_BRANCH, |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 220 | .compact_branch = true, |
| 221 | .branch = { |
| 222 | .conditional = conditional, |
| 223 | .invert_conditional = invert |
Alyssa Rosenzweig | 29416a8 | 2019-07-30 12:20:24 -0700 | [diff] [blame] | 224 | }, |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 225 | .dest = ~0, |
Alyssa Rosenzweig | ccbc9a4 | 2019-12-19 10:35:18 -0500 | [diff] [blame] | 226 | .src = { ~0, ~0, ~0, ~0 }, |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 227 | }; |
| 228 | |
| 229 | return ins; |
| 230 | } |
| 231 | |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 232 | static midgard_branch_extended |
| 233 | midgard_create_branch_extended( midgard_condition cond, |
| 234 | midgard_jmp_writeout_op op, |
| 235 | unsigned dest_tag, |
| 236 | signed quadword_offset) |
| 237 | { |
Alyssa Rosenzweig | 13ee87c | 2019-07-29 09:15:32 -0700 | [diff] [blame] | 238 | /* The condition code is actually a LUT describing a function to |
| 239 | * combine multiple condition codes. However, we only support a single |
| 240 | * condition code at the moment, so we just duplicate over a bunch of |
| 241 | * times. */ |
| 242 | |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 243 | uint16_t duplicated_cond = |
| 244 | (cond << 14) | |
| 245 | (cond << 12) | |
| 246 | (cond << 10) | |
| 247 | (cond << 8) | |
| 248 | (cond << 6) | |
| 249 | (cond << 4) | |
| 250 | (cond << 2) | |
| 251 | (cond << 0); |
| 252 | |
| 253 | midgard_branch_extended branch = { |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 254 | .op = op, |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 255 | .dest_tag = dest_tag, |
| 256 | .offset = quadword_offset, |
| 257 | .cond = duplicated_cond |
| 258 | }; |
| 259 | |
| 260 | return branch; |
| 261 | } |
| 262 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 263 | static void |
| 264 | attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name) |
| 265 | { |
| 266 | ins->has_constants = true; |
| 267 | memcpy(&ins->constants, constants, 16); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 268 | } |
| 269 | |
| 270 | static int |
Timothy Arceri | 035759b | 2019-03-29 12:39:48 +1100 | [diff] [blame] | 271 | glsl_type_size(const struct glsl_type *type, bool bindless) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 272 | { |
| 273 | return glsl_count_attribute_slots(type, false); |
| 274 | } |
| 275 | |
| 276 | /* Lower fdot2 to a vector multiplication followed by channel addition */ |
| 277 | static void |
| 278 | midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu) |
| 279 | { |
| 280 | if (alu->op != nir_op_fdot2) |
| 281 | return; |
| 282 | |
| 283 | b->cursor = nir_before_instr(&alu->instr); |
| 284 | |
| 285 | nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0); |
| 286 | nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1); |
| 287 | |
| 288 | nir_ssa_def *product = nir_fmul(b, src0, src1); |
| 289 | |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 290 | nir_ssa_def *sum = nir_fadd(b, |
| 291 | nir_channel(b, product, 0), |
| 292 | nir_channel(b, product, 1)); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 293 | |
| 294 | /* Replace the fdot2 with this sum */ |
| 295 | nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum)); |
| 296 | } |
| 297 | |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 298 | static int |
Alyssa Rosenzweig | 2efa025 | 2019-08-01 11:03:15 -0700 | [diff] [blame] | 299 | midgard_sysval_for_ssbo(nir_intrinsic_instr *instr) |
| 300 | { |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 301 | /* This is way too meta */ |
| 302 | bool is_store = instr->intrinsic == nir_intrinsic_store_ssbo; |
| 303 | unsigned idx_idx = is_store ? 1 : 0; |
| 304 | |
| 305 | nir_src index = instr->src[idx_idx]; |
Alyssa Rosenzweig | 2efa025 | 2019-08-01 11:03:15 -0700 | [diff] [blame] | 306 | assert(nir_src_is_const(index)); |
| 307 | uint32_t uindex = nir_src_as_uint(index); |
| 308 | |
| 309 | return PAN_SYSVAL(SSBO, uindex); |
| 310 | } |
| 311 | |
| 312 | static int |
Alyssa Rosenzweig | 4e07e7b | 2019-11-21 08:42:28 -0500 | [diff] [blame] | 313 | midgard_sysval_for_sampler(nir_intrinsic_instr *instr) |
| 314 | { |
| 315 | /* TODO: indirect samplers !!! */ |
| 316 | nir_src index = instr->src[0]; |
| 317 | assert(nir_src_is_const(index)); |
| 318 | uint32_t uindex = nir_src_as_uint(index); |
| 319 | |
| 320 | return PAN_SYSVAL(SAMPLER, uindex); |
| 321 | } |
| 322 | |
| 323 | static int |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 324 | midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr) |
| 325 | { |
| 326 | switch (instr->intrinsic) { |
| 327 | case nir_intrinsic_load_viewport_scale: |
| 328 | return PAN_SYSVAL_VIEWPORT_SCALE; |
| 329 | case nir_intrinsic_load_viewport_offset: |
| 330 | return PAN_SYSVAL_VIEWPORT_OFFSET; |
Alyssa Rosenzweig | 15954ab | 2019-08-06 14:07:10 -0700 | [diff] [blame] | 331 | case nir_intrinsic_load_num_work_groups: |
| 332 | return PAN_SYSVAL_NUM_WORK_GROUPS; |
Alyssa Rosenzweig | 2efa025 | 2019-08-01 11:03:15 -0700 | [diff] [blame] | 333 | case nir_intrinsic_load_ssbo: |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 334 | case nir_intrinsic_store_ssbo: |
Alyssa Rosenzweig | 2efa025 | 2019-08-01 11:03:15 -0700 | [diff] [blame] | 335 | return midgard_sysval_for_ssbo(instr); |
Alyssa Rosenzweig | 4e07e7b | 2019-11-21 08:42:28 -0500 | [diff] [blame] | 336 | case nir_intrinsic_load_sampler_lod_parameters_pan: |
| 337 | return midgard_sysval_for_sampler(instr); |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 338 | default: |
Alyssa Rosenzweig | 6189274 | 2019-08-21 09:15:56 -0700 | [diff] [blame] | 339 | return ~0; |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 340 | } |
| 341 | } |
| 342 | |
Boris Brezillon | bd49c8f | 2019-06-14 09:59:20 +0200 | [diff] [blame] | 343 | static int sysval_for_instr(compiler_context *ctx, nir_instr *instr, |
| 344 | unsigned *dest) |
| 345 | { |
| 346 | nir_intrinsic_instr *intr; |
| 347 | nir_dest *dst = NULL; |
Boris Brezillon | c355886 | 2019-06-17 22:13:04 +0200 | [diff] [blame] | 348 | nir_tex_instr *tex; |
Boris Brezillon | bd49c8f | 2019-06-14 09:59:20 +0200 | [diff] [blame] | 349 | int sysval = -1; |
| 350 | |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 351 | bool is_store = false; |
| 352 | |
Boris Brezillon | bd49c8f | 2019-06-14 09:59:20 +0200 | [diff] [blame] | 353 | switch (instr->type) { |
| 354 | case nir_instr_type_intrinsic: |
| 355 | intr = nir_instr_as_intrinsic(instr); |
| 356 | sysval = midgard_nir_sysval_for_intrinsic(intr); |
| 357 | dst = &intr->dest; |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 358 | is_store |= intr->intrinsic == nir_intrinsic_store_ssbo; |
Boris Brezillon | bd49c8f | 2019-06-14 09:59:20 +0200 | [diff] [blame] | 359 | break; |
Boris Brezillon | c355886 | 2019-06-17 22:13:04 +0200 | [diff] [blame] | 360 | case nir_instr_type_tex: |
| 361 | tex = nir_instr_as_tex(instr); |
| 362 | if (tex->op != nir_texop_txs) |
| 363 | break; |
| 364 | |
| 365 | sysval = PAN_SYSVAL(TEXTURE_SIZE, |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 366 | PAN_TXS_SYSVAL_ID(tex->texture_index, |
| 367 | nir_tex_instr_dest_size(tex) - |
| 368 | (tex->is_array ? 1 : 0), |
| 369 | tex->is_array)); |
Boris Brezillon | c355886 | 2019-06-17 22:13:04 +0200 | [diff] [blame] | 370 | dst = &tex->dest; |
| 371 | break; |
Boris Brezillon | bd49c8f | 2019-06-14 09:59:20 +0200 | [diff] [blame] | 372 | default: |
| 373 | break; |
| 374 | } |
| 375 | |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 376 | if (dest && dst && !is_store) |
Boris Brezillon | bd49c8f | 2019-06-14 09:59:20 +0200 | [diff] [blame] | 377 | *dest = nir_dest_index(ctx, dst); |
| 378 | |
| 379 | return sysval; |
| 380 | } |
| 381 | |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 382 | static void |
| 383 | midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr) |
| 384 | { |
Boris Brezillon | bd49c8f | 2019-06-14 09:59:20 +0200 | [diff] [blame] | 385 | int sysval; |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 386 | |
Boris Brezillon | bd49c8f | 2019-06-14 09:59:20 +0200 | [diff] [blame] | 387 | sysval = sysval_for_instr(ctx, instr, NULL); |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 388 | if (sysval < 0) |
| 389 | return; |
| 390 | |
| 391 | /* We have a sysval load; check if it's already been assigned */ |
| 392 | |
| 393 | if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval)) |
| 394 | return; |
| 395 | |
| 396 | /* It hasn't -- so assign it now! */ |
| 397 | |
| 398 | unsigned id = ctx->sysval_count++; |
| 399 | _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1)); |
| 400 | ctx->sysvals[id] = sysval; |
| 401 | } |
| 402 | |
| 403 | static void |
| 404 | midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader) |
| 405 | { |
| 406 | ctx->sysval_count = 0; |
| 407 | |
| 408 | nir_foreach_function(function, shader) { |
| 409 | if (!function->impl) continue; |
| 410 | |
| 411 | nir_foreach_block(block, function->impl) { |
| 412 | nir_foreach_instr_safe(instr, block) { |
| 413 | midgard_nir_assign_sysval_body(ctx, instr); |
| 414 | } |
| 415 | } |
| 416 | } |
| 417 | } |
| 418 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 419 | static bool |
| 420 | midgard_nir_lower_fdot2(nir_shader *shader) |
| 421 | { |
| 422 | bool progress = false; |
| 423 | |
| 424 | nir_foreach_function(function, shader) { |
| 425 | if (!function->impl) continue; |
| 426 | |
| 427 | nir_builder _b; |
| 428 | nir_builder *b = &_b; |
| 429 | nir_builder_init(b, function->impl); |
| 430 | |
| 431 | nir_foreach_block(block, function->impl) { |
| 432 | nir_foreach_instr_safe(instr, block) { |
| 433 | if (instr->type != nir_instr_type_alu) continue; |
| 434 | |
| 435 | nir_alu_instr *alu = nir_instr_as_alu(instr); |
| 436 | midgard_nir_lower_fdot2_body(b, alu); |
| 437 | |
| 438 | progress |= true; |
| 439 | } |
| 440 | } |
| 441 | |
| 442 | nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance); |
| 443 | |
| 444 | } |
| 445 | |
| 446 | return progress; |
| 447 | } |
| 448 | |
Alyssa Rosenzweig | a2f1a06 | 2019-07-08 12:40:34 -0700 | [diff] [blame] | 449 | /* Flushes undefined values to zero */ |
| 450 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 451 | static void |
Alyssa Rosenzweig | bda2bb3 | 2019-11-21 08:45:27 -0500 | [diff] [blame] | 452 | optimise_nir(nir_shader *nir, unsigned quirks) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 453 | { |
| 454 | bool progress; |
Ian Romanick | d41cdef | 2018-08-18 16:42:04 -0700 | [diff] [blame] | 455 | unsigned lower_flrp = |
| 456 | (nir->options->lower_flrp16 ? 16 : 0) | |
| 457 | (nir->options->lower_flrp32 ? 32 : 0) | |
| 458 | (nir->options->lower_flrp64 ? 64 : 0); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 459 | |
| 460 | NIR_PASS(progress, nir, nir_lower_regs_to_ssa); |
Rhys Perry | 8b98d09 | 2019-02-05 15:56:24 +0000 | [diff] [blame] | 461 | NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 462 | |
Alyssa Rosenzweig | 44a6c38 | 2019-08-14 08:44:40 -0700 | [diff] [blame] | 463 | nir_lower_tex_options lower_tex_options = { |
| 464 | .lower_txs_lod = true, |
Alyssa Rosenzweig | 4c43b35 | 2019-11-21 13:40:00 -0500 | [diff] [blame] | 465 | .lower_txp = ~0, |
| 466 | .lower_tex_without_implicit_lod = |
| 467 | (quirks & MIDGARD_EXPLICIT_LOD), |
Alyssa Rosenzweig | c57337b | 2019-12-19 11:12:50 -0500 | [diff] [blame] | 468 | |
| 469 | /* TODO: we have native gradient.. */ |
| 470 | .lower_txd = true, |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 471 | }; |
| 472 | |
Alyssa Rosenzweig | 44a6c38 | 2019-08-14 08:44:40 -0700 | [diff] [blame] | 473 | NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 474 | |
Alyssa Rosenzweig | c57337b | 2019-12-19 11:12:50 -0500 | [diff] [blame] | 475 | /* Must lower fdot2 after tex is lowered */ |
| 476 | NIR_PASS(progress, nir, midgard_nir_lower_fdot2); |
| 477 | |
Alyssa Rosenzweig | bda2bb3 | 2019-11-21 08:45:27 -0500 | [diff] [blame] | 478 | /* T720 is broken. */ |
| 479 | |
| 480 | if (quirks & MIDGARD_BROKEN_LOD) |
| 481 | NIR_PASS_V(nir, midgard_nir_lod_errata); |
| 482 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 483 | do { |
| 484 | progress = false; |
| 485 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 486 | NIR_PASS(progress, nir, nir_lower_var_copies); |
| 487 | NIR_PASS(progress, nir, nir_lower_vars_to_ssa); |
| 488 | |
| 489 | NIR_PASS(progress, nir, nir_copy_prop); |
Boris Brezillon | 440b0d6 | 2020-01-06 14:31:38 +0100 | [diff] [blame] | 490 | NIR_PASS(progress, nir, nir_opt_remove_phis); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 491 | NIR_PASS(progress, nir, nir_opt_dce); |
| 492 | NIR_PASS(progress, nir, nir_opt_dead_cf); |
| 493 | NIR_PASS(progress, nir, nir_opt_cse); |
| 494 | NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true); |
| 495 | NIR_PASS(progress, nir, nir_opt_algebraic); |
| 496 | NIR_PASS(progress, nir, nir_opt_constant_folding); |
Ian Romanick | d41cdef | 2018-08-18 16:42:04 -0700 | [diff] [blame] | 497 | |
| 498 | if (lower_flrp != 0) { |
Ian Romanick | 1f1007a | 2019-05-08 07:32:43 -0700 | [diff] [blame] | 499 | bool lower_flrp_progress = false; |
Ian Romanick | d41cdef | 2018-08-18 16:42:04 -0700 | [diff] [blame] | 500 | NIR_PASS(lower_flrp_progress, |
| 501 | nir, |
| 502 | nir_lower_flrp, |
| 503 | lower_flrp, |
| 504 | false /* always_precise */, |
| 505 | nir->options->lower_ffma); |
| 506 | if (lower_flrp_progress) { |
| 507 | NIR_PASS(progress, nir, |
| 508 | nir_opt_constant_folding); |
| 509 | progress = true; |
| 510 | } |
| 511 | |
| 512 | /* Nothing should rematerialize any flrps, so we only |
| 513 | * need to do this lowering once. |
| 514 | */ |
| 515 | lower_flrp = 0; |
| 516 | } |
| 517 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 518 | NIR_PASS(progress, nir, nir_opt_undef); |
Alyssa Rosenzweig | a2f1a06 | 2019-07-08 12:40:34 -0700 | [diff] [blame] | 519 | NIR_PASS(progress, nir, nir_undef_to_zero); |
| 520 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 521 | NIR_PASS(progress, nir, nir_opt_loop_unroll, |
| 522 | nir_var_shader_in | |
| 523 | nir_var_shader_out | |
| 524 | nir_var_function_temp); |
| 525 | |
Alyssa Rosenzweig | 9402970 | 2019-06-17 11:12:51 -0700 | [diff] [blame] | 526 | NIR_PASS(progress, nir, nir_opt_vectorize); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 527 | } while (progress); |
| 528 | |
| 529 | /* Must be run at the end to prevent creation of fsin/fcos ops */ |
| 530 | NIR_PASS(progress, nir, midgard_nir_scale_trig); |
| 531 | |
| 532 | do { |
| 533 | progress = false; |
| 534 | |
| 535 | NIR_PASS(progress, nir, nir_opt_dce); |
| 536 | NIR_PASS(progress, nir, nir_opt_algebraic); |
| 537 | NIR_PASS(progress, nir, nir_opt_constant_folding); |
| 538 | NIR_PASS(progress, nir, nir_copy_prop); |
| 539 | } while (progress); |
| 540 | |
| 541 | NIR_PASS(progress, nir, nir_opt_algebraic_late); |
Alyssa Rosenzweig | 726f026 | 2019-05-07 02:52:08 +0000 | [diff] [blame] | 542 | |
| 543 | /* We implement booleans as 32-bit 0/~0 */ |
| 544 | NIR_PASS(progress, nir, nir_lower_bool_to_int32); |
| 545 | |
| 546 | /* Now that booleans are lowered, we can run out late opts */ |
Alyssa Rosenzweig | effe6fb0 | 2019-03-25 02:49:04 +0000 | [diff] [blame] | 547 | NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 548 | |
Alyssa Rosenzweig | effe6fb0 | 2019-03-25 02:49:04 +0000 | [diff] [blame] | 549 | /* Lower mods for float ops only. Integer ops don't support modifiers |
| 550 | * (saturate doesn't make sense on integers, neg/abs require dedicated |
| 551 | * instructions) */ |
| 552 | |
| 553 | NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 554 | NIR_PASS(progress, nir, nir_copy_prop); |
| 555 | NIR_PASS(progress, nir, nir_opt_dce); |
| 556 | |
| 557 | /* Take us out of SSA */ |
| 558 | NIR_PASS(progress, nir, nir_lower_locals_to_regs); |
| 559 | NIR_PASS(progress, nir, nir_convert_from_ssa, true); |
| 560 | |
| 561 | /* We are a vector architecture; write combine where possible */ |
| 562 | NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest); |
| 563 | NIR_PASS(progress, nir, nir_lower_vec_to_movs); |
| 564 | |
| 565 | NIR_PASS(progress, nir, nir_opt_dce); |
| 566 | } |
| 567 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 568 | /* Do not actually emit a load; instead, cache the constant for inlining */ |
| 569 | |
| 570 | static void |
| 571 | emit_load_const(compiler_context *ctx, nir_load_const_instr *instr) |
| 572 | { |
| 573 | nir_ssa_def def = instr->def; |
| 574 | |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 575 | midgard_constants *consts = rzalloc(NULL, midgard_constants); |
| 576 | |
| 577 | assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8); |
| 578 | |
| 579 | #define RAW_CONST_COPY(bits) \ |
| 580 | nir_const_value_to_array(consts->u##bits, instr->value, \ |
| 581 | instr->def.num_components, u##bits) |
| 582 | |
| 583 | switch (instr->def.bit_size) { |
| 584 | case 64: |
| 585 | RAW_CONST_COPY(64); |
| 586 | break; |
| 587 | case 32: |
| 588 | RAW_CONST_COPY(32); |
| 589 | break; |
| 590 | case 16: |
| 591 | RAW_CONST_COPY(16); |
| 592 | break; |
| 593 | case 8: |
| 594 | RAW_CONST_COPY(8); |
| 595 | break; |
| 596 | default: |
| 597 | unreachable("Invalid bit_size for load_const instruction\n"); |
| 598 | } |
Alyssa Rosenzweig | 9beb339 | 2019-07-26 11:30:06 -0700 | [diff] [blame] | 599 | |
| 600 | /* Shifted for SSA, +1 for off-by-one */ |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 601 | _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 602 | } |
| 603 | |
Alyssa Rosenzweig | e169301 | 2019-07-24 12:52:27 -0700 | [diff] [blame] | 604 | /* Normally constants are embedded implicitly, but for I/O and such we have to |
| 605 | * explicitly emit a move with the constant source */ |
| 606 | |
| 607 | static void |
| 608 | emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to) |
| 609 | { |
| 610 | void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1); |
| 611 | |
| 612 | if (constant_value) { |
Alyssa Rosenzweig | c3a46e7 | 2019-10-30 16:29:28 -0400 | [diff] [blame] | 613 | midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to); |
Alyssa Rosenzweig | e169301 | 2019-07-24 12:52:27 -0700 | [diff] [blame] | 614 | attach_constants(ctx, &ins, constant_value, node + 1); |
| 615 | emit_mir_instruction(ctx, ins); |
| 616 | } |
| 617 | } |
| 618 | |
Alyssa Rosenzweig | 726f026 | 2019-05-07 02:52:08 +0000 | [diff] [blame] | 619 | static bool |
| 620 | nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components) |
| 621 | { |
| 622 | unsigned comp = src->swizzle[0]; |
| 623 | |
| 624 | for (unsigned c = 1; c < nr_components; ++c) { |
| 625 | if (src->swizzle[c] != comp) |
| 626 | return true; |
| 627 | } |
| 628 | |
| 629 | return false; |
| 630 | } |
| 631 | |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 632 | #define ALU_CASE(nir, _op) \ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 633 | case nir_op_##nir: \ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 634 | op = midgard_alu_op_##_op; \ |
Alyssa Rosenzweig | 0ed8cca | 2019-07-01 17:35:25 -0700 | [diff] [blame] | 635 | assert(src_bitsize == dst_bitsize); \ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 636 | break; |
Alyssa Rosenzweig | 195e297 | 2019-06-19 07:23:27 -0700 | [diff] [blame] | 637 | |
| 638 | #define ALU_CASE_BCAST(nir, _op, count) \ |
| 639 | case nir_op_##nir: \ |
| 640 | op = midgard_alu_op_##_op; \ |
| 641 | broadcast_swizzle = count; \ |
Alyssa Rosenzweig | 0ed8cca | 2019-07-01 17:35:25 -0700 | [diff] [blame] | 642 | assert(src_bitsize == dst_bitsize); \ |
Alyssa Rosenzweig | 195e297 | 2019-06-19 07:23:27 -0700 | [diff] [blame] | 643 | break; |
Alyssa Rosenzweig | 7bc91b4 | 2019-04-24 23:42:30 +0000 | [diff] [blame] | 644 | static bool |
| 645 | nir_is_fzero_constant(nir_src src) |
| 646 | { |
| 647 | if (!nir_src_is_const(src)) |
| 648 | return false; |
| 649 | |
| 650 | for (unsigned c = 0; c < nir_src_num_components(src); ++c) { |
| 651 | if (nir_src_comp_as_float(src, c) != 0.0) |
| 652 | return false; |
| 653 | } |
| 654 | |
| 655 | return true; |
| 656 | } |
| 657 | |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 658 | /* Analyze the sizes of the inputs to determine which reg mode. Ops needed |
| 659 | * special treatment override this anyway. */ |
Alyssa Rosenzweig | 4df80ca | 2019-07-01 15:26:22 -0700 | [diff] [blame] | 660 | |
| 661 | static midgard_reg_mode |
| 662 | reg_mode_for_nir(nir_alu_instr *instr) |
| 663 | { |
| 664 | unsigned src_bitsize = nir_src_bit_size(instr->src[0].src); |
| 665 | |
| 666 | switch (src_bitsize) { |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 667 | case 8: |
| 668 | return midgard_reg_mode_8; |
| 669 | case 16: |
| 670 | return midgard_reg_mode_16; |
| 671 | case 32: |
| 672 | return midgard_reg_mode_32; |
| 673 | case 64: |
| 674 | return midgard_reg_mode_64; |
| 675 | default: |
| 676 | unreachable("Invalid bit size"); |
Alyssa Rosenzweig | 4df80ca | 2019-07-01 15:26:22 -0700 | [diff] [blame] | 677 | } |
| 678 | } |
| 679 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 680 | static void |
| 681 | emit_alu(compiler_context *ctx, nir_alu_instr *instr) |
| 682 | { |
Alyssa Rosenzweig | 8f88732 | 2019-07-29 15:11:12 -0700 | [diff] [blame] | 683 | /* Derivatives end up emitted on the texture pipe, not the ALUs. This |
| 684 | * is handled elsewhere */ |
| 685 | |
| 686 | if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) { |
| 687 | midgard_emit_derivatives(ctx, instr); |
| 688 | return; |
| 689 | } |
| 690 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 691 | bool is_ssa = instr->dest.dest.is_ssa; |
| 692 | |
Alyssa Rosenzweig | 4ed23b1 | 2019-02-07 04:56:13 +0000 | [diff] [blame] | 693 | unsigned dest = nir_dest_index(ctx, &instr->dest.dest); |
Alyssa Rosenzweig | f42e5be | 2019-07-01 15:28:37 -0700 | [diff] [blame] | 694 | unsigned nr_components = nir_dest_num_components(instr->dest.dest); |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 695 | unsigned nr_inputs = nir_op_infos[instr->op].num_inputs; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 696 | |
| 697 | /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are |
| 698 | * supported. A few do not and are commented for now. Also, there are a |
| 699 | * number of NIR ops which Midgard does not support and need to be |
| 700 | * lowered, also TODO. This switch block emits the opcode and calling |
| 701 | * convention of the Midgard instruction; actual packing is done in |
| 702 | * emit_alu below */ |
| 703 | |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 704 | unsigned op; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 705 | |
Alyssa Rosenzweig | 195e297 | 2019-06-19 07:23:27 -0700 | [diff] [blame] | 706 | /* Number of components valid to check for the instruction (the rest |
| 707 | * will be forced to the last), or 0 to use as-is. Relevant as |
| 708 | * ball-type instructions have a channel count in NIR but are all vec4 |
| 709 | * in Midgard */ |
| 710 | |
| 711 | unsigned broadcast_swizzle = 0; |
| 712 | |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 713 | /* What register mode should we operate in? */ |
| 714 | midgard_reg_mode reg_mode = |
| 715 | reg_mode_for_nir(instr); |
| 716 | |
Alyssa Rosenzweig | 4df80ca | 2019-07-01 15:26:22 -0700 | [diff] [blame] | 717 | /* Do we need a destination override? Used for inline |
| 718 | * type conversion */ |
| 719 | |
| 720 | midgard_dest_override dest_override = |
| 721 | midgard_dest_override_none; |
| 722 | |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 723 | /* Should we use a smaller respective source and sign-extend? */ |
| 724 | |
| 725 | bool half_1 = false, sext_1 = false; |
| 726 | bool half_2 = false, sext_2 = false; |
| 727 | |
Alyssa Rosenzweig | 0ed8cca | 2019-07-01 17:35:25 -0700 | [diff] [blame] | 728 | unsigned src_bitsize = nir_src_bit_size(instr->src[0].src); |
| 729 | unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest); |
| 730 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 731 | switch (instr->op) { |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 732 | ALU_CASE(fadd, fadd); |
| 733 | ALU_CASE(fmul, fmul); |
| 734 | ALU_CASE(fmin, fmin); |
| 735 | ALU_CASE(fmax, fmax); |
| 736 | ALU_CASE(imin, imin); |
| 737 | ALU_CASE(imax, imax); |
Alyssa Rosenzweig | 2e7555b | 2019-04-05 05:16:54 +0000 | [diff] [blame] | 738 | ALU_CASE(umin, umin); |
| 739 | ALU_CASE(umax, umax); |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 740 | ALU_CASE(ffloor, ffloor); |
Alyssa Rosenzweig | c6be996 | 2019-02-23 01:12:10 +0000 | [diff] [blame] | 741 | ALU_CASE(fround_even, froundeven); |
| 742 | ALU_CASE(ftrunc, ftrunc); |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 743 | ALU_CASE(fceil, fceil); |
| 744 | ALU_CASE(fdot3, fdot3); |
| 745 | ALU_CASE(fdot4, fdot4); |
| 746 | ALU_CASE(iadd, iadd); |
| 747 | ALU_CASE(isub, isub); |
| 748 | ALU_CASE(imul, imul); |
Alyssa Rosenzweig | 9f14e20 | 2019-06-05 15:18:35 +0000 | [diff] [blame] | 749 | |
| 750 | /* Zero shoved as second-arg */ |
| 751 | ALU_CASE(iabs, iabsdiff); |
| 752 | |
Jason Ekstrand | f2dc0f2 | 2019-05-06 11:45:46 -0500 | [diff] [blame] | 753 | ALU_CASE(mov, imov); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 754 | |
Alyssa Rosenzweig | 3fb8842 | 2019-03-25 00:25:01 +0000 | [diff] [blame] | 755 | ALU_CASE(feq32, feq); |
| 756 | ALU_CASE(fne32, fne); |
| 757 | ALU_CASE(flt32, flt); |
| 758 | ALU_CASE(ieq32, ieq); |
| 759 | ALU_CASE(ine32, ine); |
| 760 | ALU_CASE(ilt32, ilt); |
Alyssa Rosenzweig | b8739c2 | 2019-03-26 04:00:33 +0000 | [diff] [blame] | 761 | ALU_CASE(ult32, ult); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 762 | |
Alyssa Rosenzweig | 3208c9d | 2019-03-25 01:13:12 +0000 | [diff] [blame] | 763 | /* We don't have a native b2f32 instruction. Instead, like many |
| 764 | * GPUs, we exploit booleans as 0/~0 for false/true, and |
| 765 | * correspondingly AND |
| 766 | * by 1.0 to do the type conversion. For the moment, prime us |
| 767 | * to emit: |
| 768 | * |
| 769 | * iand [whatever], #0 |
| 770 | * |
| 771 | * At the end of emit_alu (as MIR), we'll fix-up the constant |
| 772 | */ |
| 773 | |
| 774 | ALU_CASE(b2f32, iand); |
| 775 | ALU_CASE(b2i32, iand); |
| 776 | |
Alyssa Rosenzweig | ae43b8f | 2019-03-25 00:53:46 +0000 | [diff] [blame] | 777 | /* Likewise, we don't have a dedicated f2b32 instruction, but |
Alyssa Rosenzweig | 3208c9d | 2019-03-25 01:13:12 +0000 | [diff] [blame] | 778 | * we can do a "not equal to 0.0" test. */ |
Alyssa Rosenzweig | ae43b8f | 2019-03-25 00:53:46 +0000 | [diff] [blame] | 779 | |
| 780 | ALU_CASE(f2b32, fne); |
Alyssa Rosenzweig | 5b95fef | 2019-03-25 00:56:48 +0000 | [diff] [blame] | 781 | ALU_CASE(i2b32, ine); |
Alyssa Rosenzweig | ae43b8f | 2019-03-25 00:53:46 +0000 | [diff] [blame] | 782 | |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 783 | ALU_CASE(frcp, frcp); |
| 784 | ALU_CASE(frsq, frsqrt); |
| 785 | ALU_CASE(fsqrt, fsqrt); |
| 786 | ALU_CASE(fexp2, fexp2); |
| 787 | ALU_CASE(flog2, flog2); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 788 | |
Boris Brezillon | fcceeaf | 2020-01-20 22:05:14 +0100 | [diff] [blame] | 789 | ALU_CASE(f2i64, f2i_rtz); |
| 790 | ALU_CASE(f2u64, f2u_rtz); |
| 791 | ALU_CASE(i2f64, i2f_rtz); |
| 792 | ALU_CASE(u2f64, u2f_rtz); |
| 793 | |
Alyssa Rosenzweig | 73bf669 | 2019-06-05 15:03:02 -0700 | [diff] [blame] | 794 | ALU_CASE(f2i32, f2i_rtz); |
| 795 | ALU_CASE(f2u32, f2u_rtz); |
| 796 | ALU_CASE(i2f32, i2f_rtz); |
| 797 | ALU_CASE(u2f32, u2f_rtz); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 798 | |
Alyssa Rosenzweig | d8c084d | 2019-07-01 17:41:20 -0700 | [diff] [blame] | 799 | ALU_CASE(f2i16, f2i_rtz); |
| 800 | ALU_CASE(f2u16, f2u_rtz); |
| 801 | ALU_CASE(i2f16, i2f_rtz); |
| 802 | ALU_CASE(u2f16, u2f_rtz); |
| 803 | |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 804 | ALU_CASE(fsin, fsin); |
| 805 | ALU_CASE(fcos, fcos); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 806 | |
Alyssa Rosenzweig | 159abd5 | 2019-07-26 11:15:31 -0700 | [diff] [blame] | 807 | /* We'll set invert */ |
| 808 | ALU_CASE(inot, imov); |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 809 | ALU_CASE(iand, iand); |
| 810 | ALU_CASE(ior, ior); |
| 811 | ALU_CASE(ixor, ixor); |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 812 | ALU_CASE(ishl, ishl); |
| 813 | ALU_CASE(ishr, iasr); |
| 814 | ALU_CASE(ushr, ilsr); |
| 815 | |
Alyssa Rosenzweig | 195e297 | 2019-06-19 07:23:27 -0700 | [diff] [blame] | 816 | ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2); |
| 817 | ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3); |
Alyssa Rosenzweig | 3fb8842 | 2019-03-25 00:25:01 +0000 | [diff] [blame] | 818 | ALU_CASE(b32all_fequal4, fball_eq); |
Alyssa Rosenzweig | 5366410 | 2019-03-25 00:12:06 +0000 | [diff] [blame] | 819 | |
Alyssa Rosenzweig | 195e297 | 2019-06-19 07:23:27 -0700 | [diff] [blame] | 820 | ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2); |
| 821 | ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3); |
Alyssa Rosenzweig | 3fb8842 | 2019-03-25 00:25:01 +0000 | [diff] [blame] | 822 | ALU_CASE(b32any_fnequal4, fbany_neq); |
Alyssa Rosenzweig | 5366410 | 2019-03-25 00:12:06 +0000 | [diff] [blame] | 823 | |
Alyssa Rosenzweig | 195e297 | 2019-06-19 07:23:27 -0700 | [diff] [blame] | 824 | ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2); |
| 825 | ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3); |
Alyssa Rosenzweig | 3fb8842 | 2019-03-25 00:25:01 +0000 | [diff] [blame] | 826 | ALU_CASE(b32all_iequal4, iball_eq); |
Alyssa Rosenzweig | 5366410 | 2019-03-25 00:12:06 +0000 | [diff] [blame] | 827 | |
Alyssa Rosenzweig | 195e297 | 2019-06-19 07:23:27 -0700 | [diff] [blame] | 828 | ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2); |
| 829 | ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3); |
Alyssa Rosenzweig | 3fb8842 | 2019-03-25 00:25:01 +0000 | [diff] [blame] | 830 | ALU_CASE(b32any_inequal4, ibany_neq); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 831 | |
Alyssa Rosenzweig | 659aa3d | 2019-05-26 03:16:37 +0000 | [diff] [blame] | 832 | /* Source mods will be shoved in later */ |
| 833 | ALU_CASE(fabs, fmov); |
| 834 | ALU_CASE(fneg, fmov); |
| 835 | ALU_CASE(fsat, fmov); |
| 836 | |
Alyssa Rosenzweig | 4df80ca | 2019-07-01 15:26:22 -0700 | [diff] [blame] | 837 | /* For size conversion, we use a move. Ideally though we would squash |
| 838 | * these ops together; maybe that has to happen after in NIR as part of |
| 839 | * propagation...? An earlier algebraic pass ensured we step down by |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 840 | * only / exactly one size. If stepping down, we use a dest override to |
| 841 | * reduce the size; if stepping up, we use a larger-sized move with a |
| 842 | * half source and a sign/zero-extension modifier */ |
Alyssa Rosenzweig | 4df80ca | 2019-07-01 15:26:22 -0700 | [diff] [blame] | 843 | |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 844 | case nir_op_i2i8: |
| 845 | case nir_op_i2i16: |
| 846 | case nir_op_i2i32: |
Alyssa Rosenzweig | 2655a30 | 2019-11-04 22:21:20 -0500 | [diff] [blame] | 847 | case nir_op_i2i64: |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 848 | /* If we end up upscale, we'll need a sign-extend on the |
| 849 | * operand (the second argument) */ |
| 850 | |
| 851 | sext_2 = true; |
Alyssa Rosenzweig | 14a2032f | 2019-08-21 09:20:17 -0700 | [diff] [blame] | 852 | /* fallthrough */ |
Alyssa Rosenzweig | 4df80ca | 2019-07-01 15:26:22 -0700 | [diff] [blame] | 853 | case nir_op_u2u8: |
| 854 | case nir_op_u2u16: |
Alyssa Rosenzweig | 2655a30 | 2019-11-04 22:21:20 -0500 | [diff] [blame] | 855 | case nir_op_u2u32: |
Boris Brezillon | f53a079 | 2020-01-20 16:03:52 +0100 | [diff] [blame] | 856 | case nir_op_u2u64: |
| 857 | case nir_op_f2f16: |
Boris Brezillon | e1f9e8d | 2020-01-20 16:05:31 +0100 | [diff] [blame] | 858 | case nir_op_f2f32: |
| 859 | case nir_op_f2f64: { |
| 860 | if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 || |
| 861 | instr->op == nir_op_f2f64) |
Boris Brezillon | f53a079 | 2020-01-20 16:03:52 +0100 | [diff] [blame] | 862 | op = midgard_alu_op_fmov; |
| 863 | else |
| 864 | op = midgard_alu_op_imov; |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 865 | |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 866 | if (dst_bitsize == (src_bitsize * 2)) { |
| 867 | /* Converting up */ |
| 868 | half_2 = true; |
| 869 | |
| 870 | /* Use a greater register mode */ |
| 871 | reg_mode++; |
| 872 | } else if (src_bitsize == (dst_bitsize * 2)) { |
| 873 | /* Converting down */ |
| 874 | dest_override = midgard_dest_override_lower; |
| 875 | } |
| 876 | |
Alyssa Rosenzweig | 4df80ca | 2019-07-01 15:26:22 -0700 | [diff] [blame] | 877 | break; |
| 878 | } |
| 879 | |
Alyssa Rosenzweig | 7b78af8 | 2019-03-26 04:01:33 +0000 | [diff] [blame] | 880 | /* For greater-or-equal, we lower to less-or-equal and flip the |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 881 | * arguments */ |
| 882 | |
Alyssa Rosenzweig | 7b78af8 | 2019-03-26 04:01:33 +0000 | [diff] [blame] | 883 | case nir_op_fge: |
| 884 | case nir_op_fge32: |
| 885 | case nir_op_ige32: |
| 886 | case nir_op_uge32: { |
| 887 | op = |
| 888 | instr->op == nir_op_fge ? midgard_alu_op_fle : |
| 889 | instr->op == nir_op_fge32 ? midgard_alu_op_fle : |
| 890 | instr->op == nir_op_ige32 ? midgard_alu_op_ile : |
| 891 | instr->op == nir_op_uge32 ? midgard_alu_op_ule : |
| 892 | 0; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 893 | |
| 894 | /* Swap via temporary */ |
| 895 | nir_alu_src temp = instr->src[1]; |
| 896 | instr->src[1] = instr->src[0]; |
| 897 | instr->src[0] = temp; |
| 898 | |
| 899 | break; |
| 900 | } |
| 901 | |
Alyssa Rosenzweig | 3fb8842 | 2019-03-25 00:25:01 +0000 | [diff] [blame] | 902 | case nir_op_b32csel: { |
Alyssa Rosenzweig | 726f026 | 2019-05-07 02:52:08 +0000 | [diff] [blame] | 903 | /* Midgard features both fcsel and icsel, depending on |
| 904 | * the type of the arguments/output. However, as long |
| 905 | * as we're careful we can _always_ use icsel and |
| 906 | * _never_ need fcsel, since the latter does additional |
| 907 | * floating-point-specific processing whereas the |
| 908 | * former just moves bits on the wire. It's not obvious |
| 909 | * why these are separate opcodes, save for the ability |
| 910 | * to do things like sat/pos/abs/neg for free */ |
Alyssa Rosenzweig | 3d7874c | 2019-05-03 01:54:16 +0000 | [diff] [blame] | 911 | |
Alyssa Rosenzweig | 726f026 | 2019-05-07 02:52:08 +0000 | [diff] [blame] | 912 | bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components); |
| 913 | op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 914 | |
Alyssa Rosenzweig | 726f026 | 2019-05-07 02:52:08 +0000 | [diff] [blame] | 915 | /* The condition is the first argument; move the other |
| 916 | * arguments up one to be a binary instruction for |
Alyssa Rosenzweig | d3b3daa | 2019-09-23 08:00:51 -0400 | [diff] [blame] | 917 | * Midgard with the condition last */ |
Alyssa Rosenzweig | 8b15f8a | 2019-04-21 00:09:13 +0000 | [diff] [blame] | 918 | |
Alyssa Rosenzweig | d3b3daa | 2019-09-23 08:00:51 -0400 | [diff] [blame] | 919 | nir_alu_src temp = instr->src[2]; |
| 920 | |
| 921 | instr->src[2] = instr->src[0]; |
| 922 | instr->src[0] = instr->src[1]; |
| 923 | instr->src[1] = temp; |
| 924 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 925 | break; |
| 926 | } |
| 927 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 928 | default: |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 929 | DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 930 | assert(0); |
| 931 | return; |
| 932 | } |
| 933 | |
Alyssa Rosenzweig | 0a13bab | 2019-05-15 01:16:51 +0000 | [diff] [blame] | 934 | /* Midgard can perform certain modifiers on output of an ALU op */ |
Alyssa Rosenzweig | 6780481 | 2019-06-05 15:17:45 -0700 | [diff] [blame] | 935 | unsigned outmod; |
Alyssa Rosenzweig | 7bc91b4 | 2019-04-24 23:42:30 +0000 | [diff] [blame] | 936 | |
Alyssa Rosenzweig | 6780481 | 2019-06-05 15:17:45 -0700 | [diff] [blame] | 937 | if (midgard_is_integer_out_op(op)) { |
| 938 | outmod = midgard_outmod_int_wrap; |
| 939 | } else { |
| 940 | bool sat = instr->dest.saturate || instr->op == nir_op_fsat; |
| 941 | outmod = sat ? midgard_outmod_sat : midgard_outmod_none; |
| 942 | } |
Alyssa Rosenzweig | 659aa3d | 2019-05-26 03:16:37 +0000 | [diff] [blame] | 943 | |
Alyssa Rosenzweig | 7bc91b4 | 2019-04-24 23:42:30 +0000 | [diff] [blame] | 944 | /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */ |
| 945 | |
| 946 | if (instr->op == nir_op_fmax) { |
| 947 | if (nir_is_fzero_constant(instr->src[0].src)) { |
| 948 | op = midgard_alu_op_fmov; |
| 949 | nr_inputs = 1; |
| 950 | outmod = midgard_outmod_pos; |
| 951 | instr->src[0] = instr->src[1]; |
| 952 | } else if (nir_is_fzero_constant(instr->src[1].src)) { |
| 953 | op = midgard_alu_op_fmov; |
| 954 | nr_inputs = 1; |
| 955 | outmod = midgard_outmod_pos; |
| 956 | } |
| 957 | } |
| 958 | |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 959 | /* Fetch unit, quirks, etc information */ |
Alyssa Rosenzweig | 1f345bc | 2019-04-24 01:15:15 +0000 | [diff] [blame] | 960 | unsigned opcode_props = alu_opcode_props[op].props; |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 961 | bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 962 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 963 | /* src0 will always exist afaik, but src1 will not for 1-argument |
| 964 | * instructions. The latter can only be fetched if the instruction |
| 965 | * needs it, or else we may segfault. */ |
| 966 | |
Alyssa Rosenzweig | 4ed23b1 | 2019-02-07 04:56:13 +0000 | [diff] [blame] | 967 | unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]); |
Alyssa Rosenzweig | 8e36996 | 2019-08-30 10:42:05 -0700 | [diff] [blame] | 968 | unsigned src1 = nr_inputs >= 2 ? nir_alu_src_index(ctx, &instr->src[1]) : ~0; |
| 969 | unsigned src2 = nr_inputs == 3 ? nir_alu_src_index(ctx, &instr->src[2]) : ~0; |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 970 | assert(nr_inputs <= 3); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 971 | |
| 972 | /* Rather than use the instruction generation helpers, we do it |
| 973 | * ourselves here to avoid the mess */ |
| 974 | |
| 975 | midgard_instruction ins = { |
| 976 | .type = TAG_ALU_4, |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 977 | .src = { |
| 978 | quirk_flipped_r24 ? ~0 : src0, |
| 979 | quirk_flipped_r24 ? src0 : src1, |
Alyssa Rosenzweig | 8e36996 | 2019-08-30 10:42:05 -0700 | [diff] [blame] | 980 | src2, |
Alyssa Rosenzweig | ccbc9a4 | 2019-12-19 10:35:18 -0500 | [diff] [blame] | 981 | ~0 |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 982 | }, |
| 983 | .dest = dest, |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 984 | }; |
| 985 | |
Alyssa Rosenzweig | 8e36996 | 2019-08-30 10:42:05 -0700 | [diff] [blame] | 986 | nir_alu_src *nirmods[3] = { NULL }; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 987 | |
Alyssa Rosenzweig | 8e36996 | 2019-08-30 10:42:05 -0700 | [diff] [blame] | 988 | if (nr_inputs >= 2) { |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 989 | nirmods[0] = &instr->src[0]; |
| 990 | nirmods[1] = &instr->src[1]; |
| 991 | } else if (nr_inputs == 1) { |
| 992 | nirmods[quirk_flipped_r24] = &instr->src[0]; |
| 993 | } else { |
| 994 | assert(0); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 995 | } |
| 996 | |
Alyssa Rosenzweig | 8e36996 | 2019-08-30 10:42:05 -0700 | [diff] [blame] | 997 | if (nr_inputs == 3) |
| 998 | nirmods[2] = &instr->src[2]; |
| 999 | |
Alyssa Rosenzweig | 659aa3d | 2019-05-26 03:16:37 +0000 | [diff] [blame] | 1000 | /* These were lowered to a move, so apply the corresponding mod */ |
| 1001 | |
| 1002 | if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) { |
| 1003 | nir_alu_src *s = nirmods[quirk_flipped_r24]; |
| 1004 | |
| 1005 | if (instr->op == nir_op_fneg) |
| 1006 | s->negate = !s->negate; |
| 1007 | |
| 1008 | if (instr->op == nir_op_fabs) |
| 1009 | s->abs = !s->abs; |
| 1010 | } |
| 1011 | |
Alyssa Rosenzweig | fcdfb67 | 2019-04-22 03:25:42 +0000 | [diff] [blame] | 1012 | bool is_int = midgard_is_integer_op(op); |
| 1013 | |
Alyssa Rosenzweig | f8b18a4 | 2019-07-01 18:51:48 -0700 | [diff] [blame] | 1014 | ins.mask = mask_of(nr_components); |
| 1015 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1016 | midgard_vector_alu alu = { |
| 1017 | .op = op, |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 1018 | .reg_mode = reg_mode, |
Alyssa Rosenzweig | 4df80ca | 2019-07-01 15:26:22 -0700 | [diff] [blame] | 1019 | .dest_override = dest_override, |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1020 | .outmod = outmod, |
| 1021 | |
Alyssa Rosenzweig | 7f807ef | 2019-07-01 16:44:00 -0700 | [diff] [blame] | 1022 | .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)), |
| 1023 | .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)), |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1024 | }; |
| 1025 | |
| 1026 | /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */ |
| 1027 | |
| 1028 | if (!is_ssa) |
Alyssa Rosenzweig | f8b18a4 | 2019-07-01 18:51:48 -0700 | [diff] [blame] | 1029 | ins.mask &= instr->dest.write_mask; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1030 | |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1031 | for (unsigned m = 0; m < 3; ++m) { |
| 1032 | if (!nirmods[m]) |
| 1033 | continue; |
| 1034 | |
| 1035 | for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) |
| 1036 | ins.swizzle[m][c] = nirmods[m]->swizzle[c]; |
| 1037 | |
| 1038 | /* Replicate. TODO: remove when vec16 lands */ |
| 1039 | for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c) |
| 1040 | ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1]; |
| 1041 | } |
| 1042 | |
| 1043 | if (nr_inputs == 3) { |
| 1044 | /* Conditions can't have mods */ |
| 1045 | assert(!nirmods[2]->abs); |
| 1046 | assert(!nirmods[2]->negate); |
| 1047 | } |
| 1048 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1049 | ins.alu = alu; |
| 1050 | |
| 1051 | /* Late fixup for emulated instructions */ |
| 1052 | |
Alyssa Rosenzweig | 3208c9d | 2019-03-25 01:13:12 +0000 | [diff] [blame] | 1053 | if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) { |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1054 | /* Presently, our second argument is an inline #0 constant. |
| 1055 | * Switch over to an embedded 1.0 constant (that can't fit |
| 1056 | * inline, since we're 32-bit, not 16-bit like the inline |
| 1057 | * constants) */ |
| 1058 | |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 1059 | ins.has_inline_constant = false; |
| 1060 | ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1061 | ins.has_constants = true; |
Alyssa Rosenzweig | 9da4603 | 2019-03-24 16:07:31 +0000 | [diff] [blame] | 1062 | |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 1063 | if (instr->op == nir_op_b2f32) |
| 1064 | ins.constants.f32[0] = 1.0f; |
| 1065 | else |
| 1066 | ins.constants.i32[0] = 1; |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1067 | |
| 1068 | for (unsigned c = 0; c < 16; ++c) |
| 1069 | ins.swizzle[1][c] = 0; |
Alyssa Rosenzweig | 88c5979 | 2019-06-05 15:24:51 +0000 | [diff] [blame] | 1070 | } else if (nr_inputs == 1 && !quirk_flipped_r24) { |
| 1071 | /* Lots of instructions need a 0 plonked in */ |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 1072 | ins.has_inline_constant = false; |
| 1073 | ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); |
Alyssa Rosenzweig | 3208c9d | 2019-03-25 01:13:12 +0000 | [diff] [blame] | 1074 | ins.has_constants = true; |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 1075 | ins.constants.u32[0] = 0; |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1076 | |
| 1077 | for (unsigned c = 0; c < 16; ++c) |
| 1078 | ins.swizzle[1][c] = 0; |
Alyssa Rosenzweig | bcabcfe | 2019-04-25 04:25:33 +0000 | [diff] [blame] | 1079 | } else if (instr->op == nir_op_inot) { |
Alyssa Rosenzweig | 159abd5 | 2019-07-26 11:15:31 -0700 | [diff] [blame] | 1080 | ins.invert = true; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1081 | } |
| 1082 | |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 1083 | if ((opcode_props & UNITS_ALL) == UNIT_VLUT) { |
| 1084 | /* To avoid duplicating the lookup tables (probably), true LUT |
| 1085 | * instructions can only operate as if they were scalars. Lower |
| 1086 | * them here by changing the component. */ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1087 | |
Alyssa Rosenzweig | f8b18a4 | 2019-07-01 18:51:48 -0700 | [diff] [blame] | 1088 | unsigned orig_mask = ins.mask; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1089 | |
| 1090 | for (int i = 0; i < nr_components; ++i) { |
Alyssa Rosenzweig | 2c9e124 | 2019-06-17 11:49:44 -0700 | [diff] [blame] | 1091 | /* Mask the associated component, dropping the |
| 1092 | * instruction if needed */ |
| 1093 | |
Alyssa Rosenzweig | f8b18a4 | 2019-07-01 18:51:48 -0700 | [diff] [blame] | 1094 | ins.mask = 1 << i; |
| 1095 | ins.mask &= orig_mask; |
Alyssa Rosenzweig | 2c9e124 | 2019-06-17 11:49:44 -0700 | [diff] [blame] | 1096 | |
Alyssa Rosenzweig | f8b18a4 | 2019-07-01 18:51:48 -0700 | [diff] [blame] | 1097 | if (!ins.mask) |
Alyssa Rosenzweig | 2c9e124 | 2019-06-17 11:49:44 -0700 | [diff] [blame] | 1098 | continue; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1099 | |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1100 | for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j) |
| 1101 | ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1102 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1103 | emit_mir_instruction(ctx, ins); |
| 1104 | } |
| 1105 | } else { |
| 1106 | emit_mir_instruction(ctx, ins); |
| 1107 | } |
| 1108 | } |
| 1109 | |
Alyssa Rosenzweig | 97dcad8 | 2019-02-07 03:39:25 +0000 | [diff] [blame] | 1110 | #undef ALU_CASE |
| 1111 | |
Alyssa Rosenzweig | 1798f6b | 2019-11-15 15:16:53 -0500 | [diff] [blame] | 1112 | static void |
| 1113 | mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read) |
Alyssa Rosenzweig | 65e6cb4 | 2019-08-13 09:11:48 -0700 | [diff] [blame] | 1114 | { |
| 1115 | nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); |
Alyssa Rosenzweig | 1798f6b | 2019-11-15 15:16:53 -0500 | [diff] [blame] | 1116 | unsigned nir_mask = 0; |
| 1117 | unsigned dsize = 0; |
Alyssa Rosenzweig | 65e6cb4 | 2019-08-13 09:11:48 -0700 | [diff] [blame] | 1118 | |
Alyssa Rosenzweig | 1798f6b | 2019-11-15 15:16:53 -0500 | [diff] [blame] | 1119 | if (is_read) { |
| 1120 | nir_mask = mask_of(nir_intrinsic_dest_components(intr)); |
| 1121 | dsize = nir_dest_bit_size(intr->dest); |
| 1122 | } else { |
| 1123 | nir_mask = nir_intrinsic_write_mask(intr); |
| 1124 | dsize = 32; |
| 1125 | } |
| 1126 | |
| 1127 | /* Once we have the NIR mask, we need to normalize to work in 32-bit space */ |
| 1128 | unsigned bytemask = mir_to_bytemask(mir_mode_for_destsize(dsize), nir_mask); |
| 1129 | mir_set_bytemask(ins, bytemask); |
| 1130 | |
| 1131 | if (dsize == 64) |
| 1132 | ins->load_64 = true; |
Alyssa Rosenzweig | 65e6cb4 | 2019-08-13 09:11:48 -0700 | [diff] [blame] | 1133 | } |
| 1134 | |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1135 | /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly |
| 1136 | * optimized) versions of UBO #0 */ |
| 1137 | |
Alyssa Rosenzweig | 59d30fd | 2020-01-10 17:47:57 -0500 | [diff] [blame] | 1138 | static midgard_instruction * |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1139 | emit_ubo_read( |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1140 | compiler_context *ctx, |
Alyssa Rosenzweig | 65e6cb4 | 2019-08-13 09:11:48 -0700 | [diff] [blame] | 1141 | nir_instr *instr, |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1142 | unsigned dest, |
| 1143 | unsigned offset, |
| 1144 | nir_src *indirect_offset, |
Alyssa Rosenzweig | 59d30fd | 2020-01-10 17:47:57 -0500 | [diff] [blame] | 1145 | unsigned indirect_shift, |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1146 | unsigned index) |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1147 | { |
| 1148 | /* TODO: half-floats */ |
| 1149 | |
Alyssa Rosenzweig | bc9a7d0 | 2019-11-15 14:19:34 -0500 | [diff] [blame] | 1150 | midgard_instruction ins = m_ld_ubo_int4(dest, 0); |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 1151 | ins.constants.u32[0] = offset; |
Alyssa Rosenzweig | da73651 | 2019-12-19 11:12:25 -0500 | [diff] [blame] | 1152 | |
| 1153 | if (instr->type == nir_instr_type_intrinsic) |
| 1154 | mir_set_intr_mask(instr, &ins, true); |
Alyssa Rosenzweig | 3174bc9 | 2019-07-16 14:10:08 -0700 | [diff] [blame] | 1155 | |
| 1156 | if (indirect_offset) { |
Alyssa Rosenzweig | e7fd14c | 2019-10-26 15:50:38 -0400 | [diff] [blame] | 1157 | ins.src[2] = nir_src_index(ctx, indirect_offset); |
Alyssa Rosenzweig | 59d30fd | 2020-01-10 17:47:57 -0500 | [diff] [blame] | 1158 | ins.load_store.arg_2 = (indirect_shift << 5); |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1159 | } else { |
Alyssa Rosenzweig | c908772 | 2019-08-01 13:29:01 -0700 | [diff] [blame] | 1160 | ins.load_store.arg_2 = 0x1E; |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1161 | } |
Alyssa Rosenzweig | 3174bc9 | 2019-07-16 14:10:08 -0700 | [diff] [blame] | 1162 | |
Alyssa Rosenzweig | c908772 | 2019-08-01 13:29:01 -0700 | [diff] [blame] | 1163 | ins.load_store.arg_1 = index; |
| 1164 | |
Alyssa Rosenzweig | e7ac46b | 2019-08-02 17:09:54 -0700 | [diff] [blame] | 1165 | return emit_mir_instruction(ctx, ins); |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1166 | } |
| 1167 | |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1168 | /* SSBO reads are like UBO reads if you squint */ |
| 1169 | |
| 1170 | static void |
| 1171 | emit_ssbo_access( |
| 1172 | compiler_context *ctx, |
| 1173 | nir_instr *instr, |
| 1174 | bool is_read, |
| 1175 | unsigned srcdest, |
| 1176 | unsigned offset, |
| 1177 | nir_src *indirect_offset, |
| 1178 | unsigned index) |
| 1179 | { |
| 1180 | /* TODO: types */ |
| 1181 | |
| 1182 | midgard_instruction ins; |
| 1183 | |
| 1184 | if (is_read) |
| 1185 | ins = m_ld_int4(srcdest, offset); |
| 1186 | else |
| 1187 | ins = m_st_int4(srcdest, offset); |
| 1188 | |
| 1189 | /* SSBO reads use a generic memory read interface, so we need the |
| 1190 | * address of the SSBO as the first argument. This is a sysval. */ |
| 1191 | |
| 1192 | unsigned addr = make_compiler_temp(ctx); |
| 1193 | emit_sysval_read(ctx, instr, addr, 2); |
| 1194 | |
Alyssa Rosenzweig | e7fd14c | 2019-10-26 15:50:38 -0400 | [diff] [blame] | 1195 | /* The source array: |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1196 | * |
Alyssa Rosenzweig | e7fd14c | 2019-10-26 15:50:38 -0400 | [diff] [blame] | 1197 | * src[0] = store ? value : unused |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1198 | * src[1] = arg_1 |
| 1199 | * src[2] = arg_2 |
| 1200 | * |
| 1201 | * We would like arg_1 = the address and |
| 1202 | * arg_2 = the offset. |
| 1203 | */ |
| 1204 | |
Alyssa Rosenzweig | e7fd14c | 2019-10-26 15:50:38 -0400 | [diff] [blame] | 1205 | ins.src[1] = addr; |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1206 | |
| 1207 | /* TODO: What is this? It looks superficially like a shift << 5, but |
Alyssa Rosenzweig | 1a4153b | 2019-08-30 17:29:17 -0700 | [diff] [blame] | 1208 | * arg_1 doesn't take a shift Should it be E0 or A0? We also need the |
| 1209 | * indirect offset. */ |
| 1210 | |
| 1211 | if (indirect_offset) { |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1212 | ins.load_store.arg_1 |= 0xE0; |
Alyssa Rosenzweig | e7fd14c | 2019-10-26 15:50:38 -0400 | [diff] [blame] | 1213 | ins.src[2] = nir_src_index(ctx, indirect_offset); |
Alyssa Rosenzweig | 1a4153b | 2019-08-30 17:29:17 -0700 | [diff] [blame] | 1214 | } else { |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1215 | ins.load_store.arg_2 = 0x7E; |
Alyssa Rosenzweig | 1a4153b | 2019-08-30 17:29:17 -0700 | [diff] [blame] | 1216 | } |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1217 | |
| 1218 | /* TODO: Bounds check */ |
| 1219 | |
| 1220 | /* Finally, we emit the direct offset */ |
| 1221 | |
| 1222 | ins.load_store.varying_parameters = (offset & 0x1FF) << 1; |
| 1223 | ins.load_store.address = (offset >> 9); |
Alyssa Rosenzweig | 1798f6b | 2019-11-15 15:16:53 -0500 | [diff] [blame] | 1224 | mir_set_intr_mask(instr, &ins, is_read); |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1225 | |
| 1226 | emit_mir_instruction(ctx, ins); |
| 1227 | } |
| 1228 | |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1229 | static void |
Alyssa Rosenzweig | 15fae1e | 2019-06-04 23:26:09 +0000 | [diff] [blame] | 1230 | emit_varying_read( |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1231 | compiler_context *ctx, |
| 1232 | unsigned dest, unsigned offset, |
| 1233 | unsigned nr_comp, unsigned component, |
Alyssa Rosenzweig | c17a441 | 2019-12-27 15:32:50 -0500 | [diff] [blame] | 1234 | nir_src *indirect_offset, nir_alu_type type, bool flat) |
Alyssa Rosenzweig | 15fae1e | 2019-06-04 23:26:09 +0000 | [diff] [blame] | 1235 | { |
| 1236 | /* XXX: Half-floats? */ |
| 1237 | /* TODO: swizzle, mask */ |
| 1238 | |
| 1239 | midgard_instruction ins = m_ld_vary_32(dest, offset); |
Alyssa Rosenzweig | f8b18a4 | 2019-07-01 18:51:48 -0700 | [diff] [blame] | 1240 | ins.mask = mask_of(nr_comp); |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1241 | |
| 1242 | for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i) |
| 1243 | ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W); |
Alyssa Rosenzweig | 15fae1e | 2019-06-04 23:26:09 +0000 | [diff] [blame] | 1244 | |
| 1245 | midgard_varying_parameter p = { |
| 1246 | .is_varying = 1, |
| 1247 | .interpolation = midgard_interp_default, |
Alyssa Rosenzweig | c17a441 | 2019-12-27 15:32:50 -0500 | [diff] [blame] | 1248 | .flat = flat, |
Alyssa Rosenzweig | 15fae1e | 2019-06-04 23:26:09 +0000 | [diff] [blame] | 1249 | }; |
| 1250 | |
| 1251 | unsigned u; |
| 1252 | memcpy(&u, &p, sizeof(p)); |
| 1253 | ins.load_store.varying_parameters = u; |
| 1254 | |
Alyssa Rosenzweig | 513d02c | 2019-08-01 14:28:34 -0700 | [diff] [blame] | 1255 | if (indirect_offset) |
Alyssa Rosenzweig | e7fd14c | 2019-10-26 15:50:38 -0400 | [diff] [blame] | 1256 | ins.src[2] = nir_src_index(ctx, indirect_offset); |
Alyssa Rosenzweig | 513d02c | 2019-08-01 14:28:34 -0700 | [diff] [blame] | 1257 | else |
Alyssa Rosenzweig | c908772 | 2019-08-01 13:29:01 -0700 | [diff] [blame] | 1258 | ins.load_store.arg_2 = 0x1E; |
Alyssa Rosenzweig | 15fae1e | 2019-06-04 23:26:09 +0000 | [diff] [blame] | 1259 | |
Alyssa Rosenzweig | c908772 | 2019-08-01 13:29:01 -0700 | [diff] [blame] | 1260 | ins.load_store.arg_1 = 0x9E; |
| 1261 | |
Alyssa Rosenzweig | 9b97ed1 | 2019-06-28 09:30:59 -0700 | [diff] [blame] | 1262 | /* Use the type appropriate load */ |
| 1263 | switch (type) { |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1264 | case nir_type_uint: |
| 1265 | case nir_type_bool: |
| 1266 | ins.load_store.op = midgard_op_ld_vary_32u; |
| 1267 | break; |
| 1268 | case nir_type_int: |
| 1269 | ins.load_store.op = midgard_op_ld_vary_32i; |
| 1270 | break; |
| 1271 | case nir_type_float: |
| 1272 | ins.load_store.op = midgard_op_ld_vary_32; |
| 1273 | break; |
| 1274 | default: |
| 1275 | unreachable("Attempted to load unknown type"); |
| 1276 | break; |
Alyssa Rosenzweig | 9b97ed1 | 2019-06-28 09:30:59 -0700 | [diff] [blame] | 1277 | } |
| 1278 | |
Alyssa Rosenzweig | 15fae1e | 2019-06-04 23:26:09 +0000 | [diff] [blame] | 1279 | emit_mir_instruction(ctx, ins); |
| 1280 | } |
| 1281 | |
Alyssa Rosenzweig | 6e68890 | 2019-12-19 13:24:17 -0500 | [diff] [blame] | 1282 | static void |
| 1283 | emit_attr_read( |
| 1284 | compiler_context *ctx, |
| 1285 | unsigned dest, unsigned offset, |
| 1286 | unsigned nr_comp, nir_alu_type t) |
| 1287 | { |
| 1288 | midgard_instruction ins = m_ld_attr_32(dest, offset); |
| 1289 | ins.load_store.arg_1 = 0x1E; |
| 1290 | ins.load_store.arg_2 = 0x1E; |
| 1291 | ins.mask = mask_of(nr_comp); |
| 1292 | |
| 1293 | /* Use the type appropriate load */ |
| 1294 | switch (t) { |
| 1295 | case nir_type_uint: |
| 1296 | case nir_type_bool: |
| 1297 | ins.load_store.op = midgard_op_ld_attr_32u; |
| 1298 | break; |
| 1299 | case nir_type_int: |
| 1300 | ins.load_store.op = midgard_op_ld_attr_32i; |
| 1301 | break; |
| 1302 | case nir_type_float: |
| 1303 | ins.load_store.op = midgard_op_ld_attr_32; |
| 1304 | break; |
| 1305 | default: |
| 1306 | unreachable("Attempted to load unknown type"); |
| 1307 | break; |
| 1308 | } |
| 1309 | |
| 1310 | emit_mir_instruction(ctx, ins); |
| 1311 | } |
| 1312 | |
Alyssa Rosenzweig | fa68740 | 2019-08-02 11:06:21 -0700 | [diff] [blame] | 1313 | void |
Alyssa Rosenzweig | 63e240d | 2019-08-02 17:10:18 -0700 | [diff] [blame] | 1314 | emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, |
| 1315 | unsigned nr_components) |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1316 | { |
Alyssa Rosenzweig | 6d8490f | 2019-07-11 15:34:56 -0700 | [diff] [blame] | 1317 | unsigned dest = 0; |
| 1318 | |
Boris Brezillon | bd49c8f | 2019-06-14 09:59:20 +0200 | [diff] [blame] | 1319 | /* Figure out which uniform this is */ |
| 1320 | int sysval = sysval_for_instr(ctx, instr, &dest); |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1321 | void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval); |
| 1322 | |
Alyssa Rosenzweig | fa68740 | 2019-08-02 11:06:21 -0700 | [diff] [blame] | 1323 | if (dest_override >= 0) |
| 1324 | dest = dest_override; |
| 1325 | |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1326 | /* Sysvals are prefix uniforms */ |
| 1327 | unsigned uniform = ((uintptr_t) val) - 1; |
| 1328 | |
Alyssa Rosenzweig | 6a466c0 | 2019-04-20 23:52:42 +0000 | [diff] [blame] | 1329 | /* Emit the read itself -- this is never indirect */ |
Alyssa Rosenzweig | 63e240d | 2019-08-02 17:10:18 -0700 | [diff] [blame] | 1330 | midgard_instruction *ins = |
Alyssa Rosenzweig | 59d30fd | 2020-01-10 17:47:57 -0500 | [diff] [blame] | 1331 | emit_ubo_read(ctx, instr, dest, uniform * 16, NULL, 0, 0); |
Alyssa Rosenzweig | 63e240d | 2019-08-02 17:10:18 -0700 | [diff] [blame] | 1332 | |
| 1333 | ins->mask = mask_of(nr_components); |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1334 | } |
| 1335 | |
Alyssa Rosenzweig | 7229af7 | 2019-08-06 13:47:17 -0700 | [diff] [blame] | 1336 | static unsigned |
| 1337 | compute_builtin_arg(nir_op op) |
| 1338 | { |
| 1339 | switch (op) { |
| 1340 | case nir_intrinsic_load_work_group_id: |
| 1341 | return 0x14; |
| 1342 | case nir_intrinsic_load_local_invocation_id: |
| 1343 | return 0x10; |
| 1344 | default: |
| 1345 | unreachable("Invalid compute paramater loaded"); |
| 1346 | } |
| 1347 | } |
| 1348 | |
Alyssa Rosenzweig | dff4986 | 2019-08-12 12:36:46 -0700 | [diff] [blame] | 1349 | static void |
| 1350 | emit_fragment_store(compiler_context *ctx, unsigned src, unsigned rt) |
| 1351 | { |
Alyssa Rosenzweig | 5e06d90 | 2019-08-30 11:06:33 -0700 | [diff] [blame] | 1352 | emit_explicit_constant(ctx, src, src); |
Alyssa Rosenzweig | dff4986 | 2019-08-12 12:36:46 -0700 | [diff] [blame] | 1353 | |
Alyssa Rosenzweig | dff4986 | 2019-08-12 12:36:46 -0700 | [diff] [blame] | 1354 | struct midgard_instruction ins = |
Alyssa Rosenzweig | 02f503e | 2019-12-30 18:53:04 -0500 | [diff] [blame] | 1355 | v_branch(false, false); |
| 1356 | |
| 1357 | ins.writeout = true; |
Alyssa Rosenzweig | dff4986 | 2019-08-12 12:36:46 -0700 | [diff] [blame] | 1358 | |
| 1359 | /* Add dependencies */ |
Alyssa Rosenzweig | 7652983 | 2019-08-30 11:01:15 -0700 | [diff] [blame] | 1360 | ins.src[0] = src; |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 1361 | ins.constants.u32[0] = rt * 0x100; |
Alyssa Rosenzweig | dff4986 | 2019-08-12 12:36:46 -0700 | [diff] [blame] | 1362 | |
| 1363 | /* Emit the branch */ |
Alyssa Rosenzweig | 02f503e | 2019-12-30 18:53:04 -0500 | [diff] [blame] | 1364 | midgard_instruction *br = emit_mir_instruction(ctx, ins); |
Alyssa Rosenzweig | 281cc6f | 2019-11-23 12:43:55 -0500 | [diff] [blame] | 1365 | schedule_barrier(ctx); |
Alyssa Rosenzweig | 6039634 | 2019-11-23 16:08:02 -0500 | [diff] [blame] | 1366 | |
Alyssa Rosenzweig | 5bc62af | 2020-01-02 12:27:59 -0500 | [diff] [blame] | 1367 | assert(rt < ARRAY_SIZE(ctx->writeout_branch)); |
| 1368 | assert(!ctx->writeout_branch[rt]); |
| 1369 | ctx->writeout_branch[rt] = br; |
| 1370 | |
| 1371 | /* Push our current location = current block count - 1 = where we'll |
| 1372 | * jump to. Maybe a bit too clever for my own good */ |
| 1373 | |
| 1374 | br->branch.target_block = ctx->block_count - 1; |
Alyssa Rosenzweig | dff4986 | 2019-08-12 12:36:46 -0700 | [diff] [blame] | 1375 | } |
| 1376 | |
Alyssa Rosenzweig | 7229af7 | 2019-08-06 13:47:17 -0700 | [diff] [blame] | 1377 | static void |
| 1378 | emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr) |
| 1379 | { |
| 1380 | unsigned reg = nir_dest_index(ctx, &instr->dest); |
| 1381 | midgard_instruction ins = m_ld_compute_id(reg, 0); |
| 1382 | ins.mask = mask_of(3); |
| 1383 | ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic); |
| 1384 | emit_mir_instruction(ctx, ins); |
| 1385 | } |
Alyssa Rosenzweig | 306800d | 2019-12-19 13:31:21 -0500 | [diff] [blame] | 1386 | |
| 1387 | static unsigned |
| 1388 | vertex_builtin_arg(nir_op op) |
| 1389 | { |
| 1390 | switch (op) { |
| 1391 | case nir_intrinsic_load_vertex_id: |
| 1392 | return PAN_VERTEX_ID; |
| 1393 | case nir_intrinsic_load_instance_id: |
| 1394 | return PAN_INSTANCE_ID; |
| 1395 | default: |
| 1396 | unreachable("Invalid vertex builtin"); |
| 1397 | } |
| 1398 | } |
| 1399 | |
| 1400 | static void |
| 1401 | emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr) |
| 1402 | { |
| 1403 | unsigned reg = nir_dest_index(ctx, &instr->dest); |
| 1404 | emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int); |
| 1405 | } |
| 1406 | |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1407 | static void |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1408 | emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) |
| 1409 | { |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1410 | unsigned offset = 0, reg; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1411 | |
| 1412 | switch (instr->intrinsic) { |
| 1413 | case nir_intrinsic_discard_if: |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1414 | case nir_intrinsic_discard: { |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 1415 | bool conditional = instr->intrinsic == nir_intrinsic_discard_if; |
| 1416 | struct midgard_instruction discard = v_branch(conditional, false); |
| 1417 | discard.branch.target_type = TARGET_DISCARD; |
Alyssa Rosenzweig | d6e4e36 | 2019-08-26 13:59:29 -0700 | [diff] [blame] | 1418 | |
| 1419 | if (conditional) |
| 1420 | discard.src[0] = nir_src_index(ctx, &instr->src[0]); |
| 1421 | |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 1422 | emit_mir_instruction(ctx, discard); |
Alyssa Rosenzweig | cc2ba8e | 2019-08-30 10:53:13 -0700 | [diff] [blame] | 1423 | schedule_barrier(ctx); |
| 1424 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1425 | break; |
| 1426 | } |
| 1427 | |
| 1428 | case nir_intrinsic_load_uniform: |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1429 | case nir_intrinsic_load_ubo: |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1430 | case nir_intrinsic_load_ssbo: |
Alyssa Rosenzweig | c17a441 | 2019-12-27 15:32:50 -0500 | [diff] [blame] | 1431 | case nir_intrinsic_load_input: |
| 1432 | case nir_intrinsic_load_interpolated_input: { |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1433 | bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform; |
| 1434 | bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo; |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1435 | bool is_ssbo = instr->intrinsic == nir_intrinsic_load_ssbo; |
Alyssa Rosenzweig | c17a441 | 2019-12-27 15:32:50 -0500 | [diff] [blame] | 1436 | bool is_flat = instr->intrinsic == nir_intrinsic_load_input; |
| 1437 | bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input; |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1438 | |
Alyssa Rosenzweig | bbc050b | 2019-06-27 15:33:07 -0700 | [diff] [blame] | 1439 | /* Get the base type of the intrinsic */ |
Alyssa Rosenzweig | 8d74749 | 2019-06-27 14:13:10 -0700 | [diff] [blame] | 1440 | /* TODO: Infer type? Does it matter? */ |
| 1441 | nir_alu_type t = |
Alyssa Rosenzweig | c17a441 | 2019-12-27 15:32:50 -0500 | [diff] [blame] | 1442 | (is_ubo || is_ssbo) ? nir_type_uint : |
| 1443 | (is_interp) ? nir_type_float : |
| 1444 | nir_intrinsic_type(instr); |
| 1445 | |
Alyssa Rosenzweig | bbc050b | 2019-06-27 15:33:07 -0700 | [diff] [blame] | 1446 | t = nir_alu_type_get_base_type(t); |
| 1447 | |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1448 | if (!(is_ubo || is_ssbo)) { |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1449 | offset = nir_intrinsic_base(instr); |
| 1450 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1451 | |
Alyssa Rosenzweig | c1715b5 | 2019-05-22 02:44:12 +0000 | [diff] [blame] | 1452 | unsigned nr_comp = nir_intrinsic_dest_components(instr); |
Alyssa Rosenzweig | 6a466c0 | 2019-04-20 23:52:42 +0000 | [diff] [blame] | 1453 | |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1454 | nir_src *src_offset = nir_get_io_offset_src(instr); |
| 1455 | |
| 1456 | bool direct = nir_src_is_const(*src_offset); |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1457 | nir_src *indirect_offset = direct ? NULL : src_offset; |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1458 | |
| 1459 | if (direct) |
| 1460 | offset += nir_src_as_uint(*src_offset); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1461 | |
Alyssa Rosenzweig | 43568f2 | 2019-06-06 08:16:04 -0700 | [diff] [blame] | 1462 | /* We may need to apply a fractional offset */ |
Alyssa Rosenzweig | c17a441 | 2019-12-27 15:32:50 -0500 | [diff] [blame] | 1463 | int component = (is_flat || is_interp) ? |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1464 | nir_intrinsic_component(instr) : 0; |
Alyssa Rosenzweig | 4ed23b1 | 2019-02-07 04:56:13 +0000 | [diff] [blame] | 1465 | reg = nir_dest_index(ctx, &instr->dest); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1466 | |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1467 | if (is_uniform && !ctx->is_blend) { |
Alyssa Rosenzweig | 59d30fd | 2020-01-10 17:47:57 -0500 | [diff] [blame] | 1468 | emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysval_count + offset) * 16, indirect_offset, 4, 0); |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1469 | } else if (is_ubo) { |
| 1470 | nir_src index = instr->src[0]; |
| 1471 | |
Alyssa Rosenzweig | 59d30fd | 2020-01-10 17:47:57 -0500 | [diff] [blame] | 1472 | /* TODO: Is indirect block number possible? */ |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1473 | assert(nir_src_is_const(index)); |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1474 | |
Alyssa Rosenzweig | 5e2c3d4 | 2019-06-20 15:51:31 -0700 | [diff] [blame] | 1475 | uint32_t uindex = nir_src_as_uint(index) + 1; |
Alyssa Rosenzweig | 59d30fd | 2020-01-10 17:47:57 -0500 | [diff] [blame] | 1476 | emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex); |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1477 | } else if (is_ssbo) { |
| 1478 | nir_src index = instr->src[0]; |
| 1479 | assert(nir_src_is_const(index)); |
| 1480 | uint32_t uindex = nir_src_as_uint(index); |
| 1481 | |
| 1482 | emit_ssbo_access(ctx, &instr->instr, true, reg, offset, indirect_offset, uindex); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1483 | } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) { |
Alyssa Rosenzweig | c17a441 | 2019-12-27 15:32:50 -0500 | [diff] [blame] | 1484 | emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1485 | } else if (ctx->is_blend) { |
Alyssa Rosenzweig | 3910422 | 2019-05-06 02:12:41 +0000 | [diff] [blame] | 1486 | /* For blend shaders, load the input color, which is |
| 1487 | * preloaded to r0 */ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1488 | |
Alyssa Rosenzweig | c3a46e7 | 2019-10-30 16:29:28 -0400 | [diff] [blame] | 1489 | midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg); |
Alyssa Rosenzweig | 005d9b1 | 2019-05-20 00:46:48 +0000 | [diff] [blame] | 1490 | emit_mir_instruction(ctx, move); |
Alyssa Rosenzweig | cc2ba8e | 2019-08-30 10:53:13 -0700 | [diff] [blame] | 1491 | schedule_barrier(ctx); |
Alyssa Rosenzweig | 6e68890 | 2019-12-19 13:24:17 -0500 | [diff] [blame] | 1492 | } else if (ctx->stage == MESA_SHADER_VERTEX) { |
| 1493 | emit_attr_read(ctx, reg, offset, nr_comp, t); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1494 | } else { |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 1495 | DBG("Unknown load\n"); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1496 | assert(0); |
| 1497 | } |
| 1498 | |
| 1499 | break; |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1500 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1501 | |
Alyssa Rosenzweig | c17a441 | 2019-12-27 15:32:50 -0500 | [diff] [blame] | 1502 | /* Artefact of load_interpolated_input. TODO: other barycentric modes */ |
| 1503 | case nir_intrinsic_load_barycentric_pixel: |
Tomeu Vizoso | 2504206 | 2020-01-03 09:42:11 +0100 | [diff] [blame] | 1504 | case nir_intrinsic_load_barycentric_centroid: |
Alyssa Rosenzweig | c17a441 | 2019-12-27 15:32:50 -0500 | [diff] [blame] | 1505 | break; |
| 1506 | |
Alyssa Rosenzweig | 1686ef8 | 2019-07-01 17:23:58 -0700 | [diff] [blame] | 1507 | /* Reads 128-bit value raw off the tilebuffer during blending, tasty */ |
| 1508 | |
Alyssa Rosenzweig | 541b329 | 2019-07-01 15:02:40 -0700 | [diff] [blame] | 1509 | case nir_intrinsic_load_raw_output_pan: |
Alyssa Rosenzweig | 843874c | 2019-11-06 21:50:32 -0500 | [diff] [blame] | 1510 | case nir_intrinsic_load_output_u8_as_fp16_pan: |
Alyssa Rosenzweig | 3910422 | 2019-05-06 02:12:41 +0000 | [diff] [blame] | 1511 | reg = nir_dest_index(ctx, &instr->dest); |
Alyssa Rosenzweig | 541b329 | 2019-07-01 15:02:40 -0700 | [diff] [blame] | 1512 | assert(ctx->is_blend); |
Alyssa Rosenzweig | 1686ef8 | 2019-07-01 17:23:58 -0700 | [diff] [blame] | 1513 | |
Alyssa Rosenzweig | 843874c | 2019-11-06 21:50:32 -0500 | [diff] [blame] | 1514 | /* T720 and below use different blend opcodes with slightly |
| 1515 | * different semantics than T760 and up */ |
| 1516 | |
Alyssa Rosenzweig | 2d1e18e | 2020-01-02 12:28:54 -0500 | [diff] [blame] | 1517 | midgard_instruction ld = m_ld_color_buffer_32u(reg, 0); |
Alyssa Rosenzweig | fcf144d | 2019-11-19 20:55:42 -0500 | [diff] [blame] | 1518 | bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND; |
Alyssa Rosenzweig | 843874c | 2019-11-06 21:50:32 -0500 | [diff] [blame] | 1519 | |
| 1520 | if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) { |
| 1521 | ld.load_store.op = old_blend ? |
| 1522 | midgard_op_ld_color_buffer_u8_as_fp16_old : |
| 1523 | midgard_op_ld_color_buffer_u8_as_fp16; |
| 1524 | |
| 1525 | if (old_blend) { |
| 1526 | ld.load_store.address = 1; |
| 1527 | ld.load_store.arg_2 = 0x1E; |
| 1528 | } |
| 1529 | |
| 1530 | for (unsigned c = 2; c < 16; ++c) |
| 1531 | ld.swizzle[0][c] = 0; |
| 1532 | } |
| 1533 | |
Alyssa Rosenzweig | 1a4153b | 2019-08-30 17:29:17 -0700 | [diff] [blame] | 1534 | emit_mir_instruction(ctx, ld); |
Alyssa Rosenzweig | 3910422 | 2019-05-06 02:12:41 +0000 | [diff] [blame] | 1535 | break; |
| 1536 | |
| 1537 | case nir_intrinsic_load_blend_const_color_rgba: { |
| 1538 | assert(ctx->is_blend); |
| 1539 | reg = nir_dest_index(ctx, &instr->dest); |
| 1540 | |
| 1541 | /* Blend constants are embedded directly in the shader and |
| 1542 | * patched in, so we use some magic routing */ |
| 1543 | |
Alyssa Rosenzweig | c3a46e7 | 2019-10-30 16:29:28 -0400 | [diff] [blame] | 1544 | midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg); |
Alyssa Rosenzweig | 3910422 | 2019-05-06 02:12:41 +0000 | [diff] [blame] | 1545 | ins.has_constants = true; |
| 1546 | ins.has_blend_constant = true; |
| 1547 | emit_mir_instruction(ctx, ins); |
| 1548 | break; |
| 1549 | } |
| 1550 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1551 | case nir_intrinsic_store_output: |
Karol Herbst | 1aabb79 | 2019-03-29 21:40:45 +0100 | [diff] [blame] | 1552 | assert(nir_src_is_const(instr->src[1]) && "no indirect outputs"); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1553 | |
Karol Herbst | 1aabb79 | 2019-03-29 21:40:45 +0100 | [diff] [blame] | 1554 | offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1555 | |
Alyssa Rosenzweig | 4ed23b1 | 2019-02-07 04:56:13 +0000 | [diff] [blame] | 1556 | reg = nir_src_index(ctx, &instr->src[0]); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1557 | |
| 1558 | if (ctx->stage == MESA_SHADER_FRAGMENT) { |
Alyssa Rosenzweig | dff4986 | 2019-08-12 12:36:46 -0700 | [diff] [blame] | 1559 | emit_fragment_store(ctx, reg, offset); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1560 | } else if (ctx->stage == MESA_SHADER_VERTEX) { |
Alyssa Rosenzweig | a3ae3cb | 2019-06-17 12:35:57 -0700 | [diff] [blame] | 1561 | /* We should have been vectorized, though we don't |
| 1562 | * currently check that st_vary is emitted only once |
| 1563 | * per slot (this is relevant, since there's not a mask |
| 1564 | * parameter available on the store [set to 0 by the |
| 1565 | * blob]). We do respect the component by adjusting the |
Alyssa Rosenzweig | 233c0fa | 2019-07-24 12:54:59 -0700 | [diff] [blame] | 1566 | * swizzle. If this is a constant source, we'll need to |
| 1567 | * emit that explicitly. */ |
| 1568 | |
| 1569 | emit_explicit_constant(ctx, reg, reg); |
Alyssa Rosenzweig | a3ae3cb | 2019-06-17 12:35:57 -0700 | [diff] [blame] | 1570 | |
Boris Brezillon | 6af63c9 | 2020-01-16 11:20:06 +0100 | [diff] [blame] | 1571 | unsigned dst_component = nir_intrinsic_component(instr); |
Alyssa Rosenzweig | 2788721 | 2019-08-15 16:53:03 -0700 | [diff] [blame] | 1572 | unsigned nr_comp = nir_src_num_components(instr->src[0]); |
Alyssa Rosenzweig | de8d49a | 2019-06-06 09:15:26 -0700 | [diff] [blame] | 1573 | |
Alyssa Rosenzweig | 233c0fa | 2019-07-24 12:54:59 -0700 | [diff] [blame] | 1574 | midgard_instruction st = m_st_vary_32(reg, offset); |
Alyssa Rosenzweig | c908772 | 2019-08-01 13:29:01 -0700 | [diff] [blame] | 1575 | st.load_store.arg_1 = 0x9E; |
| 1576 | st.load_store.arg_2 = 0x1E; |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1577 | |
Alyssa Rosenzweig | 66c2696 | 2019-12-27 14:25:00 -0500 | [diff] [blame] | 1578 | switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) { |
| 1579 | case nir_type_uint: |
| 1580 | case nir_type_bool: |
| 1581 | st.load_store.op = midgard_op_st_vary_32u; |
| 1582 | break; |
| 1583 | case nir_type_int: |
| 1584 | st.load_store.op = midgard_op_st_vary_32i; |
| 1585 | break; |
| 1586 | case nir_type_float: |
| 1587 | st.load_store.op = midgard_op_st_vary_32; |
| 1588 | break; |
| 1589 | default: |
| 1590 | unreachable("Attempted to store unknown type"); |
| 1591 | break; |
| 1592 | } |
| 1593 | |
Boris Brezillon | 6af63c9 | 2020-01-16 11:20:06 +0100 | [diff] [blame] | 1594 | /* nir_intrinsic_component(store_intr) encodes the |
| 1595 | * destination component start. Source component offset |
| 1596 | * adjustment is taken care of in |
| 1597 | * install_registers_instr(), when offset_swizzle() is |
| 1598 | * called. |
| 1599 | */ |
| 1600 | unsigned src_component = COMPONENT_X; |
| 1601 | |
| 1602 | assert(nr_comp > 0); |
| 1603 | for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) { |
| 1604 | st.swizzle[0][i] = src_component; |
| 1605 | if (i >= dst_component && i < dst_component + nr_comp - 1) |
| 1606 | src_component++; |
| 1607 | } |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1608 | |
Alyssa Rosenzweig | 4aced18 | 2019-06-06 08:21:27 -0700 | [diff] [blame] | 1609 | emit_mir_instruction(ctx, st); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1610 | } else { |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 1611 | DBG("Unknown store\n"); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1612 | assert(0); |
| 1613 | } |
| 1614 | |
| 1615 | break; |
| 1616 | |
Alyssa Rosenzweig | 541b329 | 2019-07-01 15:02:40 -0700 | [diff] [blame] | 1617 | /* Special case of store_output for lowered blend shaders */ |
| 1618 | case nir_intrinsic_store_raw_output_pan: |
| 1619 | assert (ctx->stage == MESA_SHADER_FRAGMENT); |
| 1620 | reg = nir_src_index(ctx, &instr->src[0]); |
Alyssa Rosenzweig | 8555bff | 2019-11-26 08:48:33 -0500 | [diff] [blame] | 1621 | |
| 1622 | if (ctx->quirks & MIDGARD_OLD_BLEND) { |
| 1623 | /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So |
| 1624 | * reg = r0.x. We want to splatter. So we can do a 32-bit move |
| 1625 | * of: |
| 1626 | * |
| 1627 | * imov r0.xyzw, r0.xxxx |
| 1628 | */ |
| 1629 | |
| 1630 | unsigned expanded = make_compiler_temp(ctx); |
| 1631 | |
| 1632 | midgard_instruction splatter = v_mov(reg, expanded); |
| 1633 | |
| 1634 | for (unsigned c = 0; c < 16; ++c) |
| 1635 | splatter.swizzle[1][c] = 0; |
| 1636 | |
| 1637 | emit_mir_instruction(ctx, splatter); |
Alyssa Rosenzweig | a2d5503 | 2019-11-23 21:44:16 -0500 | [diff] [blame] | 1638 | emit_fragment_store(ctx, expanded, ctx->blend_rt); |
Alyssa Rosenzweig | 8555bff | 2019-11-26 08:48:33 -0500 | [diff] [blame] | 1639 | } else |
Alyssa Rosenzweig | a2d5503 | 2019-11-23 21:44:16 -0500 | [diff] [blame] | 1640 | emit_fragment_store(ctx, reg, ctx->blend_rt); |
Alyssa Rosenzweig | 541b329 | 2019-07-01 15:02:40 -0700 | [diff] [blame] | 1641 | |
| 1642 | break; |
| 1643 | |
Alyssa Rosenzweig | 419ddd6 | 2019-08-01 10:03:02 -0700 | [diff] [blame] | 1644 | case nir_intrinsic_store_ssbo: |
| 1645 | assert(nir_src_is_const(instr->src[1])); |
| 1646 | |
| 1647 | bool direct_offset = nir_src_is_const(instr->src[2]); |
| 1648 | offset = direct_offset ? nir_src_as_uint(instr->src[2]) : 0; |
| 1649 | nir_src *indirect_offset = direct_offset ? NULL : &instr->src[2]; |
| 1650 | reg = nir_src_index(ctx, &instr->src[0]); |
| 1651 | |
| 1652 | uint32_t uindex = nir_src_as_uint(instr->src[1]); |
| 1653 | |
| 1654 | emit_explicit_constant(ctx, reg, reg); |
| 1655 | emit_ssbo_access(ctx, &instr->instr, false, reg, offset, indirect_offset, uindex); |
| 1656 | break; |
| 1657 | |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1658 | case nir_intrinsic_load_viewport_scale: |
| 1659 | case nir_intrinsic_load_viewport_offset: |
Alyssa Rosenzweig | 15954ab | 2019-08-06 14:07:10 -0700 | [diff] [blame] | 1660 | case nir_intrinsic_load_num_work_groups: |
Alyssa Rosenzweig | 4e07e7b | 2019-11-21 08:42:28 -0500 | [diff] [blame] | 1661 | case nir_intrinsic_load_sampler_lod_parameters_pan: |
Alyssa Rosenzweig | 6189274 | 2019-08-21 09:15:56 -0700 | [diff] [blame] | 1662 | emit_sysval_read(ctx, &instr->instr, ~0, 3); |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 1663 | break; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1664 | |
Alyssa Rosenzweig | 7229af7 | 2019-08-06 13:47:17 -0700 | [diff] [blame] | 1665 | case nir_intrinsic_load_work_group_id: |
| 1666 | case nir_intrinsic_load_local_invocation_id: |
| 1667 | emit_compute_builtin(ctx, instr); |
| 1668 | break; |
| 1669 | |
Alyssa Rosenzweig | 306800d | 2019-12-19 13:31:21 -0500 | [diff] [blame] | 1670 | case nir_intrinsic_load_vertex_id: |
| 1671 | case nir_intrinsic_load_instance_id: |
| 1672 | emit_vertex_builtin(ctx, instr); |
| 1673 | break; |
| 1674 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1675 | default: |
Tomeu Vizoso | 2504206 | 2020-01-03 09:42:11 +0100 | [diff] [blame] | 1676 | printf ("Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1677 | assert(0); |
| 1678 | break; |
| 1679 | } |
| 1680 | } |
| 1681 | |
| 1682 | static unsigned |
| 1683 | midgard_tex_format(enum glsl_sampler_dim dim) |
| 1684 | { |
| 1685 | switch (dim) { |
Alyssa Rosenzweig | 83c02a5 | 2019-06-17 14:26:08 -0700 | [diff] [blame] | 1686 | case GLSL_SAMPLER_DIM_1D: |
| 1687 | case GLSL_SAMPLER_DIM_BUF: |
| 1688 | return MALI_TEX_1D; |
| 1689 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1690 | case GLSL_SAMPLER_DIM_2D: |
| 1691 | case GLSL_SAMPLER_DIM_EXTERNAL: |
Alyssa Rosenzweig | 44a6c38 | 2019-08-14 08:44:40 -0700 | [diff] [blame] | 1692 | case GLSL_SAMPLER_DIM_RECT: |
Alyssa Rosenzweig | 83c02a5 | 2019-06-17 14:26:08 -0700 | [diff] [blame] | 1693 | return MALI_TEX_2D; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1694 | |
| 1695 | case GLSL_SAMPLER_DIM_3D: |
Alyssa Rosenzweig | 83c02a5 | 2019-06-17 14:26:08 -0700 | [diff] [blame] | 1696 | return MALI_TEX_3D; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1697 | |
| 1698 | case GLSL_SAMPLER_DIM_CUBE: |
Alyssa Rosenzweig | 83c02a5 | 2019-06-17 14:26:08 -0700 | [diff] [blame] | 1699 | return MALI_TEX_CUBE; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1700 | |
| 1701 | default: |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 1702 | DBG("Unknown sampler dim type\n"); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1703 | assert(0); |
| 1704 | return 0; |
| 1705 | } |
| 1706 | } |
| 1707 | |
Alyssa Rosenzweig | 213b628 | 2019-06-18 09:02:20 -0700 | [diff] [blame] | 1708 | /* Tries to attach an explicit LOD / bias as a constant. Returns whether this |
| 1709 | * was successful */ |
| 1710 | |
| 1711 | static bool |
| 1712 | pan_attach_constant_bias( |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1713 | compiler_context *ctx, |
| 1714 | nir_src lod, |
| 1715 | midgard_texture_word *word) |
Alyssa Rosenzweig | 213b628 | 2019-06-18 09:02:20 -0700 | [diff] [blame] | 1716 | { |
| 1717 | /* To attach as constant, it has to *be* constant */ |
| 1718 | |
| 1719 | if (!nir_src_is_const(lod)) |
| 1720 | return false; |
| 1721 | |
| 1722 | float f = nir_src_as_float(lod); |
| 1723 | |
| 1724 | /* Break into fixed-point */ |
| 1725 | signed lod_int = f; |
| 1726 | float lod_frac = f - lod_int; |
| 1727 | |
| 1728 | /* Carry over negative fractions */ |
| 1729 | if (lod_frac < 0.0) { |
| 1730 | lod_int--; |
| 1731 | lod_frac += 1.0; |
| 1732 | } |
| 1733 | |
| 1734 | /* Encode */ |
| 1735 | word->bias = float_to_ubyte(lod_frac); |
| 1736 | word->bias_int = lod_int; |
| 1737 | |
| 1738 | return true; |
| 1739 | } |
| 1740 | |
Alyssa Rosenzweig | e32af4b | 2019-06-26 16:12:28 -0700 | [diff] [blame] | 1741 | static enum mali_sampler_type |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1742 | midgard_sampler_type(nir_alu_type t) { |
| 1743 | switch (nir_alu_type_get_base_type(t)) |
| 1744 | { |
| 1745 | case nir_type_float: |
| 1746 | return MALI_SAMPLER_FLOAT; |
| 1747 | case nir_type_int: |
| 1748 | return MALI_SAMPLER_SIGNED; |
| 1749 | case nir_type_uint: |
| 1750 | return MALI_SAMPLER_UNSIGNED; |
| 1751 | default: |
| 1752 | unreachable("Unknown sampler type"); |
Alyssa Rosenzweig | e32af4b | 2019-06-26 16:12:28 -0700 | [diff] [blame] | 1753 | } |
| 1754 | } |
| 1755 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1756 | static void |
Boris Brezillon | 5c17f84 | 2019-06-17 21:47:46 +0200 | [diff] [blame] | 1757 | emit_texop_native(compiler_context *ctx, nir_tex_instr *instr, |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1758 | unsigned midgard_texop) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1759 | { |
| 1760 | /* TODO */ |
| 1761 | //assert (!instr->sampler); |
| 1762 | //assert (!instr->texture_array_size); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1763 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1764 | int texture_index = instr->texture_index; |
| 1765 | int sampler_index = texture_index; |
| 1766 | |
Alyssa Rosenzweig | b0e8941 | 2019-06-18 09:02:35 -0700 | [diff] [blame] | 1767 | /* No helper to build texture words -- we do it all here */ |
| 1768 | midgard_instruction ins = { |
| 1769 | .type = TAG_TEXTURE_4, |
Alyssa Rosenzweig | f8b18a4 | 2019-07-01 18:51:48 -0700 | [diff] [blame] | 1770 | .mask = 0xF, |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 1771 | .dest = nir_dest_index(ctx, &instr->dest), |
Alyssa Rosenzweig | ccbc9a4 | 2019-12-19 10:35:18 -0500 | [diff] [blame] | 1772 | .src = { ~0, ~0, ~0, ~0 }, |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1773 | .swizzle = SWIZZLE_IDENTITY_4, |
Alyssa Rosenzweig | b0e8941 | 2019-06-18 09:02:35 -0700 | [diff] [blame] | 1774 | .texture = { |
| 1775 | .op = midgard_texop, |
| 1776 | .format = midgard_tex_format(instr->sampler_dim), |
| 1777 | .texture_handle = texture_index, |
| 1778 | .sampler_handle = sampler_index, |
Alyssa Rosenzweig | b0e8941 | 2019-06-18 09:02:35 -0700 | [diff] [blame] | 1779 | |
| 1780 | /* TODO: half */ |
| 1781 | .in_reg_full = 1, |
| 1782 | .out_full = 1, |
| 1783 | |
Alyssa Rosenzweig | e32af4b | 2019-06-26 16:12:28 -0700 | [diff] [blame] | 1784 | .sampler_type = midgard_sampler_type(instr->dest_type), |
Alyssa Rosenzweig | 1a53bed | 2019-12-16 17:13:46 -0500 | [diff] [blame] | 1785 | .shadow = instr->is_shadow, |
Alyssa Rosenzweig | b0e8941 | 2019-06-18 09:02:35 -0700 | [diff] [blame] | 1786 | } |
| 1787 | }; |
Alyssa Rosenzweig | 8429bee | 2019-06-14 16:03:39 -0700 | [diff] [blame] | 1788 | |
Alyssa Rosenzweig | d183f84 | 2019-12-16 17:02:36 -0500 | [diff] [blame] | 1789 | /* We may need a temporary for the coordinate */ |
| 1790 | |
Alyssa Rosenzweig | 66013cb | 2019-12-16 17:14:04 -0500 | [diff] [blame] | 1791 | bool needs_temp_coord = |
| 1792 | (midgard_texop == TEXTURE_OP_TEXEL_FETCH) || |
Alyssa Rosenzweig | 6b7243f | 2019-12-20 17:25:05 -0500 | [diff] [blame] | 1793 | (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) || |
Alyssa Rosenzweig | 66013cb | 2019-12-16 17:14:04 -0500 | [diff] [blame] | 1794 | (instr->is_shadow); |
| 1795 | |
Alyssa Rosenzweig | d183f84 | 2019-12-16 17:02:36 -0500 | [diff] [blame] | 1796 | unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0; |
| 1797 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1798 | for (unsigned i = 0; i < instr->num_srcs; ++i) { |
Alyssa Rosenzweig | a19ca34 | 2019-06-11 09:23:05 -0700 | [diff] [blame] | 1799 | int index = nir_src_index(ctx, &instr->src[i].src); |
Alyssa Rosenzweig | edc8e41 | 2019-08-15 16:41:53 -0700 | [diff] [blame] | 1800 | unsigned nr_components = nir_src_num_components(instr->src[i].src); |
Alyssa Rosenzweig | a19ca34 | 2019-06-11 09:23:05 -0700 | [diff] [blame] | 1801 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1802 | switch (instr->src[i].src_type) { |
| 1803 | case nir_tex_src_coord: { |
Alyssa Rosenzweig | b6946d3 | 2019-07-25 08:44:53 -0700 | [diff] [blame] | 1804 | emit_explicit_constant(ctx, index, index); |
| 1805 | |
Alyssa Rosenzweig | 9e5a141 | 2019-12-20 17:01:29 -0500 | [diff] [blame] | 1806 | unsigned coord_mask = mask_of(instr->coord_components); |
| 1807 | |
Alyssa Rosenzweig | bc4c853 | 2020-01-06 21:31:46 -0500 | [diff] [blame] | 1808 | bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z)); |
| 1809 | |
| 1810 | if (flip_zw) |
| 1811 | coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W)); |
| 1812 | |
Alyssa Rosenzweig | 6b7243f | 2019-12-20 17:25:05 -0500 | [diff] [blame] | 1813 | if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) { |
| 1814 | /* texelFetch is undefined on samplerCube */ |
| 1815 | assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH); |
| 1816 | |
| 1817 | /* For cubemaps, we use a special ld/st op to |
| 1818 | * select the face and copy the xy into the |
| 1819 | * texture register */ |
| 1820 | |
| 1821 | midgard_instruction ld = m_ld_cubemap_coords(coords, 0); |
| 1822 | ld.src[1] = index; |
| 1823 | ld.mask = 0x3; /* xy */ |
| 1824 | ld.load_store.arg_1 = 0x20; |
| 1825 | ld.swizzle[1][3] = COMPONENT_X; |
| 1826 | emit_mir_instruction(ctx, ld); |
| 1827 | |
| 1828 | /* xyzw -> xyxx */ |
| 1829 | ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X; |
| 1830 | ins.swizzle[1][3] = COMPONENT_X; |
| 1831 | } else if (needs_temp_coord) { |
Alyssa Rosenzweig | d183f84 | 2019-12-16 17:02:36 -0500 | [diff] [blame] | 1832 | /* mov coord_temp, coords */ |
| 1833 | midgard_instruction mov = v_mov(index, coords); |
Alyssa Rosenzweig | 9e5a141 | 2019-12-20 17:01:29 -0500 | [diff] [blame] | 1834 | mov.mask = coord_mask; |
Alyssa Rosenzweig | bc4c853 | 2020-01-06 21:31:46 -0500 | [diff] [blame] | 1835 | |
| 1836 | if (flip_zw) |
| 1837 | mov.swizzle[1][COMPONENT_W] = COMPONENT_Z; |
| 1838 | |
Alyssa Rosenzweig | d183f84 | 2019-12-16 17:02:36 -0500 | [diff] [blame] | 1839 | emit_mir_instruction(ctx, mov); |
| 1840 | } else { |
| 1841 | coords = index; |
| 1842 | } |
| 1843 | |
Alyssa Rosenzweig | 6b7243f | 2019-12-20 17:25:05 -0500 | [diff] [blame] | 1844 | ins.src[1] = coords; |
| 1845 | |
Alyssa Rosenzweig | b6946d3 | 2019-07-25 08:44:53 -0700 | [diff] [blame] | 1846 | /* Texelfetch coordinates uses all four elements |
| 1847 | * (xyz/index) regardless of texture dimensionality, |
| 1848 | * which means it's necessary to zero the unused |
| 1849 | * components to keep everything happy */ |
| 1850 | |
| 1851 | if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) { |
Alyssa Rosenzweig | 9e5a141 | 2019-12-20 17:01:29 -0500 | [diff] [blame] | 1852 | /* mov index.zw, #0, or generalized */ |
Alyssa Rosenzweig | d183f84 | 2019-12-16 17:02:36 -0500 | [diff] [blame] | 1853 | midgard_instruction mov = |
| 1854 | v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords); |
Alyssa Rosenzweig | b6946d3 | 2019-07-25 08:44:53 -0700 | [diff] [blame] | 1855 | mov.has_constants = true; |
Alyssa Rosenzweig | 9e5a141 | 2019-12-20 17:01:29 -0500 | [diff] [blame] | 1856 | mov.mask = coord_mask ^ 0xF; |
Alyssa Rosenzweig | b6946d3 | 2019-07-25 08:44:53 -0700 | [diff] [blame] | 1857 | emit_mir_instruction(ctx, mov); |
| 1858 | } |
| 1859 | |
Alyssa Rosenzweig | b6946d3 | 2019-07-25 08:44:53 -0700 | [diff] [blame] | 1860 | if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) { |
Alyssa Rosenzweig | 4cd3dc9 | 2020-01-06 21:36:20 -0500 | [diff] [blame] | 1861 | /* Array component in w but NIR wants it in z, |
| 1862 | * but if we have a temp coord we already fixed |
| 1863 | * that up */ |
| 1864 | |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1865 | if (nr_components == 3) { |
| 1866 | ins.swizzle[1][2] = COMPONENT_Z; |
Alyssa Rosenzweig | 4cd3dc9 | 2020-01-06 21:36:20 -0500 | [diff] [blame] | 1867 | ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z; |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1868 | } else if (nr_components == 2) { |
Alyssa Rosenzweig | 66013cb | 2019-12-16 17:14:04 -0500 | [diff] [blame] | 1869 | ins.swizzle[1][2] = |
| 1870 | instr->is_shadow ? COMPONENT_Z : COMPONENT_X; |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1871 | ins.swizzle[1][3] = COMPONENT_X; |
| 1872 | } else |
Alyssa Rosenzweig | edc8e41 | 2019-08-15 16:41:53 -0700 | [diff] [blame] | 1873 | unreachable("Invalid texture 2D components"); |
Alyssa Rosenzweig | 70b3e5d | 2019-03-28 04:27:13 +0000 | [diff] [blame] | 1874 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1875 | |
Alyssa Rosenzweig | 64b2fe9 | 2019-12-20 12:38:24 -0500 | [diff] [blame] | 1876 | if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) { |
| 1877 | /* We zeroed */ |
| 1878 | ins.swizzle[1][2] = COMPONENT_Z; |
| 1879 | ins.swizzle[1][3] = COMPONENT_W; |
| 1880 | } |
| 1881 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1882 | break; |
| 1883 | } |
| 1884 | |
Alyssa Rosenzweig | 4012e06 | 2019-06-11 09:43:08 -0700 | [diff] [blame] | 1885 | case nir_tex_src_bias: |
| 1886 | case nir_tex_src_lod: { |
Alyssa Rosenzweig | b0e8941 | 2019-06-18 09:02:35 -0700 | [diff] [blame] | 1887 | /* Try as a constant if we can */ |
| 1888 | |
| 1889 | bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH; |
| 1890 | if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture)) |
| 1891 | break; |
| 1892 | |
Alyssa Rosenzweig | b0e8941 | 2019-06-18 09:02:35 -0700 | [diff] [blame] | 1893 | ins.texture.lod_register = true; |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 1894 | ins.src[2] = index; |
Alyssa Rosenzweig | 72e5749 | 2019-12-20 12:34:20 -0500 | [diff] [blame] | 1895 | |
| 1896 | for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) |
| 1897 | ins.swizzle[2][c] = COMPONENT_X; |
| 1898 | |
Alyssa Rosenzweig | b6946d3 | 2019-07-25 08:44:53 -0700 | [diff] [blame] | 1899 | emit_explicit_constant(ctx, index, index); |
Alyssa Rosenzweig | b0e8941 | 2019-06-18 09:02:35 -0700 | [diff] [blame] | 1900 | |
Alyssa Rosenzweig | a19ca34 | 2019-06-11 09:23:05 -0700 | [diff] [blame] | 1901 | break; |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1902 | }; |
Alyssa Rosenzweig | a19ca34 | 2019-06-11 09:23:05 -0700 | [diff] [blame] | 1903 | |
Alyssa Rosenzweig | ccbc9a4 | 2019-12-19 10:35:18 -0500 | [diff] [blame] | 1904 | case nir_tex_src_offset: { |
| 1905 | ins.texture.offset_register = true; |
| 1906 | ins.src[3] = index; |
| 1907 | |
| 1908 | for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) |
| 1909 | ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c; |
| 1910 | |
| 1911 | emit_explicit_constant(ctx, index, index); |
Alyssa Rosenzweig | 4ec1f95 | 2019-12-20 12:58:10 -0500 | [diff] [blame] | 1912 | break; |
Alyssa Rosenzweig | ccbc9a4 | 2019-12-19 10:35:18 -0500 | [diff] [blame] | 1913 | }; |
| 1914 | |
Alyssa Rosenzweig | 66013cb | 2019-12-16 17:14:04 -0500 | [diff] [blame] | 1915 | case nir_tex_src_comparator: { |
Alyssa Rosenzweig | 66013cb | 2019-12-16 17:14:04 -0500 | [diff] [blame] | 1916 | unsigned comp = COMPONENT_Z; |
| 1917 | |
| 1918 | /* mov coord_temp.foo, coords */ |
| 1919 | midgard_instruction mov = v_mov(index, coords); |
| 1920 | mov.mask = 1 << comp; |
| 1921 | |
| 1922 | for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i) |
| 1923 | mov.swizzle[1][i] = COMPONENT_X; |
| 1924 | |
| 1925 | emit_mir_instruction(ctx, mov); |
| 1926 | break; |
| 1927 | } |
| 1928 | |
Tomeu Vizoso | 226c1ef | 2019-12-19 15:07:39 +0100 | [diff] [blame] | 1929 | default: { |
| 1930 | printf ("Unknown texture source type: %d\n", instr->src[i].src_type); |
| 1931 | assert(0); |
| 1932 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1933 | } |
| 1934 | } |
| 1935 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1936 | emit_mir_instruction(ctx, ins); |
| 1937 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1938 | /* Used for .cont and .last hinting */ |
| 1939 | ctx->texture_op_count++; |
| 1940 | } |
| 1941 | |
| 1942 | static void |
Boris Brezillon | 5c17f84 | 2019-06-17 21:47:46 +0200 | [diff] [blame] | 1943 | emit_tex(compiler_context *ctx, nir_tex_instr *instr) |
| 1944 | { |
| 1945 | switch (instr->op) { |
| 1946 | case nir_texop_tex: |
| 1947 | case nir_texop_txb: |
| 1948 | emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL); |
| 1949 | break; |
| 1950 | case nir_texop_txl: |
| 1951 | emit_texop_native(ctx, instr, TEXTURE_OP_LOD); |
| 1952 | break; |
Alyssa Rosenzweig | f4bb7f0 | 2019-06-21 16:17:34 -0700 | [diff] [blame] | 1953 | case nir_texop_txf: |
| 1954 | emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH); |
| 1955 | break; |
Boris Brezillon | c355886 | 2019-06-17 22:13:04 +0200 | [diff] [blame] | 1956 | case nir_texop_txs: |
Alyssa Rosenzweig | 6189274 | 2019-08-21 09:15:56 -0700 | [diff] [blame] | 1957 | emit_sysval_read(ctx, &instr->instr, ~0, 4); |
Boris Brezillon | c355886 | 2019-06-17 22:13:04 +0200 | [diff] [blame] | 1958 | break; |
Tomeu Vizoso | 226c1ef | 2019-12-19 15:07:39 +0100 | [diff] [blame] | 1959 | default: { |
| 1960 | printf ("Unhandled texture op: %d\n", instr->op); |
| 1961 | assert(0); |
| 1962 | } |
Boris Brezillon | 5c17f84 | 2019-06-17 21:47:46 +0200 | [diff] [blame] | 1963 | } |
| 1964 | } |
| 1965 | |
| 1966 | static void |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1967 | emit_jump(compiler_context *ctx, nir_jump_instr *instr) |
| 1968 | { |
| 1969 | switch (instr->type) { |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1970 | case nir_jump_break: { |
| 1971 | /* Emit a branch out of the loop */ |
| 1972 | struct midgard_instruction br = v_branch(false, false); |
| 1973 | br.branch.target_type = TARGET_BREAK; |
| 1974 | br.branch.target_break = ctx->current_loop_depth; |
| 1975 | emit_mir_instruction(ctx, br); |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1976 | break; |
| 1977 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1978 | |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 1979 | default: |
| 1980 | DBG("Unknown jump type %d\n", instr->type); |
| 1981 | break; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 1982 | } |
| 1983 | } |
| 1984 | |
| 1985 | static void |
| 1986 | emit_instr(compiler_context *ctx, struct nir_instr *instr) |
| 1987 | { |
| 1988 | switch (instr->type) { |
| 1989 | case nir_instr_type_load_const: |
| 1990 | emit_load_const(ctx, nir_instr_as_load_const(instr)); |
| 1991 | break; |
| 1992 | |
| 1993 | case nir_instr_type_intrinsic: |
| 1994 | emit_intrinsic(ctx, nir_instr_as_intrinsic(instr)); |
| 1995 | break; |
| 1996 | |
| 1997 | case nir_instr_type_alu: |
| 1998 | emit_alu(ctx, nir_instr_as_alu(instr)); |
| 1999 | break; |
| 2000 | |
| 2001 | case nir_instr_type_tex: |
| 2002 | emit_tex(ctx, nir_instr_as_tex(instr)); |
| 2003 | break; |
| 2004 | |
| 2005 | case nir_instr_type_jump: |
| 2006 | emit_jump(ctx, nir_instr_as_jump(instr)); |
| 2007 | break; |
| 2008 | |
| 2009 | case nir_instr_type_ssa_undef: |
| 2010 | /* Spurious */ |
| 2011 | break; |
| 2012 | |
| 2013 | default: |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 2014 | DBG("Unhandled instruction type\n"); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2015 | break; |
| 2016 | } |
| 2017 | } |
| 2018 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2019 | |
| 2020 | /* ALU instructions can inline or embed constants, which decreases register |
| 2021 | * pressure and saves space. */ |
| 2022 | |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2023 | #define CONDITIONAL_ATTACH(idx) { \ |
| 2024 | void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2025 | \ |
| 2026 | if (entry) { \ |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2027 | attach_constants(ctx, alu, entry, alu->src[idx] + 1); \ |
| 2028 | alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2029 | } \ |
| 2030 | } |
| 2031 | |
| 2032 | static void |
Alyssa Rosenzweig | cc2ba8e | 2019-08-30 10:53:13 -0700 | [diff] [blame] | 2033 | inline_alu_constants(compiler_context *ctx, midgard_block *block) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2034 | { |
Alyssa Rosenzweig | cc2ba8e | 2019-08-30 10:53:13 -0700 | [diff] [blame] | 2035 | mir_foreach_instr_in_block(block, alu) { |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2036 | /* Other instructions cannot inline constants */ |
| 2037 | if (alu->type != TAG_ALU_4) continue; |
Alyssa Rosenzweig | 5e06d90 | 2019-08-30 11:06:33 -0700 | [diff] [blame] | 2038 | if (alu->compact_branch) continue; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2039 | |
| 2040 | /* If there is already a constant here, we can do nothing */ |
| 2041 | if (alu->has_constants) continue; |
| 2042 | |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2043 | CONDITIONAL_ATTACH(0); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2044 | |
| 2045 | if (!alu->has_constants) { |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2046 | CONDITIONAL_ATTACH(1) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2047 | } else if (!alu->inline_constant) { |
| 2048 | /* Corner case: _two_ vec4 constants, for instance with a |
| 2049 | * csel. For this case, we can only use a constant |
| 2050 | * register for one, we'll have to emit a move for the |
| 2051 | * other. Note, if both arguments are constants, then |
| 2052 | * necessarily neither argument depends on the value of |
| 2053 | * any particular register. As the destination register |
| 2054 | * will be wiped, that means we can spill the constant |
| 2055 | * to the destination register. |
| 2056 | */ |
| 2057 | |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2058 | void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1); |
| 2059 | unsigned scratch = alu->dest; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2060 | |
| 2061 | if (entry) { |
Alyssa Rosenzweig | c3a46e7 | 2019-10-30 16:29:28 -0400 | [diff] [blame] | 2062 | midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch); |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2063 | attach_constants(ctx, &ins, entry, alu->src[1] + 1); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2064 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2065 | /* Set the source */ |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2066 | alu->src[1] = scratch; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2067 | |
| 2068 | /* Inject us -before- the last instruction which set r31 */ |
Boris Brezillon | 938c5b0 | 2019-08-28 09:17:21 +0200 | [diff] [blame] | 2069 | mir_insert_instruction_before(ctx, mir_prev_op(alu), ins); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2070 | } |
| 2071 | } |
| 2072 | } |
| 2073 | } |
| 2074 | |
Alyssa Rosenzweig | 62a5ee3 | 2019-07-26 14:25:25 -0700 | [diff] [blame] | 2075 | /* Being a little silly with the names, but returns the op that is the bitwise |
| 2076 | * inverse of the op with the argument switched. I.e. (f and g are |
| 2077 | * contrapositives): |
| 2078 | * |
| 2079 | * f(a, b) = ~g(b, a) |
| 2080 | * |
| 2081 | * Corollary: if g is the contrapositve of f, f is the contrapositive of g: |
| 2082 | * |
| 2083 | * f(a, b) = ~g(b, a) |
| 2084 | * ~f(a, b) = g(b, a) |
| 2085 | * ~f(a, b) = ~h(a, b) where h is the contrapositive of g |
| 2086 | * f(a, b) = h(a, b) |
| 2087 | * |
| 2088 | * Thus we define this function in pairs. |
| 2089 | */ |
| 2090 | |
| 2091 | static inline midgard_alu_op |
| 2092 | mir_contrapositive(midgard_alu_op op) |
| 2093 | { |
| 2094 | switch (op) { |
| 2095 | case midgard_alu_op_flt: |
| 2096 | return midgard_alu_op_fle; |
| 2097 | case midgard_alu_op_fle: |
| 2098 | return midgard_alu_op_flt; |
| 2099 | |
| 2100 | case midgard_alu_op_ilt: |
| 2101 | return midgard_alu_op_ile; |
| 2102 | case midgard_alu_op_ile: |
| 2103 | return midgard_alu_op_ilt; |
| 2104 | |
| 2105 | default: |
| 2106 | unreachable("No known contrapositive"); |
| 2107 | } |
| 2108 | } |
| 2109 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2110 | /* Midgard supports two types of constants, embedded constants (128-bit) and |
| 2111 | * inline constants (16-bit). Sometimes, especially with scalar ops, embedded |
| 2112 | * constants can be demoted to inline constants, for space savings and |
| 2113 | * sometimes a performance boost */ |
| 2114 | |
| 2115 | static void |
Alyssa Rosenzweig | cc2ba8e | 2019-08-30 10:53:13 -0700 | [diff] [blame] | 2116 | embedded_to_inline_constant(compiler_context *ctx, midgard_block *block) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2117 | { |
Alyssa Rosenzweig | cc2ba8e | 2019-08-30 10:53:13 -0700 | [diff] [blame] | 2118 | mir_foreach_instr_in_block(block, ins) { |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2119 | if (!ins->has_constants) continue; |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2120 | if (ins->has_inline_constant) continue; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2121 | |
| 2122 | /* Blend constants must not be inlined by definition */ |
| 2123 | if (ins->has_blend_constant) continue; |
| 2124 | |
Alyssa Rosenzweig | e92caad | 2019-07-01 20:02:57 -0700 | [diff] [blame] | 2125 | /* We can inline 32-bit (sometimes) or 16-bit (usually) */ |
| 2126 | bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16; |
| 2127 | bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32; |
| 2128 | |
| 2129 | if (!(is_16 || is_32)) |
| 2130 | continue; |
| 2131 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2132 | /* src1 cannot be an inline constant due to encoding |
| 2133 | * restrictions. So, if possible we try to flip the arguments |
| 2134 | * in that case */ |
| 2135 | |
| 2136 | int op = ins->alu.op; |
| 2137 | |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2138 | if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) { |
Alyssa Rosenzweig | 62a5ee3 | 2019-07-26 14:25:25 -0700 | [diff] [blame] | 2139 | bool flip = alu_opcode_props[op].props & OP_COMMUTES; |
| 2140 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2141 | switch (op) { |
Alyssa Rosenzweig | 62a5ee3 | 2019-07-26 14:25:25 -0700 | [diff] [blame] | 2142 | /* Conditionals can be inverted */ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2143 | case midgard_alu_op_flt: |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2144 | case midgard_alu_op_ilt: |
Alyssa Rosenzweig | 62a5ee3 | 2019-07-26 14:25:25 -0700 | [diff] [blame] | 2145 | case midgard_alu_op_fle: |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2146 | case midgard_alu_op_ile: |
Alyssa Rosenzweig | 62a5ee3 | 2019-07-26 14:25:25 -0700 | [diff] [blame] | 2147 | ins->alu.op = mir_contrapositive(ins->alu.op); |
| 2148 | ins->invert = true; |
| 2149 | flip = true; |
| 2150 | break; |
| 2151 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2152 | case midgard_alu_op_fcsel: |
| 2153 | case midgard_alu_op_icsel: |
Alyssa Rosenzweig | 1f345bc | 2019-04-24 01:15:15 +0000 | [diff] [blame] | 2154 | DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name); |
Alyssa Rosenzweig | bb1aff3 | 2019-04-24 02:18:28 +0000 | [diff] [blame] | 2155 | default: |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2156 | break; |
Alyssa Rosenzweig | bb1aff3 | 2019-04-24 02:18:28 +0000 | [diff] [blame] | 2157 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2158 | |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 2159 | if (flip) |
| 2160 | mir_flip(ins); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2161 | } |
| 2162 | |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2163 | if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) { |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2164 | /* Extract the source information */ |
| 2165 | |
| 2166 | midgard_vector_alu_src *src; |
| 2167 | int q = ins->alu.src2; |
| 2168 | midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q; |
| 2169 | src = m; |
| 2170 | |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 2171 | /* Component is from the swizzle. Take a nonzero component */ |
| 2172 | assert(ins->mask); |
| 2173 | unsigned first_comp = ffs(ins->mask) - 1; |
| 2174 | unsigned component = ins->swizzle[1][first_comp]; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2175 | |
| 2176 | /* Scale constant appropriately, if we can legally */ |
| 2177 | uint16_t scaled_constant = 0; |
| 2178 | |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 2179 | if (is_16) { |
| 2180 | scaled_constant = ins->constants.u16[component]; |
| 2181 | } else if (midgard_is_integer_op(op)) { |
| 2182 | scaled_constant = ins->constants.u32[component]; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2183 | |
| 2184 | /* Constant overflow after resize */ |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 2185 | if (scaled_constant != ins->constants.u32[component]) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2186 | continue; |
| 2187 | } else { |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 2188 | float original = ins->constants.f32[component]; |
Alyssa Rosenzweig | 3978614 | 2019-04-28 15:46:47 +0000 | [diff] [blame] | 2189 | scaled_constant = _mesa_float_to_half(original); |
| 2190 | |
| 2191 | /* Check for loss of precision. If this is |
| 2192 | * mediump, we don't care, but for a highp |
| 2193 | * shader, we need to pay attention. NIR |
| 2194 | * doesn't yet tell us which mode we're in! |
| 2195 | * Practically this prevents most constants |
| 2196 | * from being inlined, sadly. */ |
| 2197 | |
| 2198 | float fp32 = _mesa_half_to_float(scaled_constant); |
| 2199 | |
| 2200 | if (fp32 != original) |
| 2201 | continue; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2202 | } |
| 2203 | |
| 2204 | /* We don't know how to handle these with a constant */ |
| 2205 | |
Alyssa Rosenzweig | c45487b | 2019-07-26 11:52:30 -0700 | [diff] [blame] | 2206 | if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) { |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 2207 | DBG("Bailing inline constant...\n"); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2208 | continue; |
| 2209 | } |
| 2210 | |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 2211 | /* Make sure that the constant is not itself a vector |
| 2212 | * by checking if all accessed values are the same. */ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2213 | |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 2214 | const midgard_constants *cons = &ins->constants; |
| 2215 | uint32_t value = is_16 ? cons->u16[component] : cons->u32[component]; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2216 | |
| 2217 | bool is_vector = false; |
Alyssa Rosenzweig | f8b18a4 | 2019-07-01 18:51:48 -0700 | [diff] [blame] | 2218 | unsigned mask = effective_writemask(&ins->alu, ins->mask); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2219 | |
Alyssa Rosenzweig | 70072a2 | 2019-10-26 14:06:17 -0400 | [diff] [blame] | 2220 | for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) { |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2221 | /* We only care if this component is actually used */ |
| 2222 | if (!(mask & (1 << c))) |
| 2223 | continue; |
| 2224 | |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 2225 | uint32_t test = is_16 ? |
| 2226 | cons->u16[ins->swizzle[1][c]] : |
| 2227 | cons->u32[ins->swizzle[1][c]]; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2228 | |
| 2229 | if (test != value) { |
| 2230 | is_vector = true; |
| 2231 | break; |
| 2232 | } |
| 2233 | } |
| 2234 | |
| 2235 | if (is_vector) |
| 2236 | continue; |
| 2237 | |
| 2238 | /* Get rid of the embedded constant */ |
| 2239 | ins->has_constants = false; |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2240 | ins->src[1] = ~0; |
| 2241 | ins->has_inline_constant = true; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2242 | ins->inline_constant = scaled_constant; |
| 2243 | } |
| 2244 | } |
| 2245 | } |
| 2246 | |
Alyssa Rosenzweig | ae20bee | 2019-06-06 11:19:13 -0700 | [diff] [blame] | 2247 | /* Dead code elimination for branches at the end of a block - only one branch |
| 2248 | * per block is legal semantically */ |
| 2249 | |
| 2250 | static void |
| 2251 | midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block) |
| 2252 | { |
| 2253 | bool branched = false; |
| 2254 | |
| 2255 | mir_foreach_instr_in_block_safe(block, ins) { |
| 2256 | if (!midgard_is_branch_unit(ins->unit)) continue; |
| 2257 | |
Alyssa Rosenzweig | cc2ba8e | 2019-08-30 10:53:13 -0700 | [diff] [blame] | 2258 | if (branched) |
Alyssa Rosenzweig | ae20bee | 2019-06-06 11:19:13 -0700 | [diff] [blame] | 2259 | mir_remove_instruction(ins); |
Alyssa Rosenzweig | ae20bee | 2019-06-06 11:19:13 -0700 | [diff] [blame] | 2260 | |
| 2261 | branched = true; |
| 2262 | } |
| 2263 | } |
| 2264 | |
Alyssa Rosenzweig | 4a03d37 | 2019-05-23 03:01:32 +0000 | [diff] [blame] | 2265 | /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then |
| 2266 | * the move can be propagated away entirely */ |
| 2267 | |
| 2268 | static bool |
Alyssa Rosenzweig | 6780481 | 2019-06-05 15:17:45 -0700 | [diff] [blame] | 2269 | mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp) |
Alyssa Rosenzweig | 4a03d37 | 2019-05-23 03:01:32 +0000 | [diff] [blame] | 2270 | { |
| 2271 | /* Nothing to do */ |
| 2272 | if (comp == midgard_outmod_none) |
| 2273 | return true; |
| 2274 | |
| 2275 | if (*outmod == midgard_outmod_none) { |
| 2276 | *outmod = comp; |
| 2277 | return true; |
| 2278 | } |
| 2279 | |
| 2280 | /* TODO: Compose rules */ |
| 2281 | return false; |
| 2282 | } |
| 2283 | |
| 2284 | static bool |
| 2285 | midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block) |
| 2286 | { |
| 2287 | bool progress = false; |
| 2288 | |
| 2289 | mir_foreach_instr_in_block_safe(block, ins) { |
| 2290 | if (ins->type != TAG_ALU_4) continue; |
| 2291 | if (ins->alu.op != midgard_alu_op_fmov) continue; |
| 2292 | if (ins->alu.outmod != midgard_outmod_pos) continue; |
| 2293 | |
| 2294 | /* TODO: Registers? */ |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2295 | unsigned src = ins->src[1]; |
Alyssa Rosenzweig | 9beb339 | 2019-07-26 11:30:06 -0700 | [diff] [blame] | 2296 | if (src & IS_REG) continue; |
Alyssa Rosenzweig | 4a03d37 | 2019-05-23 03:01:32 +0000 | [diff] [blame] | 2297 | |
| 2298 | /* There might be a source modifier, too */ |
| 2299 | if (mir_nontrivial_source2_mod(ins)) continue; |
| 2300 | |
| 2301 | /* Backpropagate the modifier */ |
| 2302 | mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) { |
| 2303 | if (v->type != TAG_ALU_4) continue; |
Alyssa Rosenzweig | 75b6be2 | 2019-08-26 11:58:27 -0700 | [diff] [blame] | 2304 | if (v->dest != src) continue; |
Alyssa Rosenzweig | 4a03d37 | 2019-05-23 03:01:32 +0000 | [diff] [blame] | 2305 | |
Alyssa Rosenzweig | 6780481 | 2019-06-05 15:17:45 -0700 | [diff] [blame] | 2306 | /* Can we even take a float outmod? */ |
| 2307 | if (midgard_is_integer_out_op(v->alu.op)) continue; |
| 2308 | |
| 2309 | midgard_outmod_float temp = v->alu.outmod; |
| 2310 | progress |= mir_compose_float_outmod(&temp, ins->alu.outmod); |
Alyssa Rosenzweig | 4a03d37 | 2019-05-23 03:01:32 +0000 | [diff] [blame] | 2311 | |
| 2312 | /* Throw in the towel.. */ |
| 2313 | if (!progress) break; |
| 2314 | |
| 2315 | /* Otherwise, transfer the modifier */ |
| 2316 | v->alu.outmod = temp; |
| 2317 | ins->alu.outmod = midgard_outmod_none; |
| 2318 | |
| 2319 | break; |
| 2320 | } |
| 2321 | } |
| 2322 | |
| 2323 | return progress; |
| 2324 | } |
| 2325 | |
Alyssa Rosenzweig | 5bc62af | 2020-01-02 12:27:59 -0500 | [diff] [blame] | 2326 | static unsigned |
Alyssa Rosenzweig | 6039634 | 2019-11-23 16:08:02 -0500 | [diff] [blame] | 2327 | emit_fragment_epilogue(compiler_context *ctx, unsigned rt) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2328 | { |
Alyssa Rosenzweig | 02f503e | 2019-12-30 18:53:04 -0500 | [diff] [blame] | 2329 | /* Loop to ourselves */ |
| 2330 | |
| 2331 | struct midgard_instruction ins = v_branch(false, false); |
| 2332 | ins.writeout = true; |
| 2333 | ins.branch.target_block = ctx->block_count - 1; |
Boris Brezillon | 15c92d1 | 2020-01-20 15:00:57 +0100 | [diff] [blame] | 2334 | ins.constants.u32[0] = rt * 0x100; |
Alyssa Rosenzweig | 02f503e | 2019-12-30 18:53:04 -0500 | [diff] [blame] | 2335 | emit_mir_instruction(ctx, ins); |
| 2336 | |
Alyssa Rosenzweig | 3448b26 | 2019-12-03 10:37:01 -0500 | [diff] [blame] | 2337 | ctx->current_block->epilogue = true; |
Alyssa Rosenzweig | 6039634 | 2019-11-23 16:08:02 -0500 | [diff] [blame] | 2338 | schedule_barrier(ctx); |
Alyssa Rosenzweig | 5bc62af | 2020-01-02 12:27:59 -0500 | [diff] [blame] | 2339 | return ins.branch.target_block; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2340 | } |
| 2341 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2342 | static midgard_block * |
| 2343 | emit_block(compiler_context *ctx, nir_block *block) |
| 2344 | { |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2345 | midgard_block *this_block = ctx->after_block; |
| 2346 | ctx->after_block = NULL; |
| 2347 | |
| 2348 | if (!this_block) |
Alyssa Rosenzweig | aeeeef1 | 2019-08-15 08:11:10 -0700 | [diff] [blame] | 2349 | this_block = create_empty_block(ctx); |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2350 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2351 | list_addtail(&this_block->link, &ctx->blocks); |
| 2352 | |
| 2353 | this_block->is_scheduled = false; |
| 2354 | ++ctx->block_count; |
| 2355 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2356 | /* Set up current block */ |
| 2357 | list_inithead(&this_block->instructions); |
| 2358 | ctx->current_block = this_block; |
| 2359 | |
| 2360 | nir_foreach_instr(instr, block) { |
| 2361 | emit_instr(ctx, instr); |
| 2362 | ++ctx->instruction_count; |
| 2363 | } |
| 2364 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2365 | return this_block; |
| 2366 | } |
| 2367 | |
| 2368 | static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list); |
| 2369 | |
| 2370 | static void |
| 2371 | emit_if(struct compiler_context *ctx, nir_if *nif) |
| 2372 | { |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2373 | midgard_block *before_block = ctx->current_block; |
| 2374 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2375 | /* Speculatively emit the branch, but we can't fill it in until later */ |
| 2376 | EMIT(branch, true, true); |
| 2377 | midgard_instruction *then_branch = mir_last_in_block(ctx->current_block); |
Alyssa Rosenzweig | d6e4e36 | 2019-08-26 13:59:29 -0700 | [diff] [blame] | 2378 | then_branch->src[0] = nir_src_index(ctx, &nif->condition); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2379 | |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2380 | /* Emit the two subblocks. */ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2381 | midgard_block *then_block = emit_cf_list(ctx, &nif->then_list); |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2382 | midgard_block *end_then_block = ctx->current_block; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2383 | |
| 2384 | /* Emit a jump from the end of the then block to the end of the else */ |
| 2385 | EMIT(branch, false, false); |
| 2386 | midgard_instruction *then_exit = mir_last_in_block(ctx->current_block); |
| 2387 | |
| 2388 | /* Emit second block, and check if it's empty */ |
| 2389 | |
| 2390 | int else_idx = ctx->block_count; |
| 2391 | int count_in = ctx->instruction_count; |
| 2392 | midgard_block *else_block = emit_cf_list(ctx, &nif->else_list); |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2393 | midgard_block *end_else_block = ctx->current_block; |
Alyssa Rosenzweig | 2c74709 | 2019-02-17 05:14:24 +0000 | [diff] [blame] | 2394 | int after_else_idx = ctx->block_count; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2395 | |
| 2396 | /* Now that we have the subblocks emitted, fix up the branches */ |
| 2397 | |
| 2398 | assert(then_block); |
| 2399 | assert(else_block); |
| 2400 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2401 | if (ctx->instruction_count == count_in) { |
| 2402 | /* The else block is empty, so don't emit an exit jump */ |
| 2403 | mir_remove_instruction(then_exit); |
Alyssa Rosenzweig | 2c74709 | 2019-02-17 05:14:24 +0000 | [diff] [blame] | 2404 | then_branch->branch.target_block = after_else_idx; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2405 | } else { |
| 2406 | then_branch->branch.target_block = else_idx; |
Alyssa Rosenzweig | 2c74709 | 2019-02-17 05:14:24 +0000 | [diff] [blame] | 2407 | then_exit->branch.target_block = after_else_idx; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2408 | } |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2409 | |
| 2410 | /* Wire up the successors */ |
| 2411 | |
Alyssa Rosenzweig | aeeeef1 | 2019-08-15 08:11:10 -0700 | [diff] [blame] | 2412 | ctx->after_block = create_empty_block(ctx); |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2413 | |
| 2414 | midgard_block_add_successor(before_block, then_block); |
| 2415 | midgard_block_add_successor(before_block, else_block); |
| 2416 | |
| 2417 | midgard_block_add_successor(end_then_block, ctx->after_block); |
| 2418 | midgard_block_add_successor(end_else_block, ctx->after_block); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2419 | } |
| 2420 | |
| 2421 | static void |
| 2422 | emit_loop(struct compiler_context *ctx, nir_loop *nloop) |
| 2423 | { |
| 2424 | /* Remember where we are */ |
| 2425 | midgard_block *start_block = ctx->current_block; |
| 2426 | |
Alyssa Rosenzweig | 521ac6e | 2019-04-21 16:22:44 +0000 | [diff] [blame] | 2427 | /* Allocate a loop number, growing the current inner loop depth */ |
| 2428 | int loop_idx = ++ctx->current_loop_depth; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2429 | |
| 2430 | /* Get index from before the body so we can loop back later */ |
| 2431 | int start_idx = ctx->block_count; |
| 2432 | |
| 2433 | /* Emit the body itself */ |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2434 | midgard_block *loop_block = emit_cf_list(ctx, &nloop->body); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2435 | |
| 2436 | /* Branch back to loop back */ |
| 2437 | struct midgard_instruction br_back = v_branch(false, false); |
| 2438 | br_back.branch.target_block = start_idx; |
| 2439 | emit_mir_instruction(ctx, br_back); |
| 2440 | |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2441 | /* Mark down that branch in the graph. */ |
| 2442 | midgard_block_add_successor(start_block, loop_block); |
| 2443 | midgard_block_add_successor(ctx->current_block, loop_block); |
Alyssa Rosenzweig | c0fb260 | 2019-04-21 03:29:47 +0000 | [diff] [blame] | 2444 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2445 | /* Find the index of the block about to follow us (note: we don't add |
| 2446 | * one; blocks are 0-indexed so we get a fencepost problem) */ |
| 2447 | int break_block_idx = ctx->block_count; |
| 2448 | |
| 2449 | /* Fix up the break statements we emitted to point to the right place, |
| 2450 | * now that we can allocate a block number for them */ |
Alyssa Rosenzweig | aeeeef1 | 2019-08-15 08:11:10 -0700 | [diff] [blame] | 2451 | ctx->after_block = create_empty_block(ctx); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2452 | |
| 2453 | list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) { |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2454 | mir_foreach_instr_in_block(block, ins) { |
| 2455 | if (ins->type != TAG_ALU_4) continue; |
| 2456 | if (!ins->compact_branch) continue; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2457 | |
| 2458 | /* We found a branch -- check the type to see if we need to do anything */ |
| 2459 | if (ins->branch.target_type != TARGET_BREAK) continue; |
| 2460 | |
| 2461 | /* It's a break! Check if it's our break */ |
| 2462 | if (ins->branch.target_break != loop_idx) continue; |
| 2463 | |
| 2464 | /* Okay, cool, we're breaking out of this loop. |
| 2465 | * Rewrite from a break to a goto */ |
| 2466 | |
| 2467 | ins->branch.target_type = TARGET_GOTO; |
| 2468 | ins->branch.target_block = break_block_idx; |
Alyssa Rosenzweig | 9aeb726 | 2019-08-02 13:48:27 -0700 | [diff] [blame] | 2469 | |
| 2470 | midgard_block_add_successor(block, ctx->after_block); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2471 | } |
| 2472 | } |
Alyssa Rosenzweig | 521ac6e | 2019-04-21 16:22:44 +0000 | [diff] [blame] | 2473 | |
| 2474 | /* Now that we've finished emitting the loop, free up the depth again |
| 2475 | * so we play nice with recursion amid nested loops */ |
| 2476 | --ctx->current_loop_depth; |
Alyssa Rosenzweig | 7ad6516 | 2019-07-09 11:10:49 -0700 | [diff] [blame] | 2477 | |
| 2478 | /* Dump loop stats */ |
| 2479 | ++ctx->loop_count; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2480 | } |
| 2481 | |
| 2482 | static midgard_block * |
| 2483 | emit_cf_list(struct compiler_context *ctx, struct exec_list *list) |
| 2484 | { |
| 2485 | midgard_block *start_block = NULL; |
| 2486 | |
| 2487 | foreach_list_typed(nir_cf_node, node, node, list) { |
| 2488 | switch (node->type) { |
| 2489 | case nir_cf_node_block: { |
| 2490 | midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node)); |
| 2491 | |
| 2492 | if (!start_block) |
| 2493 | start_block = block; |
| 2494 | |
| 2495 | break; |
| 2496 | } |
| 2497 | |
| 2498 | case nir_cf_node_if: |
| 2499 | emit_if(ctx, nir_cf_node_as_if(node)); |
| 2500 | break; |
| 2501 | |
| 2502 | case nir_cf_node_loop: |
| 2503 | emit_loop(ctx, nir_cf_node_as_loop(node)); |
| 2504 | break; |
| 2505 | |
| 2506 | case nir_cf_node_function: |
| 2507 | assert(0); |
| 2508 | break; |
| 2509 | } |
| 2510 | } |
| 2511 | |
| 2512 | return start_block; |
| 2513 | } |
| 2514 | |
Alyssa Rosenzweig | 5e55c11 | 2019-02-17 03:35:03 +0000 | [diff] [blame] | 2515 | /* Due to lookahead, we need to report the first tag executed in the command |
| 2516 | * stream and in branch targets. An initial block might be empty, so iterate |
| 2517 | * until we find one that 'works' */ |
| 2518 | |
| 2519 | static unsigned |
| 2520 | midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx) |
| 2521 | { |
| 2522 | midgard_block *initial_block = mir_get_block(ctx, block_idx); |
| 2523 | |
| 2524 | unsigned first_tag = 0; |
| 2525 | |
Alyssa Rosenzweig | 73c40d6 | 2019-07-31 15:49:30 -0700 | [diff] [blame] | 2526 | mir_foreach_block_from(ctx, initial_block, v) { |
Alyssa Rosenzweig | 45ac8ea | 2019-11-04 10:32:49 -0500 | [diff] [blame] | 2527 | if (v->quadword_count) { |
| 2528 | midgard_bundle *initial_bundle = |
| 2529 | util_dynarray_element(&v->bundles, midgard_bundle, 0); |
Alyssa Rosenzweig | 5e55c11 | 2019-02-17 03:35:03 +0000 | [diff] [blame] | 2530 | |
Alyssa Rosenzweig | 5e55c11 | 2019-02-17 03:35:03 +0000 | [diff] [blame] | 2531 | first_tag = initial_bundle->tag; |
| 2532 | break; |
| 2533 | } |
Alyssa Rosenzweig | 73c40d6 | 2019-07-31 15:49:30 -0700 | [diff] [blame] | 2534 | } |
Alyssa Rosenzweig | 5e55c11 | 2019-02-17 03:35:03 +0000 | [diff] [blame] | 2535 | |
Alyssa Rosenzweig | 5e55c11 | 2019-02-17 03:35:03 +0000 | [diff] [blame] | 2536 | return first_tag; |
| 2537 | } |
| 2538 | |
Alyssa Rosenzweig | 67fe2af | 2019-12-27 16:01:34 -0500 | [diff] [blame] | 2539 | static unsigned |
| 2540 | pan_format_from_nir_base(nir_alu_type base) |
| 2541 | { |
| 2542 | switch (base) { |
| 2543 | case nir_type_int: |
| 2544 | return MALI_FORMAT_SINT; |
| 2545 | case nir_type_uint: |
| 2546 | case nir_type_bool: |
| 2547 | return MALI_FORMAT_UINT; |
| 2548 | case nir_type_float: |
| 2549 | return MALI_CHANNEL_FLOAT; |
| 2550 | default: |
| 2551 | unreachable("Invalid base"); |
| 2552 | } |
| 2553 | } |
| 2554 | |
| 2555 | static unsigned |
| 2556 | pan_format_from_nir_size(nir_alu_type base, unsigned size) |
| 2557 | { |
| 2558 | if (base == nir_type_float) { |
| 2559 | switch (size) { |
| 2560 | case 16: return MALI_FORMAT_SINT; |
| 2561 | case 32: return MALI_FORMAT_UNORM; |
| 2562 | default: |
| 2563 | unreachable("Invalid float size for format"); |
| 2564 | } |
| 2565 | } else { |
| 2566 | switch (size) { |
| 2567 | case 1: |
| 2568 | case 8: return MALI_CHANNEL_8; |
| 2569 | case 16: return MALI_CHANNEL_16; |
| 2570 | case 32: return MALI_CHANNEL_32; |
| 2571 | default: |
| 2572 | unreachable("Invalid int size for format"); |
| 2573 | } |
| 2574 | } |
| 2575 | } |
| 2576 | |
| 2577 | static enum mali_format |
| 2578 | pan_format_from_glsl(const struct glsl_type *type) |
| 2579 | { |
| 2580 | enum glsl_base_type glsl_base = glsl_get_base_type(glsl_without_array(type)); |
| 2581 | nir_alu_type t = nir_get_nir_type_for_glsl_base_type(glsl_base); |
| 2582 | |
| 2583 | unsigned base = nir_alu_type_get_base_type(t); |
| 2584 | unsigned size = nir_alu_type_get_type_size(t); |
| 2585 | |
| 2586 | return pan_format_from_nir_base(base) | |
| 2587 | pan_format_from_nir_size(base, size) | |
| 2588 | MALI_NR_CHANNELS(4); |
| 2589 | } |
| 2590 | |
Alyssa Rosenzweig | 5bc62af | 2020-01-02 12:27:59 -0500 | [diff] [blame] | 2591 | /* For each fragment writeout instruction, generate a writeout loop to |
| 2592 | * associate with it */ |
| 2593 | |
| 2594 | static void |
| 2595 | mir_add_writeout_loops(compiler_context *ctx) |
| 2596 | { |
| 2597 | for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) { |
| 2598 | midgard_instruction *br = ctx->writeout_branch[rt]; |
| 2599 | if (!br) continue; |
| 2600 | |
| 2601 | unsigned popped = br->branch.target_block; |
| 2602 | midgard_block_add_successor(mir_get_block(ctx, popped - 1), ctx->current_block); |
| 2603 | br->branch.target_block = emit_fragment_epilogue(ctx, rt); |
| 2604 | |
| 2605 | /* If we have more RTs, we'll need to restore back after our |
| 2606 | * loop terminates */ |
| 2607 | |
| 2608 | if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) { |
| 2609 | midgard_instruction uncond = v_branch(false, false); |
| 2610 | uncond.branch.target_block = popped; |
| 2611 | emit_mir_instruction(ctx, uncond); |
| 2612 | midgard_block_add_successor(ctx->current_block, mir_get_block(ctx, popped)); |
| 2613 | schedule_barrier(ctx); |
| 2614 | } else { |
| 2615 | /* We're last, so we can terminate here */ |
| 2616 | br->last_writeout = true; |
| 2617 | } |
| 2618 | } |
| 2619 | } |
| 2620 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2621 | int |
Alyssa Rosenzweig | 35418f6 | 2019-12-16 18:05:21 -0500 | [diff] [blame] | 2622 | midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb) |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2623 | { |
| 2624 | struct util_dynarray *compiled = &program->compiled; |
| 2625 | |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 2626 | midgard_debug = debug_get_option_midgard_debug(); |
Tomeu Vizoso | f0b1bbe | 2019-03-08 15:04:50 +0100 | [diff] [blame] | 2627 | |
Alyssa Rosenzweig | 4fa0932 | 2019-08-15 08:10:46 -0700 | [diff] [blame] | 2628 | /* TODO: Bound against what? */ |
| 2629 | compiler_context *ctx = rzalloc(NULL, compiler_context); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2630 | |
Alyssa Rosenzweig | 4fa0932 | 2019-08-15 08:10:46 -0700 | [diff] [blame] | 2631 | ctx->nir = nir; |
Alyssa Rosenzweig | 4fa0932 | 2019-08-15 08:10:46 -0700 | [diff] [blame] | 2632 | ctx->stage = nir->info.stage; |
| 2633 | ctx->is_blend = is_blend; |
| 2634 | ctx->alpha_ref = program->alpha_ref; |
Alyssa Rosenzweig | a2d5503 | 2019-11-23 21:44:16 -0500 | [diff] [blame] | 2635 | ctx->blend_rt = blend_rt; |
Alyssa Rosenzweig | fcf144d | 2019-11-19 20:55:42 -0500 | [diff] [blame] | 2636 | ctx->quirks = midgard_get_quirks(gpu_id); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2637 | |
Alyssa Rosenzweig | 3174bc9 | 2019-07-16 14:10:08 -0700 | [diff] [blame] | 2638 | /* Start off with a safe cutoff, allowing usage of all 16 work |
| 2639 | * registers. Later, we'll promote uniform reads to uniform registers |
| 2640 | * if we determine it is beneficial to do so */ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2641 | ctx->uniform_cutoff = 8; |
| 2642 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2643 | /* Initialize at a global (not block) level hash tables */ |
| 2644 | |
| 2645 | ctx->ssa_constants = _mesa_hash_table_u64_create(NULL); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2646 | ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL); |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 2647 | ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2648 | |
Alyssa Rosenzweig | b98955e | 2019-03-15 23:25:55 +0000 | [diff] [blame] | 2649 | /* Record the varying mapping for the command stream's bookkeeping */ |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2650 | |
Alyssa Rosenzweig | b98955e | 2019-03-15 23:25:55 +0000 | [diff] [blame] | 2651 | struct exec_list *varyings = |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 2652 | ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2653 | |
Alyssa Rosenzweig | de8d49a | 2019-06-06 09:15:26 -0700 | [diff] [blame] | 2654 | unsigned max_varying = 0; |
Alyssa Rosenzweig | b98955e | 2019-03-15 23:25:55 +0000 | [diff] [blame] | 2655 | nir_foreach_variable(var, varyings) { |
| 2656 | unsigned loc = var->data.driver_location; |
Alyssa Rosenzweig | 1f7b388 | 2019-04-20 23:39:29 +0000 | [diff] [blame] | 2657 | unsigned sz = glsl_type_size(var->type, FALSE); |
| 2658 | |
Boris Brezillon | 749c544 | 2019-06-13 14:56:02 +0200 | [diff] [blame] | 2659 | for (int c = 0; c < sz; ++c) { |
| 2660 | program->varyings[loc + c] = var->data.location + c; |
Alyssa Rosenzweig | 67fe2af | 2019-12-27 16:01:34 -0500 | [diff] [blame] | 2661 | program->varying_type[loc + c] = pan_format_from_glsl(var->type); |
Boris Brezillon | 749c544 | 2019-06-13 14:56:02 +0200 | [diff] [blame] | 2662 | max_varying = MAX2(max_varying, loc + c); |
Alyssa Rosenzweig | 1f7b388 | 2019-04-20 23:39:29 +0000 | [diff] [blame] | 2663 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2664 | } |
| 2665 | |
Alyssa Rosenzweig | de8d49a | 2019-06-06 09:15:26 -0700 | [diff] [blame] | 2666 | /* Lower gl_Position pre-optimisation, but after lowering vars to ssa |
| 2667 | * (so we don't accidentally duplicate the epilogue since mesa/st has |
| 2668 | * messed with our I/O quite a bit already) */ |
| 2669 | |
| 2670 | NIR_PASS_V(nir, nir_lower_vars_to_ssa); |
Alyssa Rosenzweig | 1e2cb3e | 2019-04-07 16:37:28 +0000 | [diff] [blame] | 2671 | |
Alyssa Rosenzweig | bb483a9 | 2019-07-10 11:30:00 -0700 | [diff] [blame] | 2672 | if (ctx->stage == MESA_SHADER_VERTEX) { |
Alyssa Rosenzweig | 1e2cb3e | 2019-04-07 16:37:28 +0000 | [diff] [blame] | 2673 | NIR_PASS_V(nir, nir_lower_viewport_transform); |
Alyssa Rosenzweig | 2023716 | 2019-08-26 12:14:11 -0700 | [diff] [blame] | 2674 | NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0); |
Alyssa Rosenzweig | bb483a9 | 2019-07-10 11:30:00 -0700 | [diff] [blame] | 2675 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2676 | |
| 2677 | NIR_PASS_V(nir, nir_lower_var_copies); |
| 2678 | NIR_PASS_V(nir, nir_lower_vars_to_ssa); |
| 2679 | NIR_PASS_V(nir, nir_split_var_copies); |
| 2680 | NIR_PASS_V(nir, nir_lower_var_copies); |
| 2681 | NIR_PASS_V(nir, nir_lower_global_vars_to_local); |
| 2682 | NIR_PASS_V(nir, nir_lower_var_copies); |
| 2683 | NIR_PASS_V(nir, nir_lower_vars_to_ssa); |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 2684 | |
Eric Anholt | 771adff | 2019-04-08 16:32:01 -0700 | [diff] [blame] | 2685 | NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2686 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2687 | /* Optimisation passes */ |
| 2688 | |
Alyssa Rosenzweig | bda2bb3 | 2019-11-21 08:45:27 -0500 | [diff] [blame] | 2689 | optimise_nir(nir, ctx->quirks); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2690 | |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 2691 | if (midgard_debug & MIDGARD_DBG_SHADERS) { |
| 2692 | nir_print_shader(nir, stdout); |
| 2693 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2694 | |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 2695 | /* Assign sysvals and counts, now that we're sure |
| 2696 | * (post-optimisation) */ |
| 2697 | |
| 2698 | midgard_nir_assign_sysvals(ctx, nir); |
| 2699 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2700 | program->uniform_count = nir->num_uniforms; |
Alyssa Rosenzweig | 7e8de5a | 2019-04-03 01:48:09 +0000 | [diff] [blame] | 2701 | program->sysval_count = ctx->sysval_count; |
| 2702 | memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2703 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2704 | nir_foreach_function(func, nir) { |
| 2705 | if (!func->impl) |
| 2706 | continue; |
| 2707 | |
| 2708 | list_inithead(&ctx->blocks); |
| 2709 | ctx->block_count = 0; |
| 2710 | ctx->func = func; |
| 2711 | |
| 2712 | emit_cf_list(ctx, &func->impl->body); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2713 | break; /* TODO: Multi-function shaders */ |
| 2714 | } |
| 2715 | |
| 2716 | util_dynarray_init(compiled, NULL); |
| 2717 | |
Alyssa Rosenzweig | cc2ba8e | 2019-08-30 10:53:13 -0700 | [diff] [blame] | 2718 | /* Per-block lowering before opts */ |
| 2719 | |
| 2720 | mir_foreach_block(ctx, block) { |
| 2721 | inline_alu_constants(ctx, block); |
| 2722 | midgard_opt_promote_fmov(ctx, block); |
| 2723 | embedded_to_inline_constant(ctx, block); |
| 2724 | } |
Alyssa Rosenzweig | 4d995e0 | 2019-04-22 04:58:53 +0000 | [diff] [blame] | 2725 | /* MIR-level optimizations */ |
Alyssa Rosenzweig | 84f09ff | 2019-04-21 16:11:11 +0000 | [diff] [blame] | 2726 | |
Alyssa Rosenzweig | 4d995e0 | 2019-04-22 04:58:53 +0000 | [diff] [blame] | 2727 | bool progress = false; |
| 2728 | |
| 2729 | do { |
| 2730 | progress = false; |
| 2731 | |
| 2732 | mir_foreach_block(ctx, block) { |
Alyssa Rosenzweig | 4a03d37 | 2019-05-23 03:01:32 +0000 | [diff] [blame] | 2733 | progress |= midgard_opt_pos_propagate(ctx, block); |
Alyssa Rosenzweig | 4d995e0 | 2019-04-22 04:58:53 +0000 | [diff] [blame] | 2734 | progress |= midgard_opt_copy_prop(ctx, block); |
| 2735 | progress |= midgard_opt_dead_code_eliminate(ctx, block); |
Alyssa Rosenzweig | 9ce7582 | 2019-07-24 15:37:24 -0700 | [diff] [blame] | 2736 | progress |= midgard_opt_combine_projection(ctx, block); |
| 2737 | progress |= midgard_opt_varying_projection(ctx, block); |
Alyssa Rosenzweig | 620c271 | 2019-07-26 13:14:55 -0700 | [diff] [blame] | 2738 | progress |= midgard_opt_not_propagate(ctx, block); |
Alyssa Rosenzweig | d066ca35 | 2019-07-26 13:32:54 -0700 | [diff] [blame] | 2739 | progress |= midgard_opt_fuse_src_invert(ctx, block); |
Alyssa Rosenzweig | b821e1b | 2019-07-26 13:08:54 -0700 | [diff] [blame] | 2740 | progress |= midgard_opt_fuse_dest_invert(ctx, block); |
Alyssa Rosenzweig | c20063a | 2019-09-28 12:39:15 -0400 | [diff] [blame] | 2741 | progress |= midgard_opt_csel_invert(ctx, block); |
Afonso Bordado | 3e1e4ad | 2019-12-10 13:18:00 +0000 | [diff] [blame] | 2742 | progress |= midgard_opt_drop_cmp_invert(ctx, block); |
Afonso Bordado | 525cbe8 | 2019-12-27 17:09:51 +0000 | [diff] [blame] | 2743 | progress |= midgard_opt_invert_branch(ctx, block); |
Alyssa Rosenzweig | 4d995e0 | 2019-04-22 04:58:53 +0000 | [diff] [blame] | 2744 | } |
| 2745 | } while (progress); |
Alyssa Rosenzweig | 84f09ff | 2019-04-21 16:11:11 +0000 | [diff] [blame] | 2746 | |
Alyssa Rosenzweig | 159abd5 | 2019-07-26 11:15:31 -0700 | [diff] [blame] | 2747 | mir_foreach_block(ctx, block) { |
| 2748 | midgard_lower_invert(ctx, block); |
Alyssa Rosenzweig | 8f88732 | 2019-07-29 15:11:12 -0700 | [diff] [blame] | 2749 | midgard_lower_derivatives(ctx, block); |
Alyssa Rosenzweig | 159abd5 | 2019-07-26 11:15:31 -0700 | [diff] [blame] | 2750 | } |
| 2751 | |
Alyssa Rosenzweig | ae20bee | 2019-06-06 11:19:13 -0700 | [diff] [blame] | 2752 | /* Nested control-flow can result in dead branches at the end of the |
| 2753 | * block. This messes with our analysis and is just dead code, so cull |
| 2754 | * them */ |
| 2755 | mir_foreach_block(ctx, block) { |
| 2756 | midgard_opt_cull_dead_branch(ctx, block); |
| 2757 | } |
| 2758 | |
Alyssa Rosenzweig | 159abd5 | 2019-07-26 11:15:31 -0700 | [diff] [blame] | 2759 | /* Ensure we were lowered */ |
| 2760 | mir_foreach_instr_global(ctx, ins) { |
| 2761 | assert(!ins->invert); |
| 2762 | } |
| 2763 | |
Alyssa Rosenzweig | 5bc62af | 2020-01-02 12:27:59 -0500 | [diff] [blame] | 2764 | if (ctx->stage == MESA_SHADER_FRAGMENT) |
| 2765 | mir_add_writeout_loops(ctx); |
| 2766 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2767 | /* Schedule! */ |
Robert Foss | 62adb65 | 2020-01-15 01:14:16 +0100 | [diff] [blame] | 2768 | midgard_schedule_program(ctx); |
Alyssa Rosenzweig | 9dc3b18 | 2019-12-06 09:32:38 -0500 | [diff] [blame] | 2769 | mir_ra(ctx); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2770 | |
| 2771 | /* Now that all the bundles are scheduled and we can calculate block |
| 2772 | * sizes, emit actual branch instructions rather than placeholders */ |
| 2773 | |
| 2774 | int br_block_idx = 0; |
| 2775 | |
| 2776 | mir_foreach_block(ctx, block) { |
| 2777 | util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) { |
| 2778 | for (int c = 0; c < bundle->instruction_count; ++c) { |
Alyssa Rosenzweig | 3c7abbf | 2019-05-22 04:33:21 +0000 | [diff] [blame] | 2779 | midgard_instruction *ins = bundle->instructions[c]; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2780 | |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 2781 | if (!midgard_is_branch_unit(ins->unit)) continue; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2782 | |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2783 | /* Parse some basic branch info */ |
| 2784 | bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT; |
| 2785 | bool is_conditional = ins->branch.conditional; |
| 2786 | bool is_inverted = ins->branch.invert_conditional; |
| 2787 | bool is_discard = ins->branch.target_type == TARGET_DISCARD; |
Alyssa Rosenzweig | 02f503e | 2019-12-30 18:53:04 -0500 | [diff] [blame] | 2788 | bool is_writeout = ins->writeout; |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2789 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2790 | /* Determine the block we're jumping to */ |
| 2791 | int target_number = ins->branch.target_block; |
| 2792 | |
Alyssa Rosenzweig | 3c7abbf | 2019-05-22 04:33:21 +0000 | [diff] [blame] | 2793 | /* Report the destination tag */ |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2794 | int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2795 | |
Alyssa Rosenzweig | 3c7abbf | 2019-05-22 04:33:21 +0000 | [diff] [blame] | 2796 | /* Count up the number of quadwords we're |
| 2797 | * jumping over = number of quadwords until |
| 2798 | * (br_block_idx, target_number) */ |
| 2799 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2800 | int quadword_offset = 0; |
| 2801 | |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2802 | if (is_discard) { |
Alyssa Rosenzweig | 7f75b2b | 2019-07-30 17:07:25 -0700 | [diff] [blame] | 2803 | /* Ignored */ |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2804 | } else if (target_number > br_block_idx) { |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2805 | /* Jump forward */ |
| 2806 | |
| 2807 | for (int idx = br_block_idx + 1; idx < target_number; ++idx) { |
| 2808 | midgard_block *blk = mir_get_block(ctx, idx); |
| 2809 | assert(blk); |
| 2810 | |
| 2811 | quadword_offset += blk->quadword_count; |
| 2812 | } |
| 2813 | } else { |
| 2814 | /* Jump backwards */ |
| 2815 | |
| 2816 | for (int idx = br_block_idx; idx >= target_number; --idx) { |
| 2817 | midgard_block *blk = mir_get_block(ctx, idx); |
| 2818 | assert(blk); |
| 2819 | |
| 2820 | quadword_offset -= blk->quadword_count; |
| 2821 | } |
| 2822 | } |
| 2823 | |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 2824 | /* Unconditional extended branches (far jumps) |
| 2825 | * have issues, so we always use a conditional |
| 2826 | * branch, setting the condition to always for |
| 2827 | * unconditional. For compact unconditional |
| 2828 | * branches, cond isn't used so it doesn't |
| 2829 | * matter what we pick. */ |
| 2830 | |
| 2831 | midgard_condition cond = |
| 2832 | !is_conditional ? midgard_condition_always : |
| 2833 | is_inverted ? midgard_condition_false : |
| 2834 | midgard_condition_true; |
| 2835 | |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2836 | midgard_jmp_writeout_op op = |
| 2837 | is_discard ? midgard_jmp_writeout_op_discard : |
Alyssa Rosenzweig | 02f503e | 2019-12-30 18:53:04 -0500 | [diff] [blame] | 2838 | is_writeout ? midgard_jmp_writeout_op_writeout : |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2839 | (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond : |
| 2840 | midgard_jmp_writeout_op_branch_cond; |
| 2841 | |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 2842 | if (!is_compact) { |
| 2843 | midgard_branch_extended branch = |
| 2844 | midgard_create_branch_extended( |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2845 | cond, op, |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 2846 | dest_tag, |
| 2847 | quadword_offset); |
| 2848 | |
| 2849 | memcpy(&ins->branch_extended, &branch, sizeof(branch)); |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2850 | } else if (is_conditional || is_discard) { |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2851 | midgard_branch_cond branch = { |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2852 | .op = op, |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2853 | .dest_tag = dest_tag, |
| 2854 | .offset = quadword_offset, |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 2855 | .cond = cond |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2856 | }; |
| 2857 | |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 2858 | assert(branch.offset == quadword_offset); |
| 2859 | |
| 2860 | memcpy(&ins->br_compact, &branch, sizeof(branch)); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2861 | } else { |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2862 | assert(op == midgard_jmp_writeout_op_branch_uncond); |
| 2863 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2864 | midgard_branch_uncond branch = { |
Alyssa Rosenzweig | 779e140 | 2019-02-17 23:24:39 +0000 | [diff] [blame] | 2865 | .op = op, |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2866 | .dest_tag = dest_tag, |
| 2867 | .offset = quadword_offset, |
| 2868 | .unknown = 1 |
| 2869 | }; |
| 2870 | |
Alyssa Rosenzweig | 5abb7b5 | 2019-02-17 22:09:09 +0000 | [diff] [blame] | 2871 | assert(branch.offset == quadword_offset); |
| 2872 | |
| 2873 | memcpy(&ins->br_compact, &branch, sizeof(branch)); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2874 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2875 | } |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2876 | } |
| 2877 | |
| 2878 | ++br_block_idx; |
| 2879 | } |
| 2880 | |
| 2881 | /* Emit flat binary from the instruction arrays. Iterate each block in |
| 2882 | * sequence. Save instruction boundaries such that lookahead tags can |
| 2883 | * be assigned easily */ |
| 2884 | |
| 2885 | /* Cache _all_ bundles in source order for lookahead across failed branches */ |
| 2886 | |
| 2887 | int bundle_count = 0; |
| 2888 | mir_foreach_block(ctx, block) { |
| 2889 | bundle_count += block->bundles.size / sizeof(midgard_bundle); |
| 2890 | } |
| 2891 | midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count); |
| 2892 | int bundle_idx = 0; |
| 2893 | mir_foreach_block(ctx, block) { |
| 2894 | util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) { |
| 2895 | source_order_bundles[bundle_idx++] = bundle; |
| 2896 | } |
| 2897 | } |
| 2898 | |
| 2899 | int current_bundle = 0; |
| 2900 | |
Alyssa Rosenzweig | 2a79afc | 2019-05-23 01:56:03 +0000 | [diff] [blame] | 2901 | /* Midgard prefetches instruction types, so during emission we |
| 2902 | * need to lookahead. Unless this is the last instruction, in |
Alyssa Rosenzweig | 5bc62af | 2020-01-02 12:27:59 -0500 | [diff] [blame] | 2903 | * which we return 1. */ |
Alyssa Rosenzweig | 2a79afc | 2019-05-23 01:56:03 +0000 | [diff] [blame] | 2904 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2905 | mir_foreach_block(ctx, block) { |
Alyssa Rosenzweig | d3ad8d6 | 2019-06-06 11:19:44 -0700 | [diff] [blame] | 2906 | mir_foreach_bundle_in_block(block, bundle) { |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2907 | int lookahead = 1; |
| 2908 | |
Alyssa Rosenzweig | 5bc62af | 2020-01-02 12:27:59 -0500 | [diff] [blame] | 2909 | if (!bundle->last_writeout && (current_bundle + 1 < bundle_count)) |
| 2910 | lookahead = source_order_bundles[current_bundle + 1]->tag; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2911 | |
| 2912 | emit_binary_bundle(ctx, bundle, compiled, lookahead); |
| 2913 | ++current_bundle; |
| 2914 | } |
| 2915 | |
| 2916 | /* TODO: Free deeper */ |
| 2917 | //util_dynarray_fini(&block->instructions); |
| 2918 | } |
| 2919 | |
| 2920 | free(source_order_bundles); |
| 2921 | |
Alyssa Rosenzweig | 5e55c11 | 2019-02-17 03:35:03 +0000 | [diff] [blame] | 2922 | /* Report the very first tag executed */ |
| 2923 | program->first_tag = midgard_get_first_tag_from_block(ctx, 0); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2924 | |
| 2925 | /* Deal with off-by-one related to the fencepost problem */ |
| 2926 | program->work_register_count = ctx->work_registers + 1; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2927 | program->uniform_cutoff = ctx->uniform_cutoff; |
| 2928 | |
| 2929 | program->blend_patch_offset = ctx->blend_constant_offset; |
Alyssa Rosenzweig | f0d0061 | 2019-07-19 16:23:52 -0700 | [diff] [blame] | 2930 | program->tls_size = ctx->tls_size; |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2931 | |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 2932 | if (midgard_debug & MIDGARD_DBG_SHADERS) |
Icecream95 | 968f36d | 2020-01-23 09:42:12 +1300 | [diff] [blame] | 2933 | disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage); |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2934 | |
Alyssa Rosenzweig | 35418f6 | 2019-12-16 18:05:21 -0500 | [diff] [blame] | 2935 | if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) { |
Alyssa Rosenzweig | 19bceb5 | 2019-08-30 13:57:20 -0700 | [diff] [blame] | 2936 | unsigned nr_bundles = 0, nr_ins = 0; |
Alyssa Rosenzweig | 138e40d | 2019-07-08 16:42:29 -0700 | [diff] [blame] | 2937 | |
| 2938 | /* Count instructions and bundles */ |
| 2939 | |
Alyssa Rosenzweig | 138e40d | 2019-07-08 16:42:29 -0700 | [diff] [blame] | 2940 | mir_foreach_block(ctx, block) { |
| 2941 | nr_bundles += util_dynarray_num_elements( |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 2942 | &block->bundles, midgard_bundle); |
Alyssa Rosenzweig | 2d739f6 | 2019-07-09 11:16:57 -0700 | [diff] [blame] | 2943 | |
Alyssa Rosenzweig | 67909c8 | 2019-08-30 13:08:16 -0700 | [diff] [blame] | 2944 | mir_foreach_bundle_in_block(block, bun) |
| 2945 | nr_ins += bun->instruction_count; |
Alyssa Rosenzweig | 138e40d | 2019-07-08 16:42:29 -0700 | [diff] [blame] | 2946 | } |
| 2947 | |
| 2948 | /* Calculate thread count. There are certain cutoffs by |
| 2949 | * register count for thread count */ |
| 2950 | |
| 2951 | unsigned nr_registers = program->work_register_count; |
| 2952 | |
| 2953 | unsigned nr_threads = |
| 2954 | (nr_registers <= 4) ? 4 : |
| 2955 | (nr_registers <= 8) ? 2 : |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 2956 | 1; |
Alyssa Rosenzweig | 138e40d | 2019-07-08 16:42:29 -0700 | [diff] [blame] | 2957 | |
| 2958 | /* Dump stats */ |
| 2959 | |
| 2960 | fprintf(stderr, "shader%d - %s shader: " |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 2961 | "%u inst, %u bundles, %u quadwords, " |
Alyssa Rosenzweig | e8dca7e | 2019-07-22 06:32:48 -0700 | [diff] [blame] | 2962 | "%u registers, %u threads, %u loops, " |
Alyssa Rosenzweig | 1a4153b | 2019-08-30 17:29:17 -0700 | [diff] [blame] | 2963 | "%u:%u spills:fills\n", |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 2964 | SHADER_DB_COUNT++, |
| 2965 | gl_shader_stage_name(ctx->stage), |
Alyssa Rosenzweig | 19bceb5 | 2019-08-30 13:57:20 -0700 | [diff] [blame] | 2966 | nr_ins, nr_bundles, ctx->quadword_count, |
Alyssa Rosenzweig | e4bd6fb | 2019-07-10 10:00:50 -0700 | [diff] [blame] | 2967 | nr_registers, nr_threads, |
Alyssa Rosenzweig | e8dca7e | 2019-07-22 06:32:48 -0700 | [diff] [blame] | 2968 | ctx->loop_count, |
| 2969 | ctx->spills, ctx->fills); |
Alyssa Rosenzweig | 138e40d | 2019-07-08 16:42:29 -0700 | [diff] [blame] | 2970 | } |
| 2971 | |
Alyssa Rosenzweig | 4fa0932 | 2019-08-15 08:10:46 -0700 | [diff] [blame] | 2972 | ralloc_free(ctx); |
Alyssa Rosenzweig | 138e40d | 2019-07-08 16:42:29 -0700 | [diff] [blame] | 2973 | |
Alyssa Rosenzweig | e67e072 | 2019-01-30 01:11:31 +0000 | [diff] [blame] | 2974 | return 0; |
| 2975 | } |