Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | /** |
| 25 | * \file brw_vec4_gs_visitor.cpp |
| 26 | * |
| 27 | * Geometry-shader-specific code derived from the vec4_visitor class. |
| 28 | */ |
| 29 | |
| 30 | #include "brw_vec4_gs_visitor.h" |
Iago Toral Quiroga | d2c2ca9 | 2014-07-01 12:43:59 +0200 | [diff] [blame] | 31 | #include "gen6_gs_visitor.h" |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 32 | |
| 33 | const unsigned MAX_GS_INPUT_VERTICES = 6; |
| 34 | |
| 35 | namespace brw { |
| 36 | |
Jason Ekstrand | 4080129 | 2015-06-22 17:17:56 -0700 | [diff] [blame] | 37 | vec4_gs_visitor::vec4_gs_visitor(const struct brw_compiler *compiler, |
Kenneth Graunke | 0163c99 | 2015-06-29 21:58:47 -0700 | [diff] [blame] | 38 | void *log_data, |
Paul Berry | 56a2e57 | 2013-08-23 21:49:50 -0700 | [diff] [blame] | 39 | struct brw_gs_compile *c, |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 40 | struct gl_shader_program *prog, |
Paul Berry | 34cba13 | 2013-10-16 12:13:20 -0700 | [diff] [blame] | 41 | void *mem_ctx, |
Jason Ekstrand | 1b0f6ff | 2015-06-19 15:40:09 -0700 | [diff] [blame] | 42 | bool no_spills, |
| 43 | int shader_time_index) |
Kenneth Graunke | 0163c99 | 2015-06-29 21:58:47 -0700 | [diff] [blame] | 44 | : vec4_visitor(compiler, log_data, |
Kenneth Graunke | 4f4b7c47 | 2015-08-27 18:24:39 -0700 | [diff] [blame] | 45 | &c->gp->program.Base, &c->key.tex, |
Topi Pohjolainen | a290cd0 | 2014-02-18 22:50:13 +0200 | [diff] [blame] | 46 | &c->prog_data.base, prog, MESA_SHADER_GEOMETRY, mem_ctx, |
Jason Ekstrand | 1b0f6ff | 2015-06-19 15:40:09 -0700 | [diff] [blame] | 47 | no_spills, shader_time_index), |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 48 | c(c) |
| 49 | { |
| 50 | } |
| 51 | |
| 52 | |
| 53 | dst_reg * |
Alejandro Piñeiro | 01c5617 | 2015-06-16 17:01:29 +0200 | [diff] [blame] | 54 | vec4_gs_visitor::make_reg_for_system_value(int location, |
| 55 | const glsl_type *type) |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 56 | { |
Alejandro Piñeiro | 01c5617 | 2015-06-16 17:01:29 +0200 | [diff] [blame] | 57 | dst_reg *reg = new(mem_ctx) dst_reg(this, type); |
Jordan Justen | 008338b | 2014-01-25 12:55:24 -0800 | [diff] [blame] | 58 | |
Alejandro Piñeiro | 01c5617 | 2015-06-16 17:01:29 +0200 | [diff] [blame] | 59 | switch (location) { |
Jordan Justen | 008338b | 2014-01-25 12:55:24 -0800 | [diff] [blame] | 60 | case SYSTEM_VALUE_INVOCATION_ID: |
| 61 | this->current_annotation = "initialize gl_InvocationID"; |
| 62 | emit(GS_OPCODE_GET_INSTANCE_ID, *reg); |
| 63 | break; |
| 64 | default: |
Matt Turner | 3d82672 | 2014-06-29 14:54:01 -0700 | [diff] [blame] | 65 | unreachable("not reached"); |
Jordan Justen | 008338b | 2014-01-25 12:55:24 -0800 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | return reg; |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 69 | } |
| 70 | |
| 71 | |
| 72 | int |
Paul Berry | a05589e | 2013-10-16 12:04:19 -0700 | [diff] [blame] | 73 | vec4_gs_visitor::setup_varying_inputs(int payload_reg, int *attribute_map, |
| 74 | int attributes_per_reg) |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 75 | { |
| 76 | /* For geometry shaders there are N copies of the input attributes, where N |
| 77 | * is the number of input vertices. attribute_map[BRW_VARYING_SLOT_COUNT * |
| 78 | * i + j] represents attribute j for vertex i. |
| 79 | * |
| 80 | * Note that GS inputs are read from the VUE 256 bits (2 vec4's) at a time, |
| 81 | * so the total number of input slots that will be delivered to the GS (and |
| 82 | * thus the stride of the input arrays) is urb_read_length * 2. |
| 83 | */ |
| 84 | const unsigned num_input_vertices = c->gp->program.VerticesIn; |
| 85 | assert(num_input_vertices <= MAX_GS_INPUT_VERTICES); |
| 86 | unsigned input_array_stride = c->prog_data.base.urb_read_length * 2; |
| 87 | |
Paul Berry | 8a36f43 | 2013-09-02 14:02:22 -0700 | [diff] [blame] | 88 | for (int slot = 0; slot < c->input_vue_map.num_slots; slot++) { |
| 89 | int varying = c->input_vue_map.slot_to_varying[slot]; |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 90 | for (unsigned vertex = 0; vertex < num_input_vertices; vertex++) { |
| 91 | attribute_map[BRW_VARYING_SLOT_COUNT * vertex + varying] = |
Paul Berry | a05589e | 2013-10-16 12:04:19 -0700 | [diff] [blame] | 92 | attributes_per_reg * payload_reg + input_array_stride * vertex + |
| 93 | slot; |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 94 | } |
| 95 | } |
| 96 | |
Paul Berry | a05589e | 2013-10-16 12:04:19 -0700 | [diff] [blame] | 97 | int regs_used = ALIGN(input_array_stride * num_input_vertices, |
| 98 | attributes_per_reg) / attributes_per_reg; |
| 99 | return payload_reg + regs_used; |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | |
| 103 | void |
| 104 | vec4_gs_visitor::setup_payload() |
| 105 | { |
| 106 | int attribute_map[BRW_VARYING_SLOT_COUNT * MAX_GS_INPUT_VERTICES]; |
| 107 | |
Iago Toral Quiroga | 03164f6 | 2014-07-01 08:52:31 +0200 | [diff] [blame] | 108 | /* If we are in dual instanced or single mode, then attributes are going |
| 109 | * to be interleaved, so one register contains two attribute slots. |
Paul Berry | a05589e | 2013-10-16 12:04:19 -0700 | [diff] [blame] | 110 | */ |
Iago Toral Quiroga | 03164f6 | 2014-07-01 08:52:31 +0200 | [diff] [blame] | 111 | int attributes_per_reg = |
Kenneth Graunke | 0f8ec77 | 2015-03-11 21:18:42 -0700 | [diff] [blame] | 112 | c->prog_data.base.dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2; |
Paul Berry | a05589e | 2013-10-16 12:04:19 -0700 | [diff] [blame] | 113 | |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 114 | /* If a geometry shader tries to read from an input that wasn't written by |
| 115 | * the vertex shader, that produces undefined results, but it shouldn't |
| 116 | * crash anything. So initialize attribute_map to zeros--that ensures that |
| 117 | * these undefined results are read from r0. |
| 118 | */ |
| 119 | memset(attribute_map, 0, sizeof(attribute_map)); |
| 120 | |
| 121 | int reg = 0; |
| 122 | |
| 123 | /* The payload always contains important data in r0, which contains |
| 124 | * the URB handles that are passed on to the URB write at the end |
| 125 | * of the thread. |
| 126 | */ |
| 127 | reg++; |
| 128 | |
Paul Berry | 3374dab | 2013-08-12 08:00:10 -0700 | [diff] [blame] | 129 | /* If the shader uses gl_PrimitiveIDIn, that goes in r1. */ |
| 130 | if (c->prog_data.include_primitive_id) |
Paul Berry | a05589e | 2013-10-16 12:04:19 -0700 | [diff] [blame] | 131 | attribute_map[VARYING_SLOT_PRIMITIVE_ID] = attributes_per_reg * reg++; |
Paul Berry | 3374dab | 2013-08-12 08:00:10 -0700 | [diff] [blame] | 132 | |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 133 | reg = setup_uniforms(reg); |
| 134 | |
Paul Berry | a05589e | 2013-10-16 12:04:19 -0700 | [diff] [blame] | 135 | reg = setup_varying_inputs(reg, attribute_map, attributes_per_reg); |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 136 | |
Iago Toral Quiroga | 03164f6 | 2014-07-01 08:52:31 +0200 | [diff] [blame] | 137 | lower_attributes_to_hw_regs(attribute_map, attributes_per_reg > 1); |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 138 | |
| 139 | this->first_non_payload_grf = reg; |
| 140 | } |
| 141 | |
| 142 | |
| 143 | void |
| 144 | vec4_gs_visitor::emit_prolog() |
| 145 | { |
| 146 | /* In vertex shaders, r0.2 is guaranteed to be initialized to zero. In |
| 147 | * geometry shaders, it isn't (it contains a bunch of information we don't |
| 148 | * need, like the input primitive type). We need r0.2 to be zero in order |
| 149 | * to build scratch read/write messages correctly (otherwise this value |
| 150 | * will be interpreted as a global offset, causing us to do our scratch |
| 151 | * reads/writes to garbage memory). So just set it to zero at the top of |
| 152 | * the shader. |
| 153 | */ |
| 154 | this->current_annotation = "clear r0.2"; |
| 155 | dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD)); |
Iago Toral Quiroga | f373b7e | 2014-07-17 08:54:03 +0200 | [diff] [blame] | 156 | vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, 0u); |
Paul Berry | 3da2c51 | 2013-10-19 13:26:27 -0700 | [diff] [blame] | 157 | inst->force_writemask_all = true; |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 158 | |
| 159 | /* Create a virtual register to hold the vertex count */ |
| 160 | this->vertex_count = src_reg(this, glsl_type::uint_type); |
| 161 | |
| 162 | /* Initialize the vertex_count register to 0 */ |
| 163 | this->current_annotation = "initialize vertex_count"; |
Paul Berry | 3da2c51 | 2013-10-19 13:26:27 -0700 | [diff] [blame] | 164 | inst = emit(MOV(dst_reg(this->vertex_count), 0u)); |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 165 | inst->force_writemask_all = true; |
| 166 | |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 167 | if (c->control_data_header_size_bits > 0) { |
| 168 | /* Create a virtual register to hold the current set of control data |
| 169 | * bits. |
| 170 | */ |
| 171 | this->control_data_bits = src_reg(this, glsl_type::uint_type); |
| 172 | |
| 173 | /* If we're outputting more than 32 control data bits, then EmitVertex() |
| 174 | * will set control_data_bits to 0 after emitting the first vertex. |
| 175 | * Otherwise, we need to initialize it to 0 here. |
| 176 | */ |
| 177 | if (c->control_data_header_size_bits <= 32) { |
| 178 | this->current_annotation = "initialize control data bits"; |
| 179 | inst = emit(MOV(dst_reg(this->control_data_bits), 0u)); |
| 180 | inst->force_writemask_all = true; |
| 181 | } |
| 182 | } |
| 183 | |
Paul Berry | d14fcd7 | 2013-07-12 20:17:13 -0700 | [diff] [blame] | 184 | /* If the geometry shader uses the gl_PointSize input, we need to fix it up |
| 185 | * to account for the fact that the vertex shader stored it in the w |
| 186 | * component of VARYING_SLOT_PSIZ. |
| 187 | */ |
| 188 | if (c->gp->program.Base.InputsRead & VARYING_BIT_PSIZ) { |
| 189 | this->current_annotation = "swizzle gl_PointSize input"; |
| 190 | for (int vertex = 0; vertex < c->gp->program.VerticesIn; vertex++) { |
| 191 | dst_reg dst(ATTR, |
| 192 | BRW_VARYING_SLOT_COUNT * vertex + VARYING_SLOT_PSIZ); |
| 193 | dst.type = BRW_REGISTER_TYPE_F; |
| 194 | src_reg src(dst); |
| 195 | dst.writemask = WRITEMASK_X; |
| 196 | src.swizzle = BRW_SWIZZLE_WWWW; |
Paul Berry | 03ac2c7 | 2013-10-16 13:18:11 -0700 | [diff] [blame] | 197 | inst = emit(MOV(dst, src)); |
| 198 | |
| 199 | /* In dual instanced dispatch mode, dst has a width of 4, so we need |
| 200 | * to make sure the MOV happens regardless of which channels are |
| 201 | * enabled. |
| 202 | */ |
| 203 | inst->force_writemask_all = true; |
Paul Berry | d14fcd7 | 2013-07-12 20:17:13 -0700 | [diff] [blame] | 204 | } |
| 205 | } |
| 206 | |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 207 | this->current_annotation = NULL; |
| 208 | } |
| 209 | |
| 210 | |
| 211 | void |
| 212 | vec4_gs_visitor::emit_program_code() |
| 213 | { |
| 214 | /* We don't support NV_geometry_program4. */ |
Matt Turner | 3d82672 | 2014-06-29 14:54:01 -0700 | [diff] [blame] | 215 | unreachable("Unreached"); |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 216 | } |
| 217 | |
| 218 | |
| 219 | void |
| 220 | vec4_gs_visitor::emit_thread_end() |
| 221 | { |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 222 | if (c->control_data_header_size_bits > 0) { |
| 223 | /* During shader execution, we only ever call emit_control_data_bits() |
| 224 | * just prior to outputting a vertex. Therefore, the control data bits |
| 225 | * corresponding to the most recently output vertex still need to be |
| 226 | * emitted. |
| 227 | */ |
| 228 | current_annotation = "thread end: emit control data bits"; |
| 229 | emit_control_data_bits(); |
| 230 | } |
| 231 | |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 232 | /* MRF 0 is reserved for the debugger, so start with message header |
| 233 | * in MRF 1. |
| 234 | */ |
| 235 | int base_mrf = 1; |
| 236 | |
Kenneth Graunke | f0a618e | 2015-09-24 18:21:59 -0700 | [diff] [blame] | 237 | bool static_vertex_count = c->prog_data.static_vertex_count != -1; |
| 238 | |
Kenneth Graunke | d6a41b5 | 2015-09-25 08:21:57 -0700 | [diff] [blame^] | 239 | /* If the previous instruction was a URB write, we don't need to issue |
| 240 | * a second one - we can just set the EOT bit on the previous write. |
| 241 | * |
| 242 | * Skip this on Gen8+ unless there's a static vertex count, as we also |
| 243 | * need to write the vertex count out, and combining the two may not be |
| 244 | * possible (or at least not straightforward). |
| 245 | */ |
| 246 | vec4_instruction *last = (vec4_instruction *) instructions.get_tail(); |
| 247 | if (last && last->opcode == GS_OPCODE_URB_WRITE && |
| 248 | !(INTEL_DEBUG & DEBUG_SHADER_TIME) && |
| 249 | devinfo->gen >= 8 && static_vertex_count) { |
| 250 | last->urb_write_flags = BRW_URB_WRITE_EOT | last->urb_write_flags; |
| 251 | return; |
| 252 | } |
| 253 | |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 254 | current_annotation = "thread end"; |
| 255 | dst_reg mrf_reg(MRF, base_mrf); |
| 256 | src_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); |
| 257 | vec4_instruction *inst = emit(MOV(mrf_reg, r0)); |
| 258 | inst->force_writemask_all = true; |
Kenneth Graunke | f0a618e | 2015-09-24 18:21:59 -0700 | [diff] [blame] | 259 | if (devinfo->gen < 8 || !static_vertex_count) |
| 260 | emit(GS_OPCODE_SET_VERTEX_COUNT, mrf_reg, this->vertex_count); |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 261 | if (INTEL_DEBUG & DEBUG_SHADER_TIME) |
| 262 | emit_shader_time_end(); |
| 263 | inst = emit(GS_OPCODE_THREAD_END); |
| 264 | inst->base_mrf = base_mrf; |
Kenneth Graunke | f0a618e | 2015-09-24 18:21:59 -0700 | [diff] [blame] | 265 | inst->mlen = devinfo->gen >= 8 && !static_vertex_count ? 2 : 1; |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | |
| 269 | void |
| 270 | vec4_gs_visitor::emit_urb_write_header(int mrf) |
| 271 | { |
| 272 | /* The SEND instruction that writes the vertex data to the VUE will use |
| 273 | * per_slot_offset=true, which means that DWORDs 3 and 4 of the message |
| 274 | * header specify an offset (in multiples of 256 bits) into the URB entry |
| 275 | * at which the write should take place. |
| 276 | * |
| 277 | * So we have to prepare a message header with the appropriate offset |
| 278 | * values. |
| 279 | */ |
| 280 | dst_reg mrf_reg(MRF, mrf); |
| 281 | src_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); |
| 282 | this->current_annotation = "URB write header"; |
| 283 | vec4_instruction *inst = emit(MOV(mrf_reg, r0)); |
| 284 | inst->force_writemask_all = true; |
| 285 | emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, this->vertex_count, |
| 286 | (uint32_t) c->prog_data.output_vertex_size_hwords); |
| 287 | } |
| 288 | |
| 289 | |
| 290 | vec4_instruction * |
| 291 | vec4_gs_visitor::emit_urb_write_opcode(bool complete) |
| 292 | { |
| 293 | /* We don't care whether the vertex is complete, because in general |
| 294 | * geometry shaders output multiple vertices, and we don't terminate the |
| 295 | * thread until all vertices are complete. |
| 296 | */ |
| 297 | (void) complete; |
| 298 | |
| 299 | vec4_instruction *inst = emit(GS_OPCODE_URB_WRITE); |
Paul Berry | 247f90c | 2013-08-18 21:18:19 -0700 | [diff] [blame] | 300 | inst->offset = c->prog_data.control_data_header_size_hwords; |
Kenneth Graunke | ad04e39 | 2013-11-05 16:55:06 -0800 | [diff] [blame] | 301 | |
| 302 | /* We need to increment Global Offset by 1 to make room for Broadwell's |
| 303 | * extra "Vertex Count" payload at the beginning of the URB entry. |
| 304 | */ |
Kenneth Graunke | f0a618e | 2015-09-24 18:21:59 -0700 | [diff] [blame] | 305 | if (devinfo->gen >= 8 && c->prog_data.static_vertex_count == -1) |
Kenneth Graunke | ad04e39 | 2013-11-05 16:55:06 -0800 | [diff] [blame] | 306 | inst->offset++; |
| 307 | |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 308 | inst->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET; |
| 309 | return inst; |
| 310 | } |
| 311 | |
| 312 | |
| 313 | int |
| 314 | vec4_gs_visitor::compute_array_stride(ir_dereference_array *ir) |
| 315 | { |
| 316 | /* Geometry shader inputs are arrays, but they use an unusual array layout: |
| 317 | * instead of all array elements for a given geometry shader input being |
| 318 | * stored consecutively, all geometry shader inputs are interleaved into |
| 319 | * one giant array. At this stage of compilation, we assume that the |
| 320 | * stride of the array is BRW_VARYING_SLOT_COUNT. Later, |
| 321 | * setup_attributes() will remap our accesses to the actual input array. |
| 322 | */ |
| 323 | ir_dereference_variable *deref_var = ir->array->as_dereference_variable(); |
Tapani Pälli | 33ee2c6 | 2013-12-12 13:51:01 +0200 | [diff] [blame] | 324 | if (deref_var && deref_var->var->data.mode == ir_var_shader_in) |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 325 | return BRW_VARYING_SLOT_COUNT; |
| 326 | else |
| 327 | return vec4_visitor::compute_array_stride(ir); |
| 328 | } |
| 329 | |
| 330 | |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 331 | /** |
| 332 | * Write out a batch of 32 control data bits from the control_data_bits |
| 333 | * register to the URB. |
| 334 | * |
| 335 | * The current value of the vertex_count register determines which DWORD in |
| 336 | * the URB receives the control data bits. The control_data_bits register is |
| 337 | * assumed to contain the correct data for the vertex that was most recently |
| 338 | * output, and all previous vertices that share the same DWORD. |
| 339 | * |
| 340 | * This function takes care of ensuring that if no vertices have been output |
| 341 | * yet, no control bits are emitted. |
| 342 | */ |
| 343 | void |
| 344 | vec4_gs_visitor::emit_control_data_bits() |
| 345 | { |
| 346 | assert(c->control_data_bits_per_vertex != 0); |
| 347 | |
| 348 | /* Since the URB_WRITE_OWORD message operates with 128-bit (vec4 sized) |
| 349 | * granularity, we need to use two tricks to ensure that the batch of 32 |
| 350 | * control data bits is written to the appropriate DWORD in the URB. To |
| 351 | * select which vec4 we are writing to, we use the "slot {0,1} offset" |
| 352 | * fields of the message header. To select which DWORD in the vec4 we are |
| 353 | * writing to, we use the channel mask fields of the message header. To |
| 354 | * avoid penalizing geometry shaders that emit a small number of vertices |
| 355 | * with extra bookkeeping, we only do each of these tricks when |
| 356 | * c->prog_data.control_data_header_size_bits is large enough to make it |
| 357 | * necessary. |
| 358 | * |
| 359 | * Note: this means that if we're outputting just a single DWORD of control |
| 360 | * data bits, we'll actually replicate it four times since we won't do any |
| 361 | * channel masking. But that's not a problem since in this case the |
| 362 | * hardware only pays attention to the first DWORD. |
| 363 | */ |
| 364 | enum brw_urb_write_flags urb_write_flags = BRW_URB_WRITE_OWORD; |
| 365 | if (c->control_data_header_size_bits > 32) |
| 366 | urb_write_flags = urb_write_flags | BRW_URB_WRITE_USE_CHANNEL_MASKS; |
| 367 | if (c->control_data_header_size_bits > 128) |
| 368 | urb_write_flags = urb_write_flags | BRW_URB_WRITE_PER_SLOT_OFFSET; |
| 369 | |
Kenneth Graunke | a078e13 | 2015-07-01 17:01:54 -0700 | [diff] [blame] | 370 | /* If we are using either channel masks or a per-slot offset, then we |
| 371 | * need to figure out which DWORD we are trying to write to, using the |
| 372 | * formula: |
| 373 | * |
| 374 | * dword_index = (vertex_count - 1) * bits_per_vertex / 32 |
| 375 | * |
| 376 | * Since bits_per_vertex is a power of two, and is known at compile |
| 377 | * time, this can be optimized to: |
| 378 | * |
| 379 | * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex)) |
| 380 | */ |
| 381 | src_reg dword_index(this, glsl_type::uint_type); |
| 382 | if (urb_write_flags) { |
| 383 | src_reg prev_count(this, glsl_type::uint_type); |
| 384 | emit(ADD(dst_reg(prev_count), this->vertex_count, 0xffffffffu)); |
| 385 | unsigned log2_bits_per_vertex = |
| 386 | _mesa_fls(c->control_data_bits_per_vertex); |
| 387 | emit(SHR(dst_reg(dword_index), prev_count, |
| 388 | (uint32_t) (6 - log2_bits_per_vertex))); |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 389 | } |
Kenneth Graunke | a078e13 | 2015-07-01 17:01:54 -0700 | [diff] [blame] | 390 | |
| 391 | /* Start building the URB write message. The first MRF gets a copy of |
| 392 | * R0. |
| 393 | */ |
| 394 | int base_mrf = 1; |
| 395 | dst_reg mrf_reg(MRF, base_mrf); |
| 396 | src_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); |
| 397 | vec4_instruction *inst = emit(MOV(mrf_reg, r0)); |
| 398 | inst->force_writemask_all = true; |
| 399 | |
| 400 | if (urb_write_flags & BRW_URB_WRITE_PER_SLOT_OFFSET) { |
| 401 | /* Set the per-slot offset to dword_index / 4, to that we'll write to |
| 402 | * the appropriate OWORD within the control data header. |
| 403 | */ |
| 404 | src_reg per_slot_offset(this, glsl_type::uint_type); |
| 405 | emit(SHR(dst_reg(per_slot_offset), dword_index, 2u)); |
| 406 | emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset, 1u); |
| 407 | } |
| 408 | |
| 409 | if (urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS) { |
| 410 | /* Set the channel masks to 1 << (dword_index % 4), so that we'll |
| 411 | * write to the appropriate DWORD within the OWORD. We need to do |
| 412 | * this computation with force_writemask_all, otherwise garbage data |
| 413 | * from invocation 0 might clobber the mask for invocation 1 when |
| 414 | * GS_OPCODE_PREPARE_CHANNEL_MASKS tries to OR the two masks |
| 415 | * together. |
| 416 | */ |
| 417 | src_reg channel(this, glsl_type::uint_type); |
| 418 | inst = emit(AND(dst_reg(channel), dword_index, 3u)); |
| 419 | inst->force_writemask_all = true; |
| 420 | src_reg one(this, glsl_type::uint_type); |
| 421 | inst = emit(MOV(dst_reg(one), 1u)); |
| 422 | inst->force_writemask_all = true; |
| 423 | src_reg channel_mask(this, glsl_type::uint_type); |
| 424 | inst = emit(SHL(dst_reg(channel_mask), one, channel)); |
| 425 | inst->force_writemask_all = true; |
| 426 | emit(GS_OPCODE_PREPARE_CHANNEL_MASKS, dst_reg(channel_mask), |
| 427 | channel_mask); |
| 428 | emit(GS_OPCODE_SET_CHANNEL_MASKS, mrf_reg, channel_mask); |
| 429 | } |
| 430 | |
| 431 | /* Store the control data bits in the message payload and send it. */ |
| 432 | dst_reg mrf_reg2(MRF, base_mrf + 1); |
| 433 | inst = emit(MOV(mrf_reg2, this->control_data_bits)); |
| 434 | inst->force_writemask_all = true; |
| 435 | inst = emit(GS_OPCODE_URB_WRITE); |
| 436 | inst->urb_write_flags = urb_write_flags; |
| 437 | /* We need to increment Global Offset by 256-bits to make room for |
| 438 | * Broadwell's extra "Vertex Count" payload at the beginning of the |
| 439 | * URB entry. Since this is an OWord message, Global Offset is counted |
| 440 | * in 128-bit units, so we must set it to 2. |
| 441 | */ |
Kenneth Graunke | f0a618e | 2015-09-24 18:21:59 -0700 | [diff] [blame] | 442 | if (devinfo->gen >= 8 && c->prog_data.static_vertex_count == -1) |
Kenneth Graunke | a078e13 | 2015-07-01 17:01:54 -0700 | [diff] [blame] | 443 | inst->offset = 2; |
| 444 | inst->base_mrf = base_mrf; |
| 445 | inst->mlen = 2; |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 446 | } |
| 447 | |
Iago Toral Quiroga | 5d56258 | 2014-06-03 16:38:44 +0200 | [diff] [blame] | 448 | void |
| 449 | vec4_gs_visitor::set_stream_control_data_bits(unsigned stream_id) |
| 450 | { |
| 451 | /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */ |
| 452 | |
| 453 | /* Note: we are calling this *before* increasing vertex_count, so |
| 454 | * this->vertex_count == vertex_count - 1 in the formula above. |
| 455 | */ |
| 456 | |
| 457 | /* Stream mode uses 2 bits per vertex */ |
| 458 | assert(c->control_data_bits_per_vertex == 2); |
| 459 | |
| 460 | /* Must be a valid stream */ |
| 461 | assert(stream_id >= 0 && stream_id < MAX_VERTEX_STREAMS); |
| 462 | |
| 463 | /* Control data bits are initialized to 0 so we don't have to set any |
| 464 | * bits when sending vertices to stream 0. |
| 465 | */ |
| 466 | if (stream_id == 0) |
| 467 | return; |
| 468 | |
| 469 | /* reg::sid = stream_id */ |
| 470 | src_reg sid(this, glsl_type::uint_type); |
| 471 | emit(MOV(dst_reg(sid), stream_id)); |
| 472 | |
| 473 | /* reg:shift_count = 2 * (vertex_count - 1) */ |
| 474 | src_reg shift_count(this, glsl_type::uint_type); |
| 475 | emit(SHL(dst_reg(shift_count), this->vertex_count, 1u)); |
| 476 | |
| 477 | /* Note: we're relying on the fact that the GEN SHL instruction only pays |
| 478 | * attention to the lower 5 bits of its second source argument, so on this |
| 479 | * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to |
| 480 | * stream_id << ((2 * (vertex_count - 1)) % 32). |
| 481 | */ |
| 482 | src_reg mask(this, glsl_type::uint_type); |
| 483 | emit(SHL(dst_reg(mask), sid, shift_count)); |
| 484 | emit(OR(dst_reg(this->control_data_bits), this->control_data_bits, mask)); |
| 485 | } |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 486 | |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 487 | void |
Iago Toral Quiroga | 7ade427 | 2015-06-29 13:37:31 +0200 | [diff] [blame] | 488 | vec4_gs_visitor::gs_emit_vertex(int stream_id) |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 489 | { |
| 490 | this->current_annotation = "emit vertex: safety check"; |
| 491 | |
Iago Toral Quiroga | 2042a2f | 2015-03-09 15:17:03 +0100 | [diff] [blame] | 492 | /* Haswell and later hardware ignores the "Render Stream Select" bits |
| 493 | * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled, |
| 494 | * and instead sends all primitives down the pipeline for rasterization. |
| 495 | * If the SOL stage is enabled, "Render Stream Select" is honored and |
| 496 | * primitives bound to non-zero streams are discarded after stream output. |
| 497 | * |
| 498 | * Since the only purpose of primives sent to non-zero streams is to |
| 499 | * be recorded by transform feedback, we can simply discard all geometry |
| 500 | * bound to these streams when transform feedback is disabled. |
| 501 | */ |
Iago Toral Quiroga | 7ade427 | 2015-06-29 13:37:31 +0200 | [diff] [blame] | 502 | if (stream_id > 0 && shader_prog->TransformFeedback.NumVarying == 0) |
Iago Toral Quiroga | 2042a2f | 2015-03-09 15:17:03 +0100 | [diff] [blame] | 503 | return; |
| 504 | |
Kenneth Graunke | 31a36ff | 2015-09-03 01:01:29 -0700 | [diff] [blame] | 505 | /* If we're outputting 32 control data bits or less, then we can wait |
| 506 | * until the shader is over to output them all. Otherwise we need to |
| 507 | * output them as we go. Now is the time to do it, since we're about to |
| 508 | * output the vertex_count'th vertex, so it's guaranteed that the |
| 509 | * control data bits associated with the (vertex_count - 1)th vertex are |
| 510 | * correct. |
| 511 | */ |
| 512 | if (c->control_data_header_size_bits > 32) { |
| 513 | this->current_annotation = "emit vertex: emit control data bits"; |
| 514 | /* Only emit control data bits if we've finished accumulating a batch |
| 515 | * of 32 bits. This is the case when: |
| 516 | * |
| 517 | * (vertex_count * bits_per_vertex) % 32 == 0 |
| 518 | * |
| 519 | * (in other words, when the last 5 bits of vertex_count * |
| 520 | * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some |
| 521 | * integer n (which is always the case, since bits_per_vertex is |
| 522 | * always 1 or 2), this is equivalent to requiring that the last 5-n |
| 523 | * bits of vertex_count are 0: |
| 524 | * |
| 525 | * vertex_count & (2^(5-n) - 1) == 0 |
| 526 | * |
| 527 | * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is |
| 528 | * equivalent to: |
| 529 | * |
| 530 | * vertex_count & (32 / bits_per_vertex - 1) == 0 |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 531 | */ |
Kenneth Graunke | 31a36ff | 2015-09-03 01:01:29 -0700 | [diff] [blame] | 532 | vec4_instruction *inst = |
| 533 | emit(AND(dst_null_d(), this->vertex_count, |
| 534 | (uint32_t) (32 / c->control_data_bits_per_vertex - 1))); |
| 535 | inst->conditional_mod = BRW_CONDITIONAL_Z; |
| 536 | |
| 537 | emit(IF(BRW_PREDICATE_NORMAL)); |
| 538 | { |
| 539 | /* If vertex_count is 0, then no control data bits have been |
| 540 | * accumulated yet, so we skip emitting them. |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 541 | */ |
Kenneth Graunke | 31a36ff | 2015-09-03 01:01:29 -0700 | [diff] [blame] | 542 | emit(CMP(dst_null_d(), this->vertex_count, 0u, |
| 543 | BRW_CONDITIONAL_NEQ)); |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 544 | emit(IF(BRW_PREDICATE_NORMAL)); |
Kenneth Graunke | 31a36ff | 2015-09-03 01:01:29 -0700 | [diff] [blame] | 545 | emit_control_data_bits(); |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 546 | emit(BRW_OPCODE_ENDIF); |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 547 | |
Kenneth Graunke | 31a36ff | 2015-09-03 01:01:29 -0700 | [diff] [blame] | 548 | /* Reset control_data_bits to 0 so we can start accumulating a new |
| 549 | * batch. |
| 550 | * |
| 551 | * Note: in the case where vertex_count == 0, this neutralizes the |
| 552 | * effect of any call to EndPrimitive() that the shader may have |
| 553 | * made before outputting its first vertex. |
| 554 | */ |
| 555 | inst = emit(MOV(dst_reg(this->control_data_bits), 0u)); |
| 556 | inst->force_writemask_all = true; |
Iago Toral Quiroga | 5d56258 | 2014-06-03 16:38:44 +0200 | [diff] [blame] | 557 | } |
Kenneth Graunke | 31a36ff | 2015-09-03 01:01:29 -0700 | [diff] [blame] | 558 | emit(BRW_OPCODE_ENDIF); |
| 559 | } |
| 560 | |
| 561 | this->current_annotation = "emit vertex: vertex data"; |
| 562 | emit_vertex(); |
| 563 | |
| 564 | /* In stream mode we have to set control data bits for all vertices |
| 565 | * unless we have disabled control data bits completely (which we do |
| 566 | * do for GL_POINTS outputs that don't use streams). |
| 567 | */ |
| 568 | if (c->control_data_header_size_bits > 0 && |
| 569 | c->prog_data.control_data_format == |
| 570 | GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID) { |
| 571 | this->current_annotation = "emit vertex: Stream control data bits"; |
| 572 | set_stream_control_data_bits(stream_id); |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 573 | } |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 574 | |
| 575 | this->current_annotation = NULL; |
| 576 | } |
| 577 | |
| 578 | void |
Iago Toral Quiroga | 7ade427 | 2015-06-29 13:37:31 +0200 | [diff] [blame] | 579 | vec4_gs_visitor::visit(ir_emit_vertex *ir) |
| 580 | { |
Kenneth Graunke | df31c18 | 2015-08-05 09:16:59 -0700 | [diff] [blame] | 581 | /* To ensure that we don't output more vertices than the shader specified |
| 582 | * using max_vertices, do the logic inside a conditional of the form "if |
| 583 | * (vertex_count < MAX)" |
| 584 | */ |
| 585 | unsigned num_output_vertices = c->gp->program.VerticesOut; |
| 586 | emit(CMP(dst_null_d(), this->vertex_count, |
| 587 | src_reg(num_output_vertices), BRW_CONDITIONAL_L)); |
| 588 | emit(IF(BRW_PREDICATE_NORMAL)); |
| 589 | |
Iago Toral Quiroga | 7ade427 | 2015-06-29 13:37:31 +0200 | [diff] [blame] | 590 | gs_emit_vertex(ir->stream_id()); |
Kenneth Graunke | df31c18 | 2015-08-05 09:16:59 -0700 | [diff] [blame] | 591 | |
| 592 | this->current_annotation = "emit vertex: increment vertex count"; |
| 593 | emit(ADD(dst_reg(this->vertex_count), this->vertex_count, |
| 594 | src_reg(1u))); |
| 595 | |
| 596 | emit(BRW_OPCODE_ENDIF); |
Iago Toral Quiroga | 7ade427 | 2015-06-29 13:37:31 +0200 | [diff] [blame] | 597 | } |
| 598 | |
| 599 | void |
| 600 | vec4_gs_visitor::gs_end_primitive() |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 601 | { |
Paul Berry | ebcdaa7 | 2013-04-21 08:51:33 -0700 | [diff] [blame] | 602 | /* We can only do EndPrimitive() functionality when the control data |
| 603 | * consists of cut bits. Fortunately, the only time it isn't is when the |
| 604 | * output type is points, in which case EndPrimitive() is a no-op. |
| 605 | */ |
| 606 | if (c->prog_data.control_data_format != |
| 607 | GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT) { |
| 608 | return; |
| 609 | } |
| 610 | |
| 611 | /* Cut bits use one bit per vertex. */ |
| 612 | assert(c->control_data_bits_per_vertex == 1); |
| 613 | |
| 614 | /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting |
| 615 | * vertex n, 0 otherwise. So all we need to do here is mark bit |
| 616 | * (vertex_count - 1) % 32 in the cut_bits register to indicate that |
| 617 | * EndPrimitive() was called after emitting vertex (vertex_count - 1); |
| 618 | * vec4_gs_visitor::emit_control_data_bits() will take care of the rest. |
| 619 | * |
| 620 | * Note that if EndPrimitve() is called before emitting any vertices, this |
| 621 | * will cause us to set bit 31 of the control_data_bits register to 1. |
| 622 | * That's fine because: |
| 623 | * |
| 624 | * - If max_vertices < 32, then vertex number 31 (zero-based) will never be |
| 625 | * output, so the hardware will ignore cut bit 31. |
| 626 | * |
| 627 | * - If max_vertices == 32, then vertex number 31 is guaranteed to be the |
| 628 | * last vertex, so setting cut bit 31 has no effect (since the primitive |
| 629 | * is automatically ended when the GS terminates). |
| 630 | * |
| 631 | * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the |
| 632 | * control_data_bits register to 0 when the first vertex is emitted. |
| 633 | */ |
| 634 | |
| 635 | /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */ |
| 636 | src_reg one(this, glsl_type::uint_type); |
| 637 | emit(MOV(dst_reg(one), 1u)); |
| 638 | src_reg prev_count(this, glsl_type::uint_type); |
| 639 | emit(ADD(dst_reg(prev_count), this->vertex_count, 0xffffffffu)); |
| 640 | src_reg mask(this, glsl_type::uint_type); |
| 641 | /* Note: we're relying on the fact that the GEN SHL instruction only pays |
| 642 | * attention to the lower 5 bits of its second source argument, so on this |
| 643 | * architecture, 1 << (vertex_count - 1) is equivalent to 1 << |
| 644 | * ((vertex_count - 1) % 32). |
| 645 | */ |
| 646 | emit(SHL(dst_reg(mask), one, prev_count)); |
| 647 | emit(OR(dst_reg(this->control_data_bits), this->control_data_bits, mask)); |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 648 | } |
| 649 | |
Iago Toral Quiroga | 7ade427 | 2015-06-29 13:37:31 +0200 | [diff] [blame] | 650 | void |
| 651 | vec4_gs_visitor::visit(ir_end_primitive *) |
| 652 | { |
| 653 | gs_end_primitive(); |
| 654 | } |
| 655 | |
Kenneth Graunke | 9eb568d | 2012-12-06 22:37:34 -0800 | [diff] [blame] | 656 | static const unsigned * |
| 657 | generate_assembly(struct brw_context *brw, |
| 658 | struct gl_shader_program *shader_prog, |
| 659 | struct gl_program *prog, |
Kristian Høgsberg | bf23079 | 2014-11-25 14:29:48 -0800 | [diff] [blame] | 660 | struct brw_vue_prog_data *prog_data, |
Kenneth Graunke | 9eb568d | 2012-12-06 22:37:34 -0800 | [diff] [blame] | 661 | void *mem_ctx, |
Matt Turner | a3d0ccb | 2014-07-11 21:16:13 -0700 | [diff] [blame] | 662 | const cfg_t *cfg, |
Kenneth Graunke | 9eb568d | 2012-12-06 22:37:34 -0800 | [diff] [blame] | 663 | unsigned *final_assembly_size) |
| 664 | { |
Jason Ekstrand | d7565b7 | 2015-04-16 14:34:04 -0700 | [diff] [blame] | 665 | vec4_generator g(brw->intelScreen->compiler, brw, |
Jason Ekstrand | e639a6f | 2015-04-16 14:13:52 -0700 | [diff] [blame] | 666 | shader_prog, prog, prog_data, mem_ctx, |
Kenneth Graunke | 3167a80 | 2015-01-13 14:56:54 -0800 | [diff] [blame] | 667 | INTEL_DEBUG & DEBUG_GS, "geometry", "GS"); |
Matt Turner | a3d0ccb | 2014-07-11 21:16:13 -0700 | [diff] [blame] | 668 | return g.generate_assembly(cfg, final_assembly_size); |
Kenneth Graunke | 9eb568d | 2012-12-06 22:37:34 -0800 | [diff] [blame] | 669 | } |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 670 | |
Paul Berry | 4ec2604 | 2013-03-22 12:34:19 -0700 | [diff] [blame] | 671 | extern "C" const unsigned * |
| 672 | brw_gs_emit(struct brw_context *brw, |
| 673 | struct gl_shader_program *prog, |
| 674 | struct brw_gs_compile *c, |
| 675 | void *mem_ctx, |
| 676 | unsigned *final_assembly_size) |
| 677 | { |
Topi Pohjolainen | a290cd0 | 2014-02-18 22:50:13 +0200 | [diff] [blame] | 678 | if (unlikely(INTEL_DEBUG & DEBUG_GS)) { |
| 679 | struct brw_shader *shader = |
| 680 | (brw_shader *) prog->_LinkedShaders[MESA_SHADER_GEOMETRY]; |
Paul Berry | 4ec2604 | 2013-03-22 12:34:19 -0700 | [diff] [blame] | 681 | |
Ian Romanick | 7d560a3 | 2014-10-20 15:50:36 -0700 | [diff] [blame] | 682 | brw_dump_ir("geometry", prog, &shader->base, NULL); |
Topi Pohjolainen | a290cd0 | 2014-02-18 22:50:13 +0200 | [diff] [blame] | 683 | } |
Paul Berry | 4ec2604 | 2013-03-22 12:34:19 -0700 | [diff] [blame] | 684 | |
Jason Ekstrand | 1b0f6ff | 2015-06-19 15:40:09 -0700 | [diff] [blame] | 685 | int st_index = -1; |
| 686 | if (INTEL_DEBUG & DEBUG_SHADER_TIME) |
| 687 | st_index = brw_get_shader_time_index(brw, prog, NULL, ST_GS); |
| 688 | |
Iago Toral Quiroga | d2c2ca9 | 2014-07-01 12:43:59 +0200 | [diff] [blame] | 689 | if (brw->gen >= 7) { |
| 690 | /* Compile the geometry shader in DUAL_OBJECT dispatch mode, if we can do |
| 691 | * so without spilling. If the GS invocations count > 1, then we can't use |
| 692 | * dual object mode. |
| 693 | */ |
| 694 | if (c->prog_data.invocations <= 1 && |
| 695 | likely(!(INTEL_DEBUG & DEBUG_NO_DUAL_OBJECT_GS))) { |
Kenneth Graunke | 0f8ec77 | 2015-03-11 21:18:42 -0700 | [diff] [blame] | 696 | c->prog_data.base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT; |
Paul Berry | 3c2feb1 | 2013-10-16 12:27:37 -0700 | [diff] [blame] | 697 | |
Kenneth Graunke | 0163c99 | 2015-06-29 21:58:47 -0700 | [diff] [blame] | 698 | vec4_gs_visitor v(brw->intelScreen->compiler, brw, |
Jason Ekstrand | 4080129 | 2015-06-22 17:17:56 -0700 | [diff] [blame] | 699 | c, prog, mem_ctx, true /* no_spills */, st_index); |
Kenneth Graunke | 014b902 | 2015-08-27 23:49:03 -0700 | [diff] [blame] | 700 | if (v.run()) { |
Iago Toral Quiroga | d2c2ca9 | 2014-07-01 12:43:59 +0200 | [diff] [blame] | 701 | return generate_assembly(brw, prog, &c->gp->program.Base, |
| 702 | &c->prog_data.base, mem_ctx, v.cfg, |
| 703 | final_assembly_size); |
| 704 | } |
Paul Berry | 3c2feb1 | 2013-10-16 12:27:37 -0700 | [diff] [blame] | 705 | } |
| 706 | } |
| 707 | |
| 708 | /* Either we failed to compile in DUAL_OBJECT mode (probably because it |
| 709 | * would have required spilling) or DUAL_OBJECT mode is disabled. So fall |
Iago Toral Quiroga | 03164f6 | 2014-07-01 08:52:31 +0200 | [diff] [blame] | 710 | * back to DUAL_INSTANCED or SINGLE mode, which consumes fewer registers. |
Paul Berry | 3c2feb1 | 2013-10-16 12:27:37 -0700 | [diff] [blame] | 711 | * |
Iago Toral Quiroga | 03164f6 | 2014-07-01 08:52:31 +0200 | [diff] [blame] | 712 | * FIXME: Single dispatch mode requires that the driver can handle |
| 713 | * interleaving of input registers, but this is already supported (dual |
| 714 | * instance mode has the same requirement). However, to take full advantage |
| 715 | * of single dispatch mode to reduce register pressure we would also need to |
| 716 | * do interleaved outputs, but currently, the vec4 visitor and generator |
| 717 | * classes do not support this, so at the moment register pressure in |
| 718 | * single and dual instance modes is the same. |
| 719 | * |
| 720 | * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 "3DSTATE_GS" |
| 721 | * "If InstanceCount>1, DUAL_OBJECT mode is invalid. Software will likely |
| 722 | * want to use DUAL_INSTANCE mode for higher performance, but SINGLE mode |
| 723 | * is also supported. When InstanceCount=1 (one instance per object) software |
| 724 | * can decide which dispatch mode to use. DUAL_OBJECT mode would likely be |
| 725 | * the best choice for performance, followed by SINGLE mode." |
| 726 | * |
| 727 | * So SINGLE mode is more performant when invocations == 1 and DUAL_INSTANCE |
| 728 | * mode is more performant when invocations > 1. Gen6 only supports |
| 729 | * SINGLE mode. |
Paul Berry | 3c2feb1 | 2013-10-16 12:27:37 -0700 | [diff] [blame] | 730 | */ |
Iago Toral Quiroga | d2c2ca9 | 2014-07-01 12:43:59 +0200 | [diff] [blame] | 731 | if (c->prog_data.invocations <= 1 || brw->gen < 7) |
Kenneth Graunke | 0f8ec77 | 2015-03-11 21:18:42 -0700 | [diff] [blame] | 732 | c->prog_data.base.dispatch_mode = DISPATCH_MODE_4X1_SINGLE; |
Iago Toral Quiroga | 03164f6 | 2014-07-01 08:52:31 +0200 | [diff] [blame] | 733 | else |
Kenneth Graunke | 0f8ec77 | 2015-03-11 21:18:42 -0700 | [diff] [blame] | 734 | c->prog_data.base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_INSTANCE; |
Paul Berry | a05589e | 2013-10-16 12:04:19 -0700 | [diff] [blame] | 735 | |
Iago Toral Quiroga | d2c2ca9 | 2014-07-01 12:43:59 +0200 | [diff] [blame] | 736 | vec4_gs_visitor *gs = NULL; |
| 737 | const unsigned *ret = NULL; |
| 738 | |
| 739 | if (brw->gen >= 7) |
Kenneth Graunke | 0163c99 | 2015-06-29 21:58:47 -0700 | [diff] [blame] | 740 | gs = new vec4_gs_visitor(brw->intelScreen->compiler, brw, |
Jason Ekstrand | 4080129 | 2015-06-22 17:17:56 -0700 | [diff] [blame] | 741 | c, prog, mem_ctx, false /* no_spills */, |
Jason Ekstrand | 1b0f6ff | 2015-06-19 15:40:09 -0700 | [diff] [blame] | 742 | st_index); |
Iago Toral Quiroga | d2c2ca9 | 2014-07-01 12:43:59 +0200 | [diff] [blame] | 743 | else |
Kenneth Graunke | 0163c99 | 2015-06-29 21:58:47 -0700 | [diff] [blame] | 744 | gs = new gen6_gs_visitor(brw->intelScreen->compiler, brw, |
Jason Ekstrand | 4080129 | 2015-06-22 17:17:56 -0700 | [diff] [blame] | 745 | c, prog, mem_ctx, false /* no_spills */, |
Jason Ekstrand | 1b0f6ff | 2015-06-19 15:40:09 -0700 | [diff] [blame] | 746 | st_index); |
Iago Toral Quiroga | d2c2ca9 | 2014-07-01 12:43:59 +0200 | [diff] [blame] | 747 | |
Kenneth Graunke | 014b902 | 2015-08-27 23:49:03 -0700 | [diff] [blame] | 748 | if (!gs->run()) { |
Paul Berry | 4ec2604 | 2013-03-22 12:34:19 -0700 | [diff] [blame] | 749 | prog->LinkStatus = false; |
Iago Toral Quiroga | d2c2ca9 | 2014-07-01 12:43:59 +0200 | [diff] [blame] | 750 | ralloc_strcat(&prog->InfoLog, gs->fail_msg); |
| 751 | } else { |
| 752 | ret = generate_assembly(brw, prog, &c->gp->program.Base, |
| 753 | &c->prog_data.base, mem_ctx, gs->cfg, |
| 754 | final_assembly_size); |
Paul Berry | 4ec2604 | 2013-03-22 12:34:19 -0700 | [diff] [blame] | 755 | } |
| 756 | |
Iago Toral Quiroga | d2c2ca9 | 2014-07-01 12:43:59 +0200 | [diff] [blame] | 757 | delete gs; |
| 758 | return ret; |
Paul Berry | 4ec2604 | 2013-03-22 12:34:19 -0700 | [diff] [blame] | 759 | } |
| 760 | |
| 761 | |
Paul Berry | 16512ba | 2013-02-19 07:31:16 -0800 | [diff] [blame] | 762 | } /* namespace brw */ |