Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
Eric Anholt | 185b5a5 | 2013-06-18 13:52:03 -0700 | [diff] [blame] | 24 | #include <errno.h> |
Eric Anholt | db31bc5 | 2013-02-07 18:46:18 -0800 | [diff] [blame] | 25 | #include "intel_batchbuffer.h" |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 26 | #include "intel_fbo.h" |
| 27 | |
| 28 | #include "brw_blorp.h" |
Jason Ekstrand | c1fe885 | 2016-04-27 17:16:30 -0700 | [diff] [blame] | 29 | #include "brw_compiler.h" |
| 30 | #include "brw_nir.h" |
Kenneth Graunke | 6f7c41d | 2013-09-30 18:11:03 -0700 | [diff] [blame] | 31 | #include "brw_state.h" |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 32 | |
Eric Anholt | a2ca98b | 2013-05-30 14:53:55 -0700 | [diff] [blame] | 33 | #define FILE_DEBUG_FLAG DEBUG_BLORP |
| 34 | |
Jason Ekstrand | 406c503 | 2016-07-22 14:41:43 -0700 | [diff] [blame] | 35 | static void |
| 36 | apply_gen6_stencil_hiz_offset(struct isl_surf *surf, |
| 37 | struct intel_mipmap_tree *mt, |
| 38 | uint32_t lod, |
| 39 | uint32_t *offset) |
| 40 | { |
| 41 | assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD); |
| 42 | |
Jason Ekstrand | d8644f3 | 2016-07-19 19:59:16 -0700 | [diff] [blame^] | 43 | if (mt->format == MESA_FORMAT_S_UINT8) { |
| 44 | /* Note: we can't compute the stencil offset using |
| 45 | * intel_miptree_get_aligned_offset(), because the miptree |
| 46 | * claims that the region is untiled even though it's W tiled. |
| 47 | */ |
| 48 | *offset = mt->level[lod].level_y * mt->pitch + |
| 49 | mt->level[lod].level_x * 64; |
| 50 | } else { |
| 51 | *offset = intel_miptree_get_aligned_offset(mt, |
| 52 | mt->level[lod].level_x, |
| 53 | mt->level[lod].level_y, |
| 54 | false); |
| 55 | } |
Jason Ekstrand | 406c503 | 2016-07-22 14:41:43 -0700 | [diff] [blame] | 56 | |
| 57 | surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod); |
| 58 | surf->logical_level0_px.height = minify(surf->logical_level0_px.height, lod); |
| 59 | surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod); |
| 60 | surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod); |
| 61 | surf->levels = 1; |
| 62 | surf->array_pitch_el_rows = |
| 63 | ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height); |
| 64 | } |
| 65 | |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 66 | void |
Jason Ekstrand | b6dd8e4 | 2016-04-21 16:39:56 -0700 | [diff] [blame] | 67 | brw_blorp_surface_info_init(struct brw_context *brw, |
| 68 | struct brw_blorp_surface_info *info, |
Jason Ekstrand | a543f74 | 2016-04-21 16:19:51 -0700 | [diff] [blame] | 69 | struct intel_mipmap_tree *mt, |
| 70 | unsigned int level, unsigned int layer, |
| 71 | mesa_format format, bool is_render_target) |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 72 | { |
Paul Berry | b5fe413 | 2013-12-03 21:15:47 -0800 | [diff] [blame] | 73 | /* Layer is a physical layer, so if this is a 2D multisample array texture |
| 74 | * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better |
| 75 | * be a multiple of num_samples. |
| 76 | */ |
Jason Ekstrand | 7997f4f | 2016-06-23 20:11:46 -0700 | [diff] [blame] | 77 | unsigned layer_multiplier = 1; |
Paul Berry | b5fe413 | 2013-12-03 21:15:47 -0800 | [diff] [blame] | 78 | if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS || |
| 79 | mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { |
Topi Pohjolainen | 01ba26d | 2016-04-18 08:51:10 +0300 | [diff] [blame] | 80 | assert(mt->num_samples <= 1 || layer % mt->num_samples == 0); |
Jason Ekstrand | 7997f4f | 2016-06-23 20:11:46 -0700 | [diff] [blame] | 81 | layer_multiplier = MAX2(mt->num_samples, 1); |
Paul Berry | b5fe413 | 2013-12-03 21:15:47 -0800 | [diff] [blame] | 82 | } |
| 83 | |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 84 | intel_miptree_check_level_layer(mt, level, layer); |
| 85 | |
Jason Ekstrand | d540864 | 2016-07-22 14:24:06 -0700 | [diff] [blame] | 86 | if (is_render_target) |
| 87 | intel_miptree_used_for_rendering(mt); |
Jason Ekstrand | b82de88 | 2016-06-22 15:33:44 -0700 | [diff] [blame] | 88 | |
| 89 | intel_miptree_get_isl_surf(brw, mt, &info->surf); |
Jason Ekstrand | d540864 | 2016-07-22 14:24:06 -0700 | [diff] [blame] | 90 | info->bo = mt->bo; |
| 91 | info->offset = mt->offset; |
Jason Ekstrand | b82de88 | 2016-06-22 15:33:44 -0700 | [diff] [blame] | 92 | |
Jason Ekstrand | d8644f3 | 2016-07-19 19:59:16 -0700 | [diff] [blame^] | 93 | if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 && |
| 94 | mt->array_layout == ALL_SLICES_AT_EACH_LOD) { |
| 95 | /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in |
| 96 | * order to allow for layered rendering. The hack makes each LOD of the |
| 97 | * stencil or HiZ buffer a single tightly packed array surface at some |
| 98 | * offset into the surface. Since ISL doesn't know how to deal with the |
| 99 | * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual |
| 100 | * offset of it anyway, we might as well do the offset here and keep the |
| 101 | * hacks inside the i965 driver. |
| 102 | * |
| 103 | * See also gen6_depth_stencil_state.c |
| 104 | */ |
| 105 | uint32_t offset; |
| 106 | apply_gen6_stencil_hiz_offset(&info->surf, mt, level, &offset); |
| 107 | info->offset += offset; |
| 108 | level = 0; |
| 109 | } |
| 110 | |
Jason Ekstrand | 406c503 | 2016-07-22 14:41:43 -0700 | [diff] [blame] | 111 | intel_miptree_get_aux_isl_surf(brw, mt, &info->aux_surf, |
| 112 | &info->aux_usage); |
Jason Ekstrand | 4d86b3f | 2016-07-01 16:01:56 -0700 | [diff] [blame] | 113 | |
Jason Ekstrand | 406c503 | 2016-07-22 14:41:43 -0700 | [diff] [blame] | 114 | /* For textures that are in the RESOLVED state, we ignore the MCS */ |
| 115 | if (mt->mcs_mt && !is_render_target && |
| 116 | mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED) |
| 117 | info->aux_usage = ISL_AUX_USAGE_NONE; |
| 118 | |
| 119 | if (info->aux_usage != ISL_AUX_USAGE_NONE) { |
Jason Ekstrand | 4d86b3f | 2016-07-01 16:01:56 -0700 | [diff] [blame] | 120 | /* We only really need a clear color if we also have an auxiliary |
| 121 | * surface. Without one, it does nothing. |
| 122 | */ |
| 123 | info->clear_color = intel_miptree_get_isl_clear_color(brw, mt); |
Jason Ekstrand | 406c503 | 2016-07-22 14:41:43 -0700 | [diff] [blame] | 124 | |
| 125 | if (mt->mcs_mt) { |
| 126 | info->aux_bo = mt->mcs_mt->bo; |
| 127 | info->aux_offset = mt->mcs_mt->offset; |
| 128 | } else { |
| 129 | assert(info->aux_usage == ISL_AUX_USAGE_HIZ); |
| 130 | struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt; |
| 131 | if (hiz_mt) { |
| 132 | info->aux_bo = hiz_mt->bo; |
| 133 | if (brw->gen == 6 && |
| 134 | hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) { |
| 135 | /* gen6 requires the HiZ buffer to be manually offset to the |
| 136 | * right location. We could fixup the surf but it doesn't |
| 137 | * matter since most of those fields don't matter. |
| 138 | */ |
| 139 | apply_gen6_stencil_hiz_offset(&info->aux_surf, hiz_mt, level, |
| 140 | &info->aux_offset); |
| 141 | } else { |
| 142 | info->aux_offset = 0; |
| 143 | } |
| 144 | assert(hiz_mt->pitch == info->aux_surf.row_pitch); |
| 145 | } else { |
| 146 | info->aux_bo = mt->hiz_buf->bo; |
| 147 | info->aux_offset = 0; |
| 148 | } |
| 149 | } |
Jason Ekstrand | b82de88 | 2016-06-22 15:33:44 -0700 | [diff] [blame] | 150 | } else { |
Jason Ekstrand | 4d86b3f | 2016-07-01 16:01:56 -0700 | [diff] [blame] | 151 | info->aux_bo = NULL; |
| 152 | info->aux_offset = 0; |
| 153 | memset(&info->clear_color, 0, sizeof(info->clear_color)); |
Jason Ekstrand | b82de88 | 2016-06-22 15:33:44 -0700 | [diff] [blame] | 154 | } |
Jason Ekstrand | 406c503 | 2016-07-22 14:41:43 -0700 | [diff] [blame] | 155 | assert((info->aux_usage == ISL_AUX_USAGE_NONE) == (info->aux_bo == NULL)); |
Jason Ekstrand | b82de88 | 2016-06-22 15:33:44 -0700 | [diff] [blame] | 156 | |
Jason Ekstrand | 7997f4f | 2016-06-23 20:11:46 -0700 | [diff] [blame] | 157 | info->view = (struct isl_view) { |
| 158 | .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT : |
| 159 | ISL_SURF_USAGE_TEXTURE_BIT, |
| 160 | .format = ISL_FORMAT_UNSUPPORTED, /* Set later */ |
| 161 | .base_level = level, |
| 162 | .levels = 1, |
Jason Ekstrand | 7997f4f | 2016-06-23 20:11:46 -0700 | [diff] [blame] | 163 | .channel_select = { |
| 164 | ISL_CHANNEL_SELECT_RED, |
| 165 | ISL_CHANNEL_SELECT_GREEN, |
| 166 | ISL_CHANNEL_SELECT_BLUE, |
| 167 | ISL_CHANNEL_SELECT_ALPHA, |
| 168 | }, |
| 169 | }; |
| 170 | |
Jason Ekstrand | 96fa98c | 2016-06-27 11:54:14 -0700 | [diff] [blame] | 171 | if (!is_render_target && |
| 172 | (info->surf.dim == ISL_SURF_DIM_3D || |
| 173 | info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) { |
| 174 | /* 3-D textures don't support base_array layer and neither do 2-D |
| 175 | * multisampled textures on IVB so we need to pass it through the |
| 176 | * sampler in those cases. These are also two cases where we are |
| 177 | * guaranteed that we won't be doing any funny surface hacks. |
Jason Ekstrand | 9f9abc8 | 2016-06-28 14:46:07 -0700 | [diff] [blame] | 178 | */ |
Jason Ekstrand | 96fa98c | 2016-06-27 11:54:14 -0700 | [diff] [blame] | 179 | info->view.base_array_layer = 0; |
| 180 | info->view.array_len = MAX2(info->surf.logical_level0_px.depth, |
| 181 | info->surf.logical_level0_px.array_len); |
| 182 | info->z_offset = layer / layer_multiplier; |
Jason Ekstrand | 9f9abc8 | 2016-06-28 14:46:07 -0700 | [diff] [blame] | 183 | } else { |
Jason Ekstrand | 96fa98c | 2016-06-27 11:54:14 -0700 | [diff] [blame] | 184 | info->view.base_array_layer = layer / layer_multiplier; |
| 185 | info->view.array_len = 1; |
Jason Ekstrand | 9f9abc8 | 2016-06-28 14:46:07 -0700 | [diff] [blame] | 186 | info->z_offset = 0; |
| 187 | } |
| 188 | |
Jason Ekstrand | 7599886 | 2014-09-03 13:53:33 -0700 | [diff] [blame] | 189 | if (format == MESA_FORMAT_NONE) |
| 190 | format = mt->format; |
| 191 | |
| 192 | switch (format) { |
Mark Mueller | 50a01d2 | 2014-01-20 19:08:54 -0800 | [diff] [blame] | 193 | case MESA_FORMAT_S_UINT8: |
Jason Ekstrand | aa4117a | 2016-06-22 16:46:20 -0700 | [diff] [blame] | 194 | assert(info->surf.tiling == ISL_TILING_W); |
| 195 | /* Prior to Broadwell, we can't render to R8_UINT */ |
Jason Ekstrand | 7997f4f | 2016-06-23 20:11:46 -0700 | [diff] [blame] | 196 | info->view.format = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT : |
| 197 | BRW_SURFACEFORMAT_R8_UNORM; |
Paul Berry | 530bda2 | 2012-06-06 11:05:02 -0700 | [diff] [blame] | 198 | break; |
Kenneth Graunke | a487ef8 | 2014-02-07 21:53:18 -0800 | [diff] [blame] | 199 | case MESA_FORMAT_Z24_UNORM_X8_UINT: |
Kenneth Graunke | 0589eae | 2013-10-07 11:27:22 -0700 | [diff] [blame] | 200 | /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS |
| 201 | * here, but unfortunately it isn't supported as a render target, which |
| 202 | * would prevent us from blitting to 24-bit depth. |
| 203 | * |
| 204 | * The miptree consists of 32 bits per pixel, arranged as 24-bit depth |
Kenneth Graunke | 590d717 | 2013-10-07 11:19:11 -0700 | [diff] [blame] | 205 | * values interleaved with 8 "don't care" bits. Since depth values don't |
| 206 | * require any blending, it doesn't matter how we interpret the bit |
| 207 | * pattern as long as we copy the right amount of data, so just map it |
| 208 | * as 8-bit BGRA. |
Paul Berry | 530bda2 | 2012-06-06 11:05:02 -0700 | [diff] [blame] | 209 | */ |
Jason Ekstrand | 7997f4f | 2016-06-23 20:11:46 -0700 | [diff] [blame] | 210 | info->view.format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; |
Paul Berry | 530bda2 | 2012-06-06 11:05:02 -0700 | [diff] [blame] | 211 | break; |
Mark Mueller | 50a01d2 | 2014-01-20 19:08:54 -0800 | [diff] [blame] | 212 | case MESA_FORMAT_Z_FLOAT32: |
Jason Ekstrand | 7997f4f | 2016-06-23 20:11:46 -0700 | [diff] [blame] | 213 | info->view.format = BRW_SURFACEFORMAT_R32_FLOAT; |
Kenneth Graunke | 590d717 | 2013-10-07 11:19:11 -0700 | [diff] [blame] | 214 | break; |
Mark Mueller | 50a01d2 | 2014-01-20 19:08:54 -0800 | [diff] [blame] | 215 | case MESA_FORMAT_Z_UNORM16: |
Jason Ekstrand | 7997f4f | 2016-06-23 20:11:46 -0700 | [diff] [blame] | 216 | info->view.format = BRW_SURFACEFORMAT_R16_UNORM; |
Paul Berry | 530bda2 | 2012-06-06 11:05:02 -0700 | [diff] [blame] | 217 | break; |
Kenneth Graunke | 72aade4 | 2013-10-07 12:44:01 -0700 | [diff] [blame] | 218 | default: { |
Kenneth Graunke | 6f7c41d | 2013-09-30 18:11:03 -0700 | [diff] [blame] | 219 | if (is_render_target) { |
Kenneth Graunke | 8679bb7 | 2016-03-16 20:15:52 -0700 | [diff] [blame] | 220 | assert(brw->format_supported_as_render_target[format]); |
Jason Ekstrand | 7997f4f | 2016-06-23 20:11:46 -0700 | [diff] [blame] | 221 | info->view.format = brw->render_target_format[format]; |
Kenneth Graunke | 6f7c41d | 2013-09-30 18:11:03 -0700 | [diff] [blame] | 222 | } else { |
Jason Ekstrand | 7997f4f | 2016-06-23 20:11:46 -0700 | [diff] [blame] | 223 | info->view.format = brw_format_for_mesa_format(format); |
Kenneth Graunke | 6f7c41d | 2013-09-30 18:11:03 -0700 | [diff] [blame] | 224 | } |
Paul Berry | 530bda2 | 2012-06-06 11:05:02 -0700 | [diff] [blame] | 225 | break; |
Paul Berry | 506d70b | 2012-04-29 22:44:25 -0700 | [diff] [blame] | 226 | } |
Kenneth Graunke | 72aade4 | 2013-10-07 12:44:01 -0700 | [diff] [blame] | 227 | } |
Paul Berry | 506d70b | 2012-04-29 22:44:25 -0700 | [diff] [blame] | 228 | } |
| 229 | |
Paul Berry | f04f219 | 2012-08-29 16:04:15 -0700 | [diff] [blame] | 230 | |
Jason Ekstrand | b3f08b5 | 2016-04-22 14:32:48 -0700 | [diff] [blame] | 231 | void |
| 232 | brw_blorp_params_init(struct brw_blorp_params *params) |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 233 | { |
Jason Ekstrand | b3f08b5 | 2016-04-22 14:32:48 -0700 | [diff] [blame] | 234 | memset(params, 0, sizeof(*params)); |
| 235 | params->hiz_op = GEN6_HIZ_OP_NONE; |
| 236 | params->fast_clear_op = 0; |
Jason Ekstrand | b3f08b5 | 2016-04-22 14:32:48 -0700 | [diff] [blame] | 237 | params->num_draw_buffers = 1; |
| 238 | params->num_layers = 1; |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 239 | } |
| 240 | |
Jason Ekstrand | c1fe885 | 2016-04-27 17:16:30 -0700 | [diff] [blame] | 241 | void |
| 242 | brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key) |
| 243 | { |
| 244 | memset(wm_key, 0, sizeof(*wm_key)); |
| 245 | wm_key->nr_color_regions = 1; |
| 246 | for (int i = 0; i < MAX_SAMPLERS; i++) |
| 247 | wm_key->tex.swizzles[i] = SWIZZLE_XYZW; |
| 248 | } |
| 249 | |
| 250 | static int |
| 251 | nir_uniform_type_size(const struct glsl_type *type) |
| 252 | { |
| 253 | /* Only very basic types are allowed */ |
| 254 | assert(glsl_type_is_vector_or_scalar(type)); |
| 255 | assert(glsl_get_bit_size(type) == 32); |
| 256 | |
| 257 | return glsl_get_vector_elements(type) * 4; |
| 258 | } |
| 259 | |
| 260 | const unsigned * |
| 261 | brw_blorp_compile_nir_shader(struct brw_context *brw, struct nir_shader *nir, |
| 262 | const struct brw_wm_prog_key *wm_key, |
| 263 | bool use_repclear, |
| 264 | struct brw_blorp_prog_data *prog_data, |
| 265 | unsigned *program_size) |
| 266 | { |
| 267 | const struct brw_compiler *compiler = brw->intelScreen->compiler; |
| 268 | |
| 269 | void *mem_ctx = ralloc_context(NULL); |
| 270 | |
| 271 | /* Calling brw_preprocess_nir and friends is destructive and, if cloning is |
| 272 | * enabled, may end up completely replacing the nir_shader. Therefore, we |
| 273 | * own it and might as well put it in our context for easy cleanup. |
| 274 | */ |
| 275 | ralloc_steal(mem_ctx, nir); |
| 276 | nir->options = |
| 277 | compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions; |
| 278 | |
| 279 | struct brw_wm_prog_data wm_prog_data; |
| 280 | memset(&wm_prog_data, 0, sizeof(wm_prog_data)); |
| 281 | |
Topi Pohjolainen | 175e095 | 2016-05-18 22:01:17 +0300 | [diff] [blame] | 282 | wm_prog_data.base.nr_params = 0; |
| 283 | wm_prog_data.base.param = NULL; |
Jason Ekstrand | c1fe885 | 2016-04-27 17:16:30 -0700 | [diff] [blame] | 284 | |
| 285 | /* BLORP always just uses the first two binding table entries */ |
| 286 | wm_prog_data.binding_table.render_target_start = 0; |
| 287 | wm_prog_data.base.binding_table.texture_start = 1; |
| 288 | |
| 289 | nir = brw_preprocess_nir(compiler, nir); |
| 290 | nir_remove_dead_variables(nir, nir_var_shader_in); |
| 291 | nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)->impl); |
| 292 | |
| 293 | /* Uniforms are required to be lowered before going into compile_fs. For |
| 294 | * BLORP, we'll assume that whoever builds the shader sets the location |
| 295 | * they want so we just need to lower them and figure out how many we have |
| 296 | * in total. |
| 297 | */ |
| 298 | nir->num_uniforms = 0; |
| 299 | nir_foreach_variable(var, &nir->uniforms) { |
| 300 | var->data.driver_location = var->data.location; |
| 301 | unsigned end = var->data.location + nir_uniform_type_size(var->type); |
| 302 | nir->num_uniforms = MAX2(nir->num_uniforms, end); |
| 303 | } |
| 304 | nir_lower_io(nir, nir_var_uniform, nir_uniform_type_size); |
| 305 | |
| 306 | const unsigned *program = |
| 307 | brw_compile_fs(compiler, brw, mem_ctx, wm_key, &wm_prog_data, nir, |
Jason Ekstrand | 265487a | 2016-05-16 14:30:25 -0700 | [diff] [blame] | 308 | NULL, -1, -1, false, use_repclear, program_size, NULL); |
Jason Ekstrand | c1fe885 | 2016-04-27 17:16:30 -0700 | [diff] [blame] | 309 | |
| 310 | /* Copy the relavent bits of wm_prog_data over into the blorp prog data */ |
| 311 | prog_data->dispatch_8 = wm_prog_data.dispatch_8; |
| 312 | prog_data->dispatch_16 = wm_prog_data.dispatch_16; |
| 313 | prog_data->first_curbe_grf_0 = wm_prog_data.base.dispatch_grf_start_reg; |
| 314 | prog_data->first_curbe_grf_2 = wm_prog_data.dispatch_grf_start_reg_2; |
| 315 | prog_data->ksp_offset_2 = wm_prog_data.prog_offset_2; |
| 316 | prog_data->persample_msaa_dispatch = wm_prog_data.persample_dispatch; |
Topi Pohjolainen | f5e8575 | 2016-05-15 11:34:37 +0300 | [diff] [blame] | 317 | prog_data->flat_inputs = wm_prog_data.flat_inputs; |
| 318 | prog_data->num_varying_inputs = wm_prog_data.num_varying_inputs; |
Topi Pohjolainen | 9b2fa17 | 2016-06-01 12:27:56 +0300 | [diff] [blame] | 319 | prog_data->inputs_read = nir->info.inputs_read; |
Jason Ekstrand | c1fe885 | 2016-04-27 17:16:30 -0700 | [diff] [blame] | 320 | |
Topi Pohjolainen | 175e095 | 2016-05-18 22:01:17 +0300 | [diff] [blame] | 321 | assert(wm_prog_data.base.nr_params == 0); |
Jason Ekstrand | c1fe885 | 2016-04-27 17:16:30 -0700 | [diff] [blame] | 322 | |
| 323 | return program; |
| 324 | } |
| 325 | |
Jason Ekstrand | 6553dc0 | 2016-06-10 12:03:18 -0700 | [diff] [blame] | 326 | struct surface_state_info { |
| 327 | unsigned num_dwords; |
| 328 | unsigned ss_align; /* Required alignment of RENDER_SURFACE_STATE in bytes */ |
| 329 | unsigned reloc_dw; |
| 330 | unsigned aux_reloc_dw; |
| 331 | unsigned tex_mocs; |
| 332 | unsigned rb_mocs; |
| 333 | }; |
| 334 | |
| 335 | static const struct surface_state_info surface_state_infos[] = { |
| 336 | [6] = {6, 32, 1, 0}, |
| 337 | [7] = {8, 32, 1, 6, GEN7_MOCS_L3, GEN7_MOCS_L3}, |
| 338 | [8] = {13, 64, 8, 10, BDW_MOCS_WB, BDW_MOCS_PTE}, |
| 339 | [9] = {16, 64, 8, 10, SKL_MOCS_WB, SKL_MOCS_PTE}, |
| 340 | }; |
| 341 | |
| 342 | uint32_t |
| 343 | brw_blorp_emit_surface_state(struct brw_context *brw, |
| 344 | const struct brw_blorp_surface_info *surface, |
| 345 | uint32_t read_domains, uint32_t write_domain, |
| 346 | bool is_render_target) |
| 347 | { |
| 348 | const struct surface_state_info ss_info = surface_state_infos[brw->gen]; |
| 349 | |
Jason Ekstrand | b82de88 | 2016-06-22 15:33:44 -0700 | [diff] [blame] | 350 | struct isl_surf surf = surface->surf; |
Jason Ekstrand | 6553dc0 | 2016-06-10 12:03:18 -0700 | [diff] [blame] | 351 | |
Jason Ekstrand | 871893c | 2016-06-27 17:30:35 -0700 | [diff] [blame] | 352 | if (surf.dim == ISL_SURF_DIM_1D && |
| 353 | surf.dim_layout == ISL_DIM_LAYOUT_GEN4_2D) { |
| 354 | assert(surf.logical_level0_px.height == 1); |
| 355 | surf.dim = ISL_SURF_DIM_2D; |
| 356 | } |
| 357 | |
Jason Ekstrand | 4d86b3f | 2016-07-01 16:01:56 -0700 | [diff] [blame] | 358 | /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */ |
| 359 | enum isl_aux_usage aux_usage = surface->aux_usage; |
| 360 | if (aux_usage == ISL_AUX_USAGE_HIZ) |
| 361 | aux_usage = ISL_AUX_USAGE_NONE; |
Jason Ekstrand | 6553dc0 | 2016-06-10 12:03:18 -0700 | [diff] [blame] | 362 | |
Jason Ekstrand | 6553dc0 | 2016-06-10 12:03:18 -0700 | [diff] [blame] | 363 | uint32_t surf_offset; |
| 364 | uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, |
| 365 | ss_info.num_dwords * 4, ss_info.ss_align, |
| 366 | &surf_offset); |
| 367 | |
| 368 | const uint32_t mocs = is_render_target ? ss_info.rb_mocs : ss_info.tex_mocs; |
Jason Ekstrand | 4d86b3f | 2016-07-01 16:01:56 -0700 | [diff] [blame] | 369 | uint64_t aux_bo_offset = surface->aux_bo ? surface->aux_bo->offset64 : 0; |
Jason Ekstrand | 6553dc0 | 2016-06-10 12:03:18 -0700 | [diff] [blame] | 370 | |
Jason Ekstrand | 603d5f7 | 2016-06-27 09:05:46 -0700 | [diff] [blame] | 371 | isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = &surface->view, |
Jason Ekstrand | d540864 | 2016-07-22 14:24:06 -0700 | [diff] [blame] | 372 | .address = surface->bo->offset64 + surface->offset, |
Jason Ekstrand | 4d86b3f | 2016-07-01 16:01:56 -0700 | [diff] [blame] | 373 | .aux_surf = &surface->aux_surf, .aux_usage = aux_usage, |
| 374 | .aux_address = aux_bo_offset + surface->aux_offset, |
| 375 | .mocs = mocs, .clear_color = surface->clear_color, |
Jason Ekstrand | e046a46 | 2016-06-23 18:40:08 -0700 | [diff] [blame] | 376 | .x_offset_sa = surface->tile_x_sa, |
| 377 | .y_offset_sa = surface->tile_y_sa); |
Jason Ekstrand | 6553dc0 | 2016-06-10 12:03:18 -0700 | [diff] [blame] | 378 | |
| 379 | /* Emit relocation to surface contents */ |
| 380 | drm_intel_bo_emit_reloc(brw->batch.bo, |
| 381 | surf_offset + ss_info.reloc_dw * 4, |
Jason Ekstrand | d540864 | 2016-07-22 14:24:06 -0700 | [diff] [blame] | 382 | surface->bo, |
| 383 | dw[ss_info.reloc_dw] - surface->bo->offset64, |
Jason Ekstrand | 6553dc0 | 2016-06-10 12:03:18 -0700 | [diff] [blame] | 384 | read_domains, write_domain); |
| 385 | |
Jason Ekstrand | 4d86b3f | 2016-07-01 16:01:56 -0700 | [diff] [blame] | 386 | if (aux_usage != ISL_AUX_USAGE_NONE) { |
Jason Ekstrand | 6553dc0 | 2016-06-10 12:03:18 -0700 | [diff] [blame] | 387 | /* On gen7 and prior, the bottom 12 bits of the MCS base address are |
| 388 | * used to store other information. This should be ok, however, because |
| 389 | * surface buffer addresses are always 4K page alinged. |
| 390 | */ |
Jason Ekstrand | 4d86b3f | 2016-07-01 16:01:56 -0700 | [diff] [blame] | 391 | assert((surface->aux_offset & 0xfff) == 0); |
Jason Ekstrand | 6553dc0 | 2016-06-10 12:03:18 -0700 | [diff] [blame] | 392 | drm_intel_bo_emit_reloc(brw->batch.bo, |
| 393 | surf_offset + ss_info.aux_reloc_dw * 4, |
Jason Ekstrand | 4d86b3f | 2016-07-01 16:01:56 -0700 | [diff] [blame] | 394 | surface->aux_bo, |
Jason Ekstrand | 6553dc0 | 2016-06-10 12:03:18 -0700 | [diff] [blame] | 395 | dw[ss_info.aux_reloc_dw] & 0xfff, |
| 396 | read_domains, write_domain); |
| 397 | } |
| 398 | |
| 399 | return surf_offset; |
| 400 | } |
| 401 | |
Jason Ekstrand | 8096ed7 | 2016-04-22 13:46:25 -0700 | [diff] [blame] | 402 | /** |
| 403 | * Perform a HiZ or depth resolve operation. |
| 404 | * |
| 405 | * For an overview of HiZ ops, see the following sections of the Sandy Bridge |
| 406 | * PRM, Volume 1, Part 2: |
| 407 | * - 7.5.3.1 Depth Buffer Clear |
| 408 | * - 7.5.3.2 Depth Buffer Resolve |
| 409 | * - 7.5.3.3 Hierarchical Depth Buffer Resolve |
| 410 | */ |
Eric Anholt | 5b226ad | 2012-05-21 09:30:35 -0700 | [diff] [blame] | 411 | void |
Kenneth Graunke | ca43757 | 2013-07-02 23:17:14 -0700 | [diff] [blame] | 412 | intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, |
Jason Ekstrand | bed7429 | 2016-04-22 16:04:05 -0700 | [diff] [blame] | 413 | unsigned int level, unsigned int layer, enum gen6_hiz_op op) |
Eric Anholt | 5b226ad | 2012-05-21 09:30:35 -0700 | [diff] [blame] | 414 | { |
Eric Anholt | a2ca98b | 2013-05-30 14:53:55 -0700 | [diff] [blame] | 415 | const char *opname = NULL; |
| 416 | |
| 417 | switch (op) { |
| 418 | case GEN6_HIZ_OP_DEPTH_RESOLVE: |
| 419 | opname = "depth resolve"; |
| 420 | break; |
| 421 | case GEN6_HIZ_OP_HIZ_RESOLVE: |
| 422 | opname = "hiz ambiguate"; |
| 423 | break; |
| 424 | case GEN6_HIZ_OP_DEPTH_CLEAR: |
| 425 | opname = "depth clear"; |
| 426 | break; |
| 427 | case GEN6_HIZ_OP_NONE: |
| 428 | opname = "noop?"; |
| 429 | break; |
| 430 | } |
| 431 | |
| 432 | DBG("%s %s to mt %p level %d layer %d\n", |
Marius Predut | 28d9e90 | 2015-04-07 22:05:28 +0300 | [diff] [blame] | 433 | __func__, opname, mt, level, layer); |
Eric Anholt | a2ca98b | 2013-05-30 14:53:55 -0700 | [diff] [blame] | 434 | |
Kenneth Graunke | 8cad1c1 | 2014-02-06 17:06:12 -0800 | [diff] [blame] | 435 | if (brw->gen >= 8) { |
| 436 | gen8_hiz_exec(brw, mt, level, layer, op); |
| 437 | } else { |
Jason Ekstrand | 8096ed7 | 2016-04-22 13:46:25 -0700 | [diff] [blame] | 438 | gen6_blorp_hiz_exec(brw, mt, level, layer, op); |
Kenneth Graunke | 8cad1c1 | 2014-02-06 17:06:12 -0800 | [diff] [blame] | 439 | } |
Eric Anholt | 5b226ad | 2012-05-21 09:30:35 -0700 | [diff] [blame] | 440 | } |
| 441 | |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 442 | void |
Jason Ekstrand | b3f08b5 | 2016-04-22 14:32:48 -0700 | [diff] [blame] | 443 | brw_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params) |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 444 | { |
Eric Anholt | 185b5a5 | 2013-06-18 13:52:03 -0700 | [diff] [blame] | 445 | struct gl_context *ctx = &brw->ctx; |
Topi Pohjolainen | 7de72f7 | 2016-03-30 20:41:30 +0300 | [diff] [blame] | 446 | const uint32_t estimated_max_batch_usage = brw->gen >= 8 ? 1800 : 1500; |
Eric Anholt | 185b5a5 | 2013-06-18 13:52:03 -0700 | [diff] [blame] | 447 | bool check_aperture_failed_once = false; |
| 448 | |
| 449 | /* Flush the sampler and render caches. We definitely need to flush the |
| 450 | * sampler cache so that we get updated contents from the render cache for |
| 451 | * the glBlitFramebuffer() source. Also, we are sometimes warned in the |
| 452 | * docs to flush the cache between reinterpretations of the same surface |
| 453 | * data with different formats, which blorp does for stencil and depth |
| 454 | * data. |
| 455 | */ |
Chris Wilson | 4b35ab9 | 2015-04-30 17:04:51 +0100 | [diff] [blame] | 456 | brw_emit_mi_flush(brw); |
Eric Anholt | 185b5a5 | 2013-06-18 13:52:03 -0700 | [diff] [blame] | 457 | |
Topi Pohjolainen | 7644e8a | 2016-04-15 10:43:05 +0300 | [diff] [blame] | 458 | brw_select_pipeline(brw, BRW_RENDER_PIPELINE); |
| 459 | |
Eric Anholt | 185b5a5 | 2013-06-18 13:52:03 -0700 | [diff] [blame] | 460 | retry: |
Kenneth Graunke | 6bc40f9 | 2013-10-28 16:06:10 -0700 | [diff] [blame] | 461 | intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING); |
Eric Anholt | 185b5a5 | 2013-06-18 13:52:03 -0700 | [diff] [blame] | 462 | intel_batchbuffer_save_state(brw); |
| 463 | drm_intel_bo *saved_bo = brw->batch.bo; |
Matt Turner | 131573d | 2015-07-11 14:36:25 -0700 | [diff] [blame] | 464 | uint32_t saved_used = USED_BATCH(brw->batch); |
Eric Anholt | 185b5a5 | 2013-06-18 13:52:03 -0700 | [diff] [blame] | 465 | uint32_t saved_state_batch_offset = brw->batch.state_batch_offset; |
| 466 | |
Kenneth Graunke | 53631be | 2013-07-06 00:36:46 -0700 | [diff] [blame] | 467 | switch (brw->gen) { |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 468 | case 6: |
Kenneth Graunke | ca43757 | 2013-07-02 23:17:14 -0700 | [diff] [blame] | 469 | gen6_blorp_exec(brw, params); |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 470 | break; |
| 471 | case 7: |
Kenneth Graunke | ca43757 | 2013-07-02 23:17:14 -0700 | [diff] [blame] | 472 | gen7_blorp_exec(brw, params); |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 473 | break; |
Topi Pohjolainen | 7de72f7 | 2016-03-30 20:41:30 +0300 | [diff] [blame] | 474 | case 8: |
| 475 | case 9: |
| 476 | gen8_blorp_exec(brw, params); |
| 477 | break; |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 478 | default: |
| 479 | /* BLORP is not supported before Gen6. */ |
Matt Turner | 3d82672 | 2014-06-29 14:54:01 -0700 | [diff] [blame] | 480 | unreachable("not reached"); |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 481 | } |
Eric Anholt | db31bc5 | 2013-02-07 18:46:18 -0800 | [diff] [blame] | 482 | |
Eric Anholt | 185b5a5 | 2013-06-18 13:52:03 -0700 | [diff] [blame] | 483 | /* Make sure we didn't wrap the batch unintentionally, and make sure we |
| 484 | * reserved enough space that a wrap will never happen. |
| 485 | */ |
| 486 | assert(brw->batch.bo == saved_bo); |
Matt Turner | 131573d | 2015-07-11 14:36:25 -0700 | [diff] [blame] | 487 | assert((USED_BATCH(brw->batch) - saved_used) * 4 + |
Eric Anholt | 185b5a5 | 2013-06-18 13:52:03 -0700 | [diff] [blame] | 488 | (saved_state_batch_offset - brw->batch.state_batch_offset) < |
| 489 | estimated_max_batch_usage); |
| 490 | /* Shut up compiler warnings on release build */ |
| 491 | (void)saved_bo; |
| 492 | (void)saved_used; |
| 493 | (void)saved_state_batch_offset; |
| 494 | |
| 495 | /* Check if the blorp op we just did would make our batch likely to fail to |
| 496 | * map all the BOs into the GPU at batch exec time later. If so, flush the |
| 497 | * batch and try again with nothing else in the batch. |
| 498 | */ |
| 499 | if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) { |
| 500 | if (!check_aperture_failed_once) { |
| 501 | check_aperture_failed_once = true; |
| 502 | intel_batchbuffer_reset_to_saved(brw); |
| 503 | intel_batchbuffer_flush(brw); |
| 504 | goto retry; |
| 505 | } else { |
| 506 | int ret = intel_batchbuffer_flush(brw); |
| 507 | WARN_ONCE(ret == -ENOSPC, |
| 508 | "i965: blorp emit exceeded available aperture space\n"); |
| 509 | } |
| 510 | } |
| 511 | |
Kenneth Graunke | e334390 | 2013-07-03 13:54:53 -0700 | [diff] [blame] | 512 | if (unlikely(brw->always_flush_batch)) |
Kenneth Graunke | ca43757 | 2013-07-02 23:17:14 -0700 | [diff] [blame] | 513 | intel_batchbuffer_flush(brw); |
Eric Anholt | db31bc5 | 2013-02-07 18:46:18 -0800 | [diff] [blame] | 514 | |
| 515 | /* We've smashed all state compared to what the normal 3D pipeline |
| 516 | * rendering tracks for GL. |
| 517 | */ |
Topi Pohjolainen | 234b5f2 | 2016-04-22 13:43:39 +0300 | [diff] [blame] | 518 | brw->ctx.NewDriverState |= BRW_NEW_BLORP; |
Eric Anholt | 3f9440c | 2014-04-06 10:49:49 -0700 | [diff] [blame] | 519 | brw->no_depth_or_stencil = false; |
Eric Anholt | 2e2445f | 2013-06-18 14:54:18 -0700 | [diff] [blame] | 520 | brw->ib.type = -1; |
Eric Anholt | db31bc5 | 2013-02-07 18:46:18 -0800 | [diff] [blame] | 521 | |
| 522 | /* Flush the sampler cache so any texturing from the destination is |
| 523 | * coherent. |
| 524 | */ |
Chris Wilson | 4b35ab9 | 2015-04-30 17:04:51 +0100 | [diff] [blame] | 525 | brw_emit_mi_flush(brw); |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 526 | } |
| 527 | |
Jason Ekstrand | 8096ed7 | 2016-04-22 13:46:25 -0700 | [diff] [blame] | 528 | void |
| 529 | gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, |
| 530 | unsigned int level, unsigned int layer, enum gen6_hiz_op op) |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 531 | { |
Jason Ekstrand | b3f08b5 | 2016-04-22 14:32:48 -0700 | [diff] [blame] | 532 | struct brw_blorp_params params; |
| 533 | brw_blorp_params_init(¶ms); |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 534 | |
Jason Ekstrand | 8096ed7 | 2016-04-22 13:46:25 -0700 | [diff] [blame] | 535 | params.hiz_op = op; |
| 536 | |
Jason Ekstrand | b6dd8e4 | 2016-04-21 16:39:56 -0700 | [diff] [blame] | 537 | brw_blorp_surface_info_init(brw, ¶ms.depth, mt, level, layer, |
| 538 | mt->format, true); |
Chad Versace | a14dc4f | 2013-03-11 19:21:46 -0700 | [diff] [blame] | 539 | |
| 540 | /* Align the rectangle primitive to 8x4 pixels. |
| 541 | * |
| 542 | * During fast depth clears, the emitted rectangle primitive must be |
| 543 | * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section |
| 544 | * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge |
| 545 | * PRM): |
| 546 | * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be |
| 547 | * aligned to an 8x4 pixel block relative to the upper left corner |
| 548 | * of the depth buffer [...] |
| 549 | * |
| 550 | * For hiz resolves, the rectangle must also be 8x4 aligned. Item |
| 551 | * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the |
| 552 | * Ivybridge simulator require the alignment. |
| 553 | * |
| 554 | * To be safe, let's just align the rect for all hiz operations and all |
| 555 | * hardware generations. |
| 556 | * |
| 557 | * However, for some miptree slices of a Z24 texture, emitting an 8x4 |
| 558 | * aligned rectangle that covers the slice may clobber adjacent slices if |
| 559 | * we strictly adhered to the texture alignments specified in the PRM. The |
| 560 | * Ivybridge PRM, Section "Alignment Unit Size", states that |
| 561 | * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces, |
| 562 | * not 8. But commit 1f112cc increased the alignment from 4 to 8, which |
| 563 | * prevents the clobbering. |
| 564 | */ |
Jason Ekstrand | 7abcdfb | 2016-06-27 19:30:32 -0700 | [diff] [blame] | 565 | params.x1 = minify(params.depth.surf.logical_level0_px.width, |
| 566 | params.depth.view.base_level); |
| 567 | params.y1 = minify(params.depth.surf.logical_level0_px.height, |
| 568 | params.depth.view.base_level); |
| 569 | params.x1 = ALIGN(params.x1, 8); |
| 570 | params.y1 = ALIGN(params.y1, 4); |
Chad Versace | a14dc4f | 2013-03-11 19:21:46 -0700 | [diff] [blame] | 571 | |
Jason Ekstrand | 7abcdfb | 2016-06-27 19:30:32 -0700 | [diff] [blame] | 572 | if (params.depth.view.base_level == 0) { |
| 573 | /* TODO: What about MSAA? */ |
| 574 | params.depth.surf.logical_level0_px.width = params.x1; |
| 575 | params.depth.surf.logical_level0_px.height = params.y1; |
| 576 | } |
| 577 | |
| 578 | params.dst.surf.samples = params.depth.surf.samples; |
| 579 | params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px; |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 580 | |
Eric Anholt | 11bef60 | 2014-04-23 14:21:21 -0700 | [diff] [blame] | 581 | assert(intel_miptree_level_has_hiz(mt, level)); |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 582 | |
| 583 | switch (mt->format) { |
Jason Ekstrand | 8096ed7 | 2016-04-22 13:46:25 -0700 | [diff] [blame] | 584 | case MESA_FORMAT_Z_UNORM16: |
| 585 | params.depth_format = BRW_DEPTHFORMAT_D16_UNORM; |
| 586 | break; |
| 587 | case MESA_FORMAT_Z_FLOAT32: |
| 588 | params.depth_format = BRW_DEPTHFORMAT_D32_FLOAT; |
| 589 | break; |
| 590 | case MESA_FORMAT_Z24_UNORM_X8_UINT: |
| 591 | params.depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; |
| 592 | break; |
| 593 | default: |
| 594 | unreachable("not reached"); |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 595 | } |
Jason Ekstrand | 8096ed7 | 2016-04-22 13:46:25 -0700 | [diff] [blame] | 596 | |
| 597 | brw_blorp_exec(brw, ¶ms); |
Paul Berry | 2c5510b | 2012-04-29 22:00:46 -0700 | [diff] [blame] | 598 | } |