Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * © Copyright 2017-2018 Alyssa Rosenzweig |
| 3 | * © Copyright 2017-2018 Connor Abbott |
| 4 | * © Copyright 2017-2018 Lyude Paul |
Alyssa Rosenzweig | d4575c3 | 2019-06-25 13:30:17 -0700 | [diff] [blame] | 5 | * © Copyright2019 Collabora, Ltd. |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the "Software"), |
| 9 | * to deal in the Software without restriction, including without limitation |
| 10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 11 | * and/or sell copies of the Software, and to permit persons to whom the |
| 12 | * Software is furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice (including the next |
| 15 | * paragraph) shall be included in all copies or substantial portions of the |
| 16 | * Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 24 | * SOFTWARE. |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #ifndef __PANFROST_JOB_H__ |
| 29 | #define __PANFROST_JOB_H__ |
| 30 | |
| 31 | #include <stdint.h> |
Icecream95 | f2f1277 | 2020-01-09 15:13:58 +1300 | [diff] [blame^] | 32 | #include <stdbool.h> |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 33 | #include <panfrost-misc.h> |
| 34 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 35 | enum mali_job_type { |
| 36 | JOB_NOT_STARTED = 0, |
| 37 | JOB_TYPE_NULL = 1, |
Alyssa Rosenzweig | adf716d | 2019-12-05 09:06:53 -0500 | [diff] [blame] | 38 | JOB_TYPE_WRITE_VALUE = 2, |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 39 | JOB_TYPE_CACHE_FLUSH = 3, |
| 40 | JOB_TYPE_COMPUTE = 4, |
| 41 | JOB_TYPE_VERTEX = 5, |
| 42 | JOB_TYPE_GEOMETRY = 6, |
| 43 | JOB_TYPE_TILER = 7, |
| 44 | JOB_TYPE_FUSED = 8, |
| 45 | JOB_TYPE_FRAGMENT = 9, |
| 46 | }; |
| 47 | |
| 48 | enum mali_draw_mode { |
| 49 | MALI_DRAW_NONE = 0x0, |
| 50 | MALI_POINTS = 0x1, |
| 51 | MALI_LINES = 0x2, |
| 52 | MALI_LINE_STRIP = 0x4, |
| 53 | MALI_LINE_LOOP = 0x6, |
| 54 | MALI_TRIANGLES = 0x8, |
| 55 | MALI_TRIANGLE_STRIP = 0xA, |
| 56 | MALI_TRIANGLE_FAN = 0xC, |
| 57 | MALI_POLYGON = 0xD, |
| 58 | MALI_QUADS = 0xE, |
| 59 | MALI_QUAD_STRIP = 0xF, |
| 60 | |
| 61 | /* All other modes invalid */ |
| 62 | }; |
| 63 | |
| 64 | /* Applies to tiler_gl_enables */ |
| 65 | |
Alyssa Rosenzweig | 2d22b53 | 2019-02-14 02:44:03 +0000 | [diff] [blame] | 66 | #define MALI_OCCLUSION_QUERY (1 << 3) |
| 67 | #define MALI_OCCLUSION_PRECISE (1 << 4) |
| 68 | |
Alyssa Rosenzweig | 2adf35e | 2019-05-23 03:01:32 +0000 | [diff] [blame] | 69 | /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium). |
| 70 | * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob |
| 71 | * disagree about how to do viewport flipping, so the blob actually sets this |
| 72 | * for GL_CW but then has a negative viewport stride */ |
Alyssa Rosenzweig | 44971b8 | 2019-10-27 19:46:50 -0400 | [diff] [blame] | 73 | |
Alyssa Rosenzweig | 2adf35e | 2019-05-23 03:01:32 +0000 | [diff] [blame] | 74 | #define MALI_FRONT_CCW_TOP (1 << 5) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 75 | |
Alyssa Rosenzweig | 2d22b53 | 2019-02-14 02:44:03 +0000 | [diff] [blame] | 76 | #define MALI_CULL_FACE_FRONT (1 << 6) |
| 77 | #define MALI_CULL_FACE_BACK (1 << 7) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 78 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 79 | /* Used in stencil and depth tests */ |
| 80 | |
| 81 | enum mali_func { |
| 82 | MALI_FUNC_NEVER = 0, |
| 83 | MALI_FUNC_LESS = 1, |
| 84 | MALI_FUNC_EQUAL = 2, |
| 85 | MALI_FUNC_LEQUAL = 3, |
| 86 | MALI_FUNC_GREATER = 4, |
| 87 | MALI_FUNC_NOTEQUAL = 5, |
| 88 | MALI_FUNC_GEQUAL = 6, |
| 89 | MALI_FUNC_ALWAYS = 7 |
| 90 | }; |
| 91 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 92 | /* Flags apply to unknown2_3? */ |
| 93 | |
| 94 | #define MALI_HAS_MSAA (1 << 0) |
| 95 | #define MALI_CAN_DISCARD (1 << 5) |
| 96 | |
Alyssa Rosenzweig | 97aa054 | 2019-02-10 20:06:21 +0000 | [diff] [blame] | 97 | /* Applies on SFBD systems, specifying that programmable blending is in use */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 98 | #define MALI_HAS_BLEND_SHADER (1 << 6) |
| 99 | |
| 100 | /* func is mali_func */ |
| 101 | #define MALI_DEPTH_FUNC(func) (func << 8) |
| 102 | #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7) |
| 103 | #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7) |
| 104 | |
Boris Brezillon | 2844082 | 2019-11-04 11:57:22 +0100 | [diff] [blame] | 105 | #define MALI_DEPTH_WRITEMASK (1 << 11) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 106 | |
| 107 | /* Next flags to unknown2_4 */ |
| 108 | #define MALI_STENCIL_TEST (1 << 0) |
| 109 | |
| 110 | /* What?! */ |
| 111 | #define MALI_SAMPLE_ALPHA_TO_COVERAGE_NO_BLEND_SHADER (1 << 1) |
| 112 | |
| 113 | #define MALI_NO_DITHER (1 << 9) |
| 114 | #define MALI_DEPTH_RANGE_A (1 << 12) |
| 115 | #define MALI_DEPTH_RANGE_B (1 << 13) |
| 116 | #define MALI_NO_MSAA (1 << 14) |
| 117 | |
| 118 | /* Stencil test state is all encoded in a single u32, just with a lot of |
| 119 | * enums... */ |
| 120 | |
| 121 | enum mali_stencil_op { |
| 122 | MALI_STENCIL_KEEP = 0, |
| 123 | MALI_STENCIL_REPLACE = 1, |
| 124 | MALI_STENCIL_ZERO = 2, |
| 125 | MALI_STENCIL_INVERT = 3, |
| 126 | MALI_STENCIL_INCR_WRAP = 4, |
| 127 | MALI_STENCIL_DECR_WRAP = 5, |
| 128 | MALI_STENCIL_INCR = 6, |
| 129 | MALI_STENCIL_DECR = 7 |
| 130 | }; |
| 131 | |
| 132 | struct mali_stencil_test { |
| 133 | unsigned ref : 8; |
| 134 | unsigned mask : 8; |
| 135 | enum mali_func func : 3; |
| 136 | enum mali_stencil_op sfail : 3; |
| 137 | enum mali_stencil_op dpfail : 3; |
| 138 | enum mali_stencil_op dppass : 3; |
| 139 | unsigned zero : 4; |
| 140 | } __attribute__((packed)); |
| 141 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 142 | #define MALI_MASK_R (1 << 0) |
| 143 | #define MALI_MASK_G (1 << 1) |
| 144 | #define MALI_MASK_B (1 << 2) |
| 145 | #define MALI_MASK_A (1 << 3) |
| 146 | |
| 147 | enum mali_nondominant_mode { |
| 148 | MALI_BLEND_NON_MIRROR = 0, |
| 149 | MALI_BLEND_NON_ZERO = 1 |
| 150 | }; |
| 151 | |
| 152 | enum mali_dominant_blend { |
| 153 | MALI_BLEND_DOM_SOURCE = 0, |
| 154 | MALI_BLEND_DOM_DESTINATION = 1 |
| 155 | }; |
| 156 | |
| 157 | enum mali_dominant_factor { |
| 158 | MALI_DOMINANT_UNK0 = 0, |
| 159 | MALI_DOMINANT_ZERO = 1, |
| 160 | MALI_DOMINANT_SRC_COLOR = 2, |
| 161 | MALI_DOMINANT_DST_COLOR = 3, |
| 162 | MALI_DOMINANT_UNK4 = 4, |
| 163 | MALI_DOMINANT_SRC_ALPHA = 5, |
| 164 | MALI_DOMINANT_DST_ALPHA = 6, |
| 165 | MALI_DOMINANT_CONSTANT = 7, |
| 166 | }; |
| 167 | |
| 168 | enum mali_blend_modifier { |
| 169 | MALI_BLEND_MOD_UNK0 = 0, |
| 170 | MALI_BLEND_MOD_NORMAL = 1, |
| 171 | MALI_BLEND_MOD_SOURCE_ONE = 2, |
| 172 | MALI_BLEND_MOD_DEST_ONE = 3, |
| 173 | }; |
| 174 | |
| 175 | struct mali_blend_mode { |
| 176 | enum mali_blend_modifier clip_modifier : 2; |
| 177 | unsigned unused_0 : 1; |
| 178 | unsigned negate_source : 1; |
| 179 | |
| 180 | enum mali_dominant_blend dominant : 1; |
| 181 | |
| 182 | enum mali_nondominant_mode nondominant_mode : 1; |
| 183 | |
| 184 | unsigned unused_1 : 1; |
| 185 | |
| 186 | unsigned negate_dest : 1; |
| 187 | |
| 188 | enum mali_dominant_factor dominant_factor : 3; |
| 189 | unsigned complement_dominant : 1; |
| 190 | } __attribute__((packed)); |
| 191 | |
| 192 | struct mali_blend_equation { |
| 193 | /* Of type mali_blend_mode */ |
| 194 | unsigned rgb_mode : 12; |
| 195 | unsigned alpha_mode : 12; |
| 196 | |
| 197 | unsigned zero1 : 4; |
| 198 | |
| 199 | /* Corresponds to MALI_MASK_* above and glColorMask arguments */ |
| 200 | |
| 201 | unsigned color_mask : 4; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 202 | } __attribute__((packed)); |
| 203 | |
| 204 | /* Used with channel swizzling */ |
| 205 | enum mali_channel { |
| 206 | MALI_CHANNEL_RED = 0, |
| 207 | MALI_CHANNEL_GREEN = 1, |
| 208 | MALI_CHANNEL_BLUE = 2, |
| 209 | MALI_CHANNEL_ALPHA = 3, |
| 210 | MALI_CHANNEL_ZERO = 4, |
| 211 | MALI_CHANNEL_ONE = 5, |
| 212 | MALI_CHANNEL_RESERVED_0 = 6, |
| 213 | MALI_CHANNEL_RESERVED_1 = 7, |
| 214 | }; |
| 215 | |
| 216 | struct mali_channel_swizzle { |
| 217 | enum mali_channel r : 3; |
| 218 | enum mali_channel g : 3; |
| 219 | enum mali_channel b : 3; |
| 220 | enum mali_channel a : 3; |
| 221 | } __attribute__((packed)); |
| 222 | |
| 223 | /* Compressed per-pixel formats. Each of these formats expands to one to four |
| 224 | * floating-point or integer numbers, as defined by the OpenGL specification. |
| 225 | * There are various places in OpenGL where the user can specify a compressed |
| 226 | * format in memory, which all use the same 8-bit enum in the various |
| 227 | * descriptors, although different hardware units support different formats. |
| 228 | */ |
| 229 | |
| 230 | /* The top 3 bits specify how the bits of each component are interpreted. */ |
| 231 | |
| 232 | /* e.g. R11F_G11F_B10F */ |
| 233 | #define MALI_FORMAT_SPECIAL (2 << 5) |
| 234 | |
| 235 | /* signed normalized, e.g. RGBA8_SNORM */ |
| 236 | #define MALI_FORMAT_SNORM (3 << 5) |
| 237 | |
| 238 | /* e.g. RGBA8UI */ |
| 239 | #define MALI_FORMAT_UINT (4 << 5) |
| 240 | |
| 241 | /* e.g. RGBA8 and RGBA32F */ |
| 242 | #define MALI_FORMAT_UNORM (5 << 5) |
| 243 | |
| 244 | /* e.g. RGBA8I and RGBA16F */ |
| 245 | #define MALI_FORMAT_SINT (6 << 5) |
| 246 | |
| 247 | /* These formats seem to largely duplicate the others. They're used at least |
| 248 | * for Bifrost framebuffer output. |
| 249 | */ |
| 250 | #define MALI_FORMAT_SPECIAL2 (7 << 5) |
| 251 | |
| 252 | /* If the high 3 bits are 3 to 6 these two bits say how many components |
| 253 | * there are. |
| 254 | */ |
| 255 | #define MALI_NR_CHANNELS(n) ((n - 1) << 3) |
| 256 | |
| 257 | /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each |
| 258 | * component is, except the special MALI_CHANNEL_FLOAT which overrides what the |
| 259 | * bits mean. |
| 260 | */ |
| 261 | |
Alyssa Rosenzweig | 60270c8 | 2019-02-24 06:28:39 +0000 | [diff] [blame] | 262 | #define MALI_CHANNEL_4 2 |
| 263 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 264 | #define MALI_CHANNEL_8 3 |
| 265 | |
| 266 | #define MALI_CHANNEL_16 4 |
| 267 | |
| 268 | #define MALI_CHANNEL_32 5 |
| 269 | |
| 270 | /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For |
| 271 | * MALI_FORMAT_UNORM, it means a 32-bit float. |
| 272 | */ |
| 273 | #define MALI_CHANNEL_FLOAT 7 |
| 274 | |
| 275 | enum mali_format { |
Alyssa Rosenzweig | 90fd82c | 2019-02-24 05:43:14 +0000 | [diff] [blame] | 276 | MALI_RGB565 = MALI_FORMAT_SPECIAL | 0x0, |
| 277 | MALI_RGB5_A1_UNORM = MALI_FORMAT_SPECIAL | 0x2, |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 278 | MALI_RGB10_A2_UNORM = MALI_FORMAT_SPECIAL | 0x3, |
| 279 | MALI_RGB10_A2_SNORM = MALI_FORMAT_SPECIAL | 0x5, |
| 280 | MALI_RGB10_A2UI = MALI_FORMAT_SPECIAL | 0x7, |
| 281 | MALI_RGB10_A2I = MALI_FORMAT_SPECIAL | 0x9, |
| 282 | |
| 283 | /* YUV formats */ |
| 284 | MALI_NV12 = MALI_FORMAT_SPECIAL | 0xc, |
| 285 | |
| 286 | MALI_Z32_UNORM = MALI_FORMAT_SPECIAL | 0xD, |
| 287 | MALI_R32_FIXED = MALI_FORMAT_SPECIAL | 0x11, |
| 288 | MALI_RG32_FIXED = MALI_FORMAT_SPECIAL | 0x12, |
| 289 | MALI_RGB32_FIXED = MALI_FORMAT_SPECIAL | 0x13, |
| 290 | MALI_RGBA32_FIXED = MALI_FORMAT_SPECIAL | 0x14, |
| 291 | MALI_R11F_G11F_B10F = MALI_FORMAT_SPECIAL | 0x19, |
Alyssa Rosenzweig | 601d4d3 | 2019-06-26 16:24:28 -0700 | [diff] [blame] | 292 | MALI_R9F_G9F_B9F_E5F = MALI_FORMAT_SPECIAL | 0x1b, |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 293 | /* Only used for varyings, to indicate the transformed gl_Position */ |
| 294 | MALI_VARYING_POS = MALI_FORMAT_SPECIAL | 0x1e, |
| 295 | /* Only used for varyings, to indicate that the write should be |
| 296 | * discarded. |
| 297 | */ |
| 298 | MALI_VARYING_DISCARD = MALI_FORMAT_SPECIAL | 0x1f, |
| 299 | |
| 300 | MALI_R8_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_8, |
| 301 | MALI_R16_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_16, |
| 302 | MALI_R32_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_32, |
| 303 | MALI_RG8_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_8, |
| 304 | MALI_RG16_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_16, |
| 305 | MALI_RG32_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_32, |
| 306 | MALI_RGB8_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_8, |
| 307 | MALI_RGB16_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_16, |
| 308 | MALI_RGB32_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_32, |
| 309 | MALI_RGBA8_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_8, |
| 310 | MALI_RGBA16_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_16, |
| 311 | MALI_RGBA32_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_32, |
| 312 | |
| 313 | MALI_R8UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_8, |
| 314 | MALI_R16UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_16, |
| 315 | MALI_R32UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_32, |
| 316 | MALI_RG8UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_8, |
| 317 | MALI_RG16UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_16, |
| 318 | MALI_RG32UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_32, |
| 319 | MALI_RGB8UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_8, |
| 320 | MALI_RGB16UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_16, |
| 321 | MALI_RGB32UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_32, |
| 322 | MALI_RGBA8UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_8, |
| 323 | MALI_RGBA16UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_16, |
| 324 | MALI_RGBA32UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_32, |
| 325 | |
| 326 | MALI_R8_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_8, |
| 327 | MALI_R16_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_16, |
| 328 | MALI_R32_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_32, |
| 329 | MALI_R32F = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT, |
| 330 | MALI_RG8_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_8, |
| 331 | MALI_RG16_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_16, |
| 332 | MALI_RG32_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_32, |
| 333 | MALI_RG32F = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT, |
| 334 | MALI_RGB8_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_8, |
| 335 | MALI_RGB16_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_16, |
| 336 | MALI_RGB32_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_32, |
| 337 | MALI_RGB32F = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT, |
Alyssa Rosenzweig | 60270c8 | 2019-02-24 06:28:39 +0000 | [diff] [blame] | 338 | MALI_RGBA4_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_4, |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 339 | MALI_RGBA8_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_8, |
| 340 | MALI_RGBA16_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_16, |
| 341 | MALI_RGBA32_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_32, |
| 342 | MALI_RGBA32F = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT, |
| 343 | |
| 344 | MALI_R8I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_8, |
| 345 | MALI_R16I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_16, |
| 346 | MALI_R32I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_32, |
| 347 | MALI_R16F = MALI_FORMAT_SINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT, |
| 348 | MALI_RG8I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_8, |
| 349 | MALI_RG16I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_16, |
| 350 | MALI_RG32I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_32, |
| 351 | MALI_RG16F = MALI_FORMAT_SINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT, |
| 352 | MALI_RGB8I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_8, |
| 353 | MALI_RGB16I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_16, |
| 354 | MALI_RGB32I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_32, |
| 355 | MALI_RGB16F = MALI_FORMAT_SINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT, |
| 356 | MALI_RGBA8I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_8, |
| 357 | MALI_RGBA16I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_16, |
| 358 | MALI_RGBA32I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_32, |
| 359 | MALI_RGBA16F = MALI_FORMAT_SINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT, |
| 360 | |
| 361 | MALI_RGBA4 = MALI_FORMAT_SPECIAL2 | 0x8, |
| 362 | MALI_RGBA8_2 = MALI_FORMAT_SPECIAL2 | 0xd, |
| 363 | MALI_RGB10_A2_2 = MALI_FORMAT_SPECIAL2 | 0xe, |
| 364 | }; |
| 365 | |
| 366 | |
| 367 | /* Alpha coverage is encoded as 4-bits (from a clampf), with inversion |
| 368 | * literally performing a bitwise invert. This function produces slightly wrong |
| 369 | * results and I'm not sure why; some rounding issue I suppose... */ |
| 370 | |
| 371 | #define MALI_ALPHA_COVERAGE(clampf) ((uint16_t) (int) (clampf * 15.0f)) |
| 372 | #define MALI_GET_ALPHA_COVERAGE(nibble) ((float) nibble / 15.0f) |
| 373 | |
Alyssa Rosenzweig | bd2fc60 | 2019-06-20 16:41:39 -0700 | [diff] [blame] | 374 | /* Applies to midgard1.flags */ |
Alyssa Rosenzweig | 8d1adc0 | 2019-06-07 16:00:49 -0700 | [diff] [blame] | 375 | |
| 376 | /* Should the hardware perform early-Z testing? Normally should be set |
| 377 | * for performance reasons. Clear if you use: discard, |
| 378 | * alpha-to-coverage... * It's also possible this disables |
| 379 | * forward-pixel kill; we're not quite sure which bit is which yet. |
| 380 | * TODO: How does this interact with blending?*/ |
| 381 | |
Alyssa Rosenzweig | bd2fc60 | 2019-06-20 16:41:39 -0700 | [diff] [blame] | 382 | #define MALI_EARLY_Z (1 << 6) |
Alyssa Rosenzweig | 8d1adc0 | 2019-06-07 16:00:49 -0700 | [diff] [blame] | 383 | |
| 384 | /* Should the hardware calculate derivatives (via helper invocations)? Set in a |
| 385 | * fragment shader that uses texturing or derivative functions */ |
| 386 | |
Alyssa Rosenzweig | bd2fc60 | 2019-06-20 16:41:39 -0700 | [diff] [blame] | 387 | #define MALI_HELPER_INVOCATIONS (1 << 7) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 388 | |
Alyssa Rosenzweig | 7cccc89 | 2019-04-05 01:17:21 +0000 | [diff] [blame] | 389 | /* Flags denoting the fragment shader's use of tilebuffer readback. If the |
| 390 | * shader might read any part of the tilebuffer, set MALI_READS_TILEBUFFER. If |
| 391 | * it might read depth/stencil in particular, also set MALI_READS_ZS */ |
| 392 | |
Alyssa Rosenzweig | bd2fc60 | 2019-06-20 16:41:39 -0700 | [diff] [blame] | 393 | #define MALI_READS_ZS (1 << 8) |
| 394 | #define MALI_READS_TILEBUFFER (1 << 12) |
Alyssa Rosenzweig | 7cccc89 | 2019-04-05 01:17:21 +0000 | [diff] [blame] | 395 | |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 396 | /* The raw Midgard blend payload can either be an equation or a shader |
| 397 | * address, depending on the context */ |
| 398 | |
| 399 | union midgard_blend { |
| 400 | mali_ptr shader; |
Alyssa Rosenzweig | 3645c78 | 2019-05-18 20:36:00 +0000 | [diff] [blame] | 401 | |
| 402 | struct { |
| 403 | struct mali_blend_equation equation; |
| 404 | float constant; |
| 405 | }; |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 406 | }; |
| 407 | |
Alyssa Rosenzweig | fd81916 | 2019-11-12 14:19:52 -0500 | [diff] [blame] | 408 | /* We need to load the tilebuffer to blend (i.e. the destination factor is not |
| 409 | * ZERO) */ |
| 410 | |
| 411 | #define MALI_BLEND_LOAD_TIB (0x1) |
| 412 | |
| 413 | /* A blend shader is used to blend this render target */ |
| 414 | #define MALI_BLEND_MRT_SHADER (0x2) |
| 415 | |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 416 | /* On MRT Midgard systems (using an MFBD), each render target gets its own |
| 417 | * blend descriptor */ |
| 418 | |
Alyssa Rosenzweig | 6585bb9 | 2019-06-17 16:23:23 -0700 | [diff] [blame] | 419 | #define MALI_BLEND_SRGB (0x400) |
| 420 | |
Alyssa Rosenzweig | 5c554e2 | 2019-07-17 16:19:45 -0700 | [diff] [blame] | 421 | /* Dithering is specified here for MFBD, otherwise NO_DITHER for SFBD */ |
| 422 | #define MALI_BLEND_NO_DITHER (0x800) |
| 423 | |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 424 | struct midgard_blend_rt { |
| 425 | /* Flags base value of 0x200 to enable the render target. |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 426 | * OR with 0x1 for blending (anything other than REPLACE). |
Alyssa Rosenzweig | 71dd52e | 2019-11-30 13:24:46 -0500 | [diff] [blame] | 427 | * OR with 0x2 for programmable blending |
Alyssa Rosenzweig | 6585bb9 | 2019-06-17 16:23:23 -0700 | [diff] [blame] | 428 | * OR with MALI_BLEND_SRGB for implicit sRGB |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 429 | */ |
| 430 | |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 431 | u64 flags; |
| 432 | union midgard_blend blend; |
| 433 | } __attribute__((packed)); |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 434 | |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 435 | /* On Bifrost systems (all MRT), each render target gets one of these |
| 436 | * descriptors */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 437 | |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 438 | struct bifrost_blend_rt { |
| 439 | /* This is likely an analogue of the flags on |
| 440 | * midgard_blend_rt */ |
| 441 | |
Alyssa Rosenzweig | ae70538 | 2019-05-18 20:48:43 +0000 | [diff] [blame] | 442 | u16 flags; // = 0x200 |
| 443 | |
| 444 | /* Single-channel blend constants are encoded in a sort of |
| 445 | * fixed-point. Basically, the float is mapped to a byte, becoming |
| 446 | * a high byte, and then the lower-byte is added for precision. |
| 447 | * For the original float f: |
| 448 | * |
| 449 | * f = (constant_hi / 255) + (constant_lo / 65535) |
| 450 | * |
| 451 | * constant_hi = int(f / 255) |
| 452 | * constant_lo = 65535*f - (65535/255) * constant_hi |
| 453 | */ |
| 454 | |
| 455 | u16 constant; |
| 456 | |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 457 | struct mali_blend_equation equation; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 458 | /* |
| 459 | * - 0x19 normally |
| 460 | * - 0x3 when this slot is unused (everything else is 0 except the index) |
| 461 | * - 0x11 when this is the fourth slot (and it's used) |
| 462 | + * - 0 when there is a blend shader |
| 463 | */ |
| 464 | u16 unk2; |
| 465 | /* increments from 0 to 3 */ |
| 466 | u16 index; |
| 467 | |
| 468 | union { |
| 469 | struct { |
| 470 | /* So far, I've only seen: |
| 471 | * - R001 for 1-component formats |
| 472 | * - RG01 for 2-component formats |
| 473 | * - RGB1 for 3-component formats |
| 474 | * - RGBA for 4-component formats |
| 475 | */ |
| 476 | u32 swizzle : 12; |
| 477 | enum mali_format format : 8; |
| 478 | |
| 479 | /* Type of the shader output variable. Note, this can |
| 480 | * be different from the format. |
| 481 | * |
| 482 | * 0: f16 (mediump float) |
| 483 | * 1: f32 (highp float) |
| 484 | * 2: i32 (highp int) |
| 485 | * 3: u32 (highp uint) |
| 486 | * 4: i16 (mediump int) |
| 487 | * 5: u16 (mediump uint) |
| 488 | */ |
| 489 | u32 shader_type : 3; |
| 490 | u32 zero : 9; |
| 491 | }; |
| 492 | |
| 493 | /* Only the low 32 bits of the blend shader are stored, the |
| 494 | * high 32 bits are implicitly the same as the original shader. |
| 495 | * According to the kernel driver, the program counter for |
| 496 | * shaders is actually only 24 bits, so shaders cannot cross |
| 497 | * the 2^24-byte boundary, and neither can the blend shader. |
| 498 | * The blob handles this by allocating a 2^24 byte pool for |
| 499 | * shaders, and making sure that any blend shaders are stored |
| 500 | * in the same pool as the original shader. The kernel will |
| 501 | * make sure this allocation is aligned to 2^24 bytes. |
| 502 | */ |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 503 | u32 shader; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 504 | }; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 505 | } __attribute__((packed)); |
| 506 | |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 507 | /* Descriptor for the shader. Following this is at least one, up to four blend |
| 508 | * descriptors for each active render target */ |
| 509 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 510 | struct mali_shader_meta { |
| 511 | mali_ptr shader; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 512 | u16 sampler_count; |
Alyssa Rosenzweig | 194b49e | 2019-07-31 07:20:29 -0700 | [diff] [blame] | 513 | u16 texture_count; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 514 | u16 attribute_count; |
| 515 | u16 varying_count; |
| 516 | |
| 517 | union { |
| 518 | struct { |
| 519 | u32 uniform_buffer_count : 4; |
| 520 | u32 unk1 : 28; // = 0x800000 for vertex, 0x958020 for tiler |
| 521 | } bifrost1; |
| 522 | struct { |
Alyssa Rosenzweig | bd2fc60 | 2019-06-20 16:41:39 -0700 | [diff] [blame] | 523 | unsigned uniform_buffer_count : 4; |
| 524 | unsigned flags : 12; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 525 | |
Alyssa Rosenzweig | 95ba661 | 2019-12-27 13:01:17 -0500 | [diff] [blame] | 526 | /* vec4 units */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 527 | unsigned work_count : 5; |
| 528 | unsigned uniform_count : 5; |
| 529 | unsigned unknown2 : 6; |
| 530 | } midgard1; |
| 531 | }; |
| 532 | |
Alyssa Rosenzweig | 7a36c72 | 2019-07-11 07:01:56 -0700 | [diff] [blame] | 533 | /* Same as glPolygoOffset() arguments */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 534 | float depth_units; |
| 535 | float depth_factor; |
| 536 | |
| 537 | u32 unknown2_2; |
| 538 | |
| 539 | u16 alpha_coverage; |
| 540 | u16 unknown2_3; |
| 541 | |
| 542 | u8 stencil_mask_front; |
| 543 | u8 stencil_mask_back; |
| 544 | u16 unknown2_4; |
| 545 | |
| 546 | struct mali_stencil_test stencil_front; |
| 547 | struct mali_stencil_test stencil_back; |
| 548 | |
| 549 | union { |
| 550 | struct { |
| 551 | u32 unk3 : 7; |
| 552 | /* On Bifrost, some system values are preloaded in |
| 553 | * registers R55-R62 by the thread dispatcher prior to |
| 554 | * the start of shader execution. This is a bitfield |
| 555 | * with one entry for each register saying which |
| 556 | * registers need to be preloaded. Right now, the known |
| 557 | * values are: |
| 558 | * |
| 559 | * Vertex/compute: |
| 560 | * - R55 : gl_LocalInvocationID.xy |
| 561 | * - R56 : gl_LocalInvocationID.z + unknown in high 16 bits |
| 562 | * - R57 : gl_WorkGroupID.x |
| 563 | * - R58 : gl_WorkGroupID.y |
| 564 | * - R59 : gl_WorkGroupID.z |
| 565 | * - R60 : gl_GlobalInvocationID.x |
| 566 | * - R61 : gl_GlobalInvocationID.y/gl_VertexID (without base) |
| 567 | * - R62 : gl_GlobalInvocationID.z/gl_InstanceID (without base) |
| 568 | * |
| 569 | * Fragment: |
| 570 | * - R55 : unknown, never seen (but the bit for this is |
| 571 | * always set?) |
| 572 | * - R56 : unknown (bit always unset) |
| 573 | * - R57 : gl_PrimitiveID |
| 574 | * - R58 : gl_FrontFacing in low bit, potentially other stuff |
| 575 | * - R59 : u16 fragment coordinates (used to compute |
| 576 | * gl_FragCoord.xy, together with sample positions) |
| 577 | * - R60 : gl_SampleMask (used in epilog, so pretty |
| 578 | * much always used, but the bit is always 0 -- is |
| 579 | * this just always pushed?) |
| 580 | * - R61 : gl_SampleMaskIn and gl_SampleID, used by |
| 581 | * varying interpolation. |
| 582 | * - R62 : unknown (bit always unset). |
| 583 | */ |
| 584 | u32 preload_regs : 8; |
| 585 | /* In units of 8 bytes or 64 bits, since the |
| 586 | * uniform/const port loads 64 bits at a time. |
| 587 | */ |
| 588 | u32 uniform_count : 7; |
| 589 | u32 unk4 : 10; // = 2 |
| 590 | } bifrost2; |
| 591 | struct { |
| 592 | u32 unknown2_7; |
| 593 | } midgard2; |
| 594 | }; |
| 595 | |
| 596 | /* zero on bifrost */ |
| 597 | u32 unknown2_8; |
| 598 | |
| 599 | /* Blending information for the older non-MRT Midgard HW. Check for |
| 600 | * MALI_HAS_BLEND_SHADER to decide how to interpret. |
| 601 | */ |
| 602 | |
Alyssa Rosenzweig | 050b934 | 2019-05-04 21:57:01 +0000 | [diff] [blame] | 603 | union midgard_blend blend; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 604 | } __attribute__((packed)); |
| 605 | |
| 606 | /* This only concerns hardware jobs */ |
| 607 | |
| 608 | /* Possible values for job_descriptor_size */ |
| 609 | |
| 610 | #define MALI_JOB_32 0 |
| 611 | #define MALI_JOB_64 1 |
| 612 | |
| 613 | struct mali_job_descriptor_header { |
| 614 | u32 exception_status; |
| 615 | u32 first_incomplete_task; |
| 616 | u64 fault_pointer; |
| 617 | u8 job_descriptor_size : 1; |
| 618 | enum mali_job_type job_type : 7; |
| 619 | u8 job_barrier : 1; |
| 620 | u8 unknown_flags : 7; |
| 621 | u16 job_index; |
| 622 | u16 job_dependency_index_1; |
| 623 | u16 job_dependency_index_2; |
Alyssa Rosenzweig | 65e5c19 | 2019-12-27 13:03:22 -0500 | [diff] [blame] | 624 | u64 next_job; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 625 | } __attribute__((packed)); |
| 626 | |
Alyssa Rosenzweig | 358372b | 2019-08-09 16:04:24 -0700 | [diff] [blame] | 627 | /* These concern exception_status */ |
| 628 | |
| 629 | /* Access type causing a fault, paralleling AS_FAULTSTATUS_* entries in the |
| 630 | * kernel */ |
| 631 | |
| 632 | enum mali_exception_access { |
| 633 | /* Atomic in the kernel for MMU, but that doesn't make sense for a job |
| 634 | * fault so it's just unused */ |
| 635 | MALI_EXCEPTION_ACCESS_NONE = 0, |
| 636 | |
| 637 | MALI_EXCEPTION_ACCESS_EXECUTE = 1, |
| 638 | MALI_EXCEPTION_ACCESS_READ = 2, |
| 639 | MALI_EXCEPTION_ACCESS_WRITE = 3 |
| 640 | }; |
| 641 | |
Alyssa Rosenzweig | adf716d | 2019-12-05 09:06:53 -0500 | [diff] [blame] | 642 | /* Details about write_value from panfrost igt tests which use it as a generic |
Alyssa Rosenzweig | 9eae950 | 2019-12-04 08:59:29 -0500 | [diff] [blame] | 643 | * dword write primitive */ |
| 644 | |
Alyssa Rosenzweig | adf716d | 2019-12-05 09:06:53 -0500 | [diff] [blame] | 645 | #define MALI_WRITE_VALUE_ZERO 3 |
Alyssa Rosenzweig | 9eae950 | 2019-12-04 08:59:29 -0500 | [diff] [blame] | 646 | |
Alyssa Rosenzweig | adf716d | 2019-12-05 09:06:53 -0500 | [diff] [blame] | 647 | struct mali_payload_write_value { |
Alyssa Rosenzweig | 9eae950 | 2019-12-04 08:59:29 -0500 | [diff] [blame] | 648 | u64 address; |
| 649 | u32 value_descriptor; |
| 650 | u32 reserved; |
| 651 | u64 immediate; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 652 | } __attribute__((packed)); |
| 653 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 654 | /* |
| 655 | * Mali Attributes |
| 656 | * |
| 657 | * This structure lets the attribute unit compute the address of an attribute |
| 658 | * given the vertex and instance ID. Unfortunately, the way this works is |
| 659 | * rather complicated when instancing is enabled. |
| 660 | * |
| 661 | * To explain this, first we need to explain how compute and vertex threads are |
| 662 | * dispatched. This is a guess (although a pretty firm guess!) since the |
| 663 | * details are mostly hidden from the driver, except for attribute instancing. |
| 664 | * When a quad is dispatched, it receives a single, linear index. However, we |
| 665 | * need to translate that index into a (vertex id, instance id) pair, or a |
| 666 | * (local id x, local id y, local id z) triple for compute shaders (although |
| 667 | * vertex shaders and compute shaders are handled almost identically). |
| 668 | * Focusing on vertex shaders, one option would be to do: |
| 669 | * |
| 670 | * vertex_id = linear_id % num_vertices |
| 671 | * instance_id = linear_id / num_vertices |
| 672 | * |
| 673 | * but this involves a costly division and modulus by an arbitrary number. |
| 674 | * Instead, we could pad num_vertices. We dispatch padded_num_vertices * |
| 675 | * num_instances threads instead of num_vertices * num_instances, which results |
| 676 | * in some "extra" threads with vertex_id >= num_vertices, which we have to |
| 677 | * discard. The more we pad num_vertices, the more "wasted" threads we |
| 678 | * dispatch, but the division is potentially easier. |
| 679 | * |
| 680 | * One straightforward choice is to pad num_vertices to the next power of two, |
| 681 | * which means that the division and modulus are just simple bit shifts and |
| 682 | * masking. But the actual algorithm is a bit more complicated. The thread |
| 683 | * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition |
| 684 | * to dividing by a power of two. This is possibly using the technique |
| 685 | * described in patent US20170010862A1. As a result, padded_num_vertices can be |
| 686 | * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads, |
| 687 | * since we need less padding. |
| 688 | * |
| 689 | * padded_num_vertices is picked by the hardware. The driver just specifies the |
| 690 | * actual number of vertices. At least for Mali G71, the first few cases are |
| 691 | * given by: |
| 692 | * |
| 693 | * num_vertices | padded_num_vertices |
| 694 | * 3 | 4 |
| 695 | * 4-7 | 8 |
| 696 | * 8-11 | 12 (3 * 4) |
| 697 | * 12-15 | 16 |
| 698 | * 16-19 | 20 (5 * 4) |
| 699 | * |
| 700 | * Note that padded_num_vertices is a multiple of four (presumably because |
| 701 | * threads are dispatched in groups of 4). Also, padded_num_vertices is always |
| 702 | * at least one more than num_vertices, which seems like a quirk of the |
| 703 | * hardware. For larger num_vertices, the hardware uses the following |
| 704 | * algorithm: using the binary representation of num_vertices, we look at the |
| 705 | * most significant set bit as well as the following 3 bits. Let n be the |
| 706 | * number of bits after those 4 bits. Then we set padded_num_vertices according |
| 707 | * to the following table: |
| 708 | * |
| 709 | * high bits | padded_num_vertices |
| 710 | * 1000 | 9 * 2^n |
| 711 | * 1001 | 5 * 2^(n+1) |
| 712 | * 101x | 3 * 2^(n+2) |
| 713 | * 110x | 7 * 2^(n+1) |
| 714 | * 111x | 2^(n+4) |
| 715 | * |
| 716 | * For example, if num_vertices = 70 is passed to glDraw(), its binary |
| 717 | * representation is 1000110, so n = 3 and the high bits are 1000, and |
| 718 | * therefore padded_num_vertices = 9 * 2^3 = 72. |
| 719 | * |
| 720 | * The attribute unit works in terms of the original linear_id. if |
| 721 | * num_instances = 1, then they are the same, and everything is simple. |
| 722 | * However, with instancing things get more complicated. There are four |
| 723 | * possible modes, two of them we can group together: |
| 724 | * |
| 725 | * 1. Use the linear_id directly. Only used when there is no instancing. |
| 726 | * |
| 727 | * 2. Use the linear_id modulo a constant. This is used for per-vertex |
| 728 | * attributes with instancing enabled by making the constant equal |
| 729 | * padded_num_vertices. Because the modulus is always padded_num_vertices, this |
| 730 | * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9. |
| 731 | * The shift field specifies the power of two, while the extra_flags field |
| 732 | * specifies the odd number. If shift = n and extra_flags = m, then the modulus |
| 733 | * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed |
| 734 | * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and |
| 735 | * shift = 3. Note that we must exactly follow the hardware algorithm used to |
| 736 | * get padded_num_vertices in order to correctly implement per-vertex |
| 737 | * attributes. |
| 738 | * |
| 739 | * 3. Divide the linear_id by a constant. In order to correctly implement |
| 740 | * instance divisors, we have to divide linear_id by padded_num_vertices times |
| 741 | * to user-specified divisor. So first we compute padded_num_vertices, again |
| 742 | * following the exact same algorithm that the hardware uses, then multiply it |
| 743 | * by the GL-level divisor to get the hardware-level divisor. This case is |
| 744 | * further divided into two more cases. If the hardware-level divisor is a |
| 745 | * power of two, then we just need to shift. The shift amount is specified by |
| 746 | * the shift field, so that the hardware-level divisor is just 2^shift. |
| 747 | * |
| 748 | * If it isn't a power of two, then we have to divide by an arbitrary integer. |
| 749 | * For that, we use the well-known technique of multiplying by an approximation |
| 750 | * of the inverse. The driver must compute the magic multiplier and shift |
| 751 | * amount, and then the hardware does the multiplication and shift. The |
| 752 | * hardware and driver also use the "round-down" optimization as described in |
| 753 | * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf. |
| 754 | * The hardware further assumes the multiplier is between 2^31 and 2^32, so the |
| 755 | * high bit is implicitly set to 1 even though it is set to 0 by the driver -- |
| 756 | * presumably this simplifies the hardware multiplier a little. The hardware |
| 757 | * first multiplies linear_id by the multiplier and takes the high 32 bits, |
| 758 | * then applies the round-down correction if extra_flags = 1, then finally |
| 759 | * shifts right by the shift field. |
| 760 | * |
| 761 | * There are some differences between ridiculousfish's algorithm and the Mali |
| 762 | * hardware algorithm, which means that the reference code from ridiculousfish |
| 763 | * doesn't always produce the right constants. Mali does not use the pre-shift |
| 764 | * optimization, since that would make a hardware implementation slower (it |
| 765 | * would have to always do the pre-shift, multiply, and post-shift operations). |
| 766 | * It also forces the multplier to be at least 2^31, which means that the |
| 767 | * exponent is entirely fixed, so there is no trial-and-error. Altogether, |
| 768 | * given the divisor d, the algorithm the driver must follow is: |
| 769 | * |
| 770 | * 1. Set shift = floor(log2(d)). |
| 771 | * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d. |
| 772 | * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set |
| 773 | * magic_divisor = m - 1 and extra_flags = 1. |
| 774 | * 4. Otherwise, set magic_divisor = m and extra_flags = 0. |
Alyssa Rosenzweig | a692126 | 2019-07-30 17:27:03 -0700 | [diff] [blame] | 775 | * |
| 776 | * Unrelated to instancing/actual attributes, images (the OpenCL kind) are |
| 777 | * implemented as special attributes, denoted by MALI_ATTR_IMAGE. For images, |
| 778 | * let shift=extra_flags=0. Stride is set to the image format's bytes-per-pixel |
| 779 | * (*NOT the row stride*). Size is set to the size of the image itself. |
Alyssa Rosenzweig | f3e1512 | 2019-07-31 11:56:55 -0700 | [diff] [blame] | 780 | * |
Alyssa Rosenzweig | 5f83761 | 2019-12-27 12:10:24 -0500 | [diff] [blame] | 781 | * Special internal attribtues and varyings (gl_VertexID, gl_FrontFacing, etc) |
| 782 | * use particular fixed addresses with modified structures. |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 783 | */ |
| 784 | |
| 785 | enum mali_attr_mode { |
| 786 | MALI_ATTR_UNUSED = 0, |
| 787 | MALI_ATTR_LINEAR = 1, |
| 788 | MALI_ATTR_POT_DIVIDE = 2, |
| 789 | MALI_ATTR_MODULO = 3, |
| 790 | MALI_ATTR_NPOT_DIVIDE = 4, |
Alyssa Rosenzweig | f3e1512 | 2019-07-31 11:56:55 -0700 | [diff] [blame] | 791 | MALI_ATTR_IMAGE = 5, |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 792 | }; |
| 793 | |
Alyssa Rosenzweig | 3b3d965 | 2019-12-19 12:28:42 -0500 | [diff] [blame] | 794 | /* Pseudo-address for gl_VertexID, gl_FragCoord, gl_FrontFacing */ |
Alyssa Rosenzweig | f3e1512 | 2019-07-31 11:56:55 -0700 | [diff] [blame] | 795 | |
Alyssa Rosenzweig | 3b3d965 | 2019-12-19 12:28:42 -0500 | [diff] [blame] | 796 | #define MALI_ATTR_VERTEXID (0x22) |
| 797 | #define MALI_ATTR_INSTANCEID (0x24) |
Alyssa Rosenzweig | 2c5ba2e | 2019-08-22 11:29:23 -0700 | [diff] [blame] | 798 | #define MALI_VARYING_FRAG_COORD (0x25) |
| 799 | #define MALI_VARYING_FRONT_FACING (0x26) |
Alyssa Rosenzweig | f3e1512 | 2019-07-31 11:56:55 -0700 | [diff] [blame] | 800 | |
Alyssa Rosenzweig | b98955e | 2019-03-15 23:25:55 +0000 | [diff] [blame] | 801 | /* This magic "pseudo-address" is used as `elements` to implement |
| 802 | * gl_PointCoord. When read from a fragment shader, it generates a point |
| 803 | * coordinate per the OpenGL ES 2.0 specification. Flipped coordinate spaces |
| 804 | * require an affine transformation in the shader. */ |
| 805 | |
Alyssa Rosenzweig | 2c5ba2e | 2019-08-22 11:29:23 -0700 | [diff] [blame] | 806 | #define MALI_VARYING_POINT_COORD (0x61) |
| 807 | |
| 808 | /* Used for comparison to check if an address is special. Mostly a guess, but |
| 809 | * it doesn't really matter. */ |
| 810 | |
Alyssa Rosenzweig | 3b3d965 | 2019-12-19 12:28:42 -0500 | [diff] [blame] | 811 | #define MALI_RECORD_SPECIAL (0x100) |
Alyssa Rosenzweig | b98955e | 2019-03-15 23:25:55 +0000 | [diff] [blame] | 812 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 813 | union mali_attr { |
| 814 | /* This is used for actual attributes. */ |
| 815 | struct { |
| 816 | /* The bottom 3 bits are the mode */ |
| 817 | mali_ptr elements : 64 - 8; |
| 818 | u32 shift : 5; |
| 819 | u32 extra_flags : 3; |
| 820 | u32 stride; |
| 821 | u32 size; |
| 822 | }; |
| 823 | /* The entry after an NPOT_DIVIDE entry has this format. It stores |
| 824 | * extra information that wouldn't fit in a normal entry. |
| 825 | */ |
| 826 | struct { |
| 827 | u32 unk; /* = 0x20 */ |
| 828 | u32 magic_divisor; |
| 829 | u32 zero; |
| 830 | /* This is the original, GL-level divisor. */ |
| 831 | u32 divisor; |
| 832 | }; |
| 833 | } __attribute__((packed)); |
| 834 | |
| 835 | struct mali_attr_meta { |
| 836 | /* Vertex buffer index */ |
| 837 | u8 index; |
| 838 | |
| 839 | unsigned unknown1 : 2; |
| 840 | unsigned swizzle : 12; |
| 841 | enum mali_format format : 8; |
| 842 | |
| 843 | /* Always observed to be zero at the moment */ |
| 844 | unsigned unknown3 : 2; |
| 845 | |
Alyssa Rosenzweig | 8d74749 | 2019-06-27 14:13:10 -0700 | [diff] [blame] | 846 | /* When packing multiple attributes in a buffer, offset addresses by |
| 847 | * this value. Obscurely, this is signed. */ |
| 848 | int32_t src_offset; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 849 | } __attribute__((packed)); |
| 850 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 851 | #define FBD_MASK (~0x3f) |
| 852 | |
Alyssa Rosenzweig | 8959364 | 2019-12-16 12:05:45 -0500 | [diff] [blame] | 853 | /* MFBD, rather than SFBD */ |
| 854 | #define MALI_MFBD (0x1) |
| 855 | |
Alyssa Rosenzweig | f06e8f7 | 2019-08-21 12:06:50 -0700 | [diff] [blame] | 856 | /* ORed into an MFBD address to specify the fbx section is included */ |
| 857 | #define MALI_MFBD_TAG_EXTRA (0x2) |
| 858 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 859 | struct mali_uniform_buffer_meta { |
| 860 | /* This is actually the size minus 1 (MALI_POSITIVE), in units of 16 |
| 861 | * bytes. This gives a maximum of 2^14 bytes, which just so happens to |
| 862 | * be the GL minimum-maximum for GL_MAX_UNIFORM_BLOCK_SIZE. |
| 863 | */ |
| 864 | u64 size : 10; |
| 865 | |
| 866 | /* This is missing the bottom 2 bits and top 8 bits. The top 8 bits |
| 867 | * should be 0 for userspace pointers, according to |
| 868 | * https://lwn.net/Articles/718895/. By reusing these bits, we can make |
| 869 | * each entry in the table only 64 bits. |
| 870 | */ |
| 871 | mali_ptr ptr : 64 - 10; |
| 872 | }; |
| 873 | |
| 874 | /* On Bifrost, these fields are the same between the vertex and tiler payloads. |
| 875 | * They also seem to be the same between Bifrost and Midgard. They're shared in |
| 876 | * fused payloads. |
| 877 | */ |
| 878 | |
| 879 | /* Applies to unknown_draw */ |
Alyssa Rosenzweig | 72981c9 | 2019-02-27 04:33:13 +0000 | [diff] [blame] | 880 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 881 | #define MALI_DRAW_INDEXED_UINT8 (0x10) |
| 882 | #define MALI_DRAW_INDEXED_UINT16 (0x20) |
| 883 | #define MALI_DRAW_INDEXED_UINT32 (0x30) |
Alyssa Rosenzweig | f38ce6e | 2019-08-21 16:06:23 -0700 | [diff] [blame] | 884 | #define MALI_DRAW_INDEXED_SIZE (0x30) |
| 885 | #define MALI_DRAW_INDEXED_SHIFT (4) |
| 886 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 887 | #define MALI_DRAW_VARYING_SIZE (0x100) |
Alyssa Rosenzweig | 71df7c6 | 2019-12-27 15:33:21 -0500 | [diff] [blame] | 888 | |
| 889 | /* Set to use first vertex as the provoking vertex for flatshading. Clear to |
| 890 | * use the last vertex. This is the default in DX and VK, but not in GL. */ |
| 891 | |
| 892 | #define MALI_DRAW_FLATSHADE_FIRST (0x800) |
| 893 | |
Alyssa Rosenzweig | 72981c9 | 2019-02-27 04:33:13 +0000 | [diff] [blame] | 894 | #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 895 | |
| 896 | struct mali_vertex_tiler_prefix { |
| 897 | /* This is a dynamic bitfield containing the following things in this order: |
| 898 | * |
| 899 | * - gl_WorkGroupSize.x |
| 900 | * - gl_WorkGroupSize.y |
| 901 | * - gl_WorkGroupSize.z |
| 902 | * - gl_NumWorkGroups.x |
| 903 | * - gl_NumWorkGroups.y |
| 904 | * - gl_NumWorkGroups.z |
| 905 | * |
| 906 | * The number of bits allocated for each number is based on the *_shift |
| 907 | * fields below. For example, workgroups_y_shift gives the bit that |
| 908 | * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit |
| 909 | * that gl_NumWorkGroups.z starts at (and therefore one after the bit |
| 910 | * that gl_NumWorkGroups.y ends at). The actual value for each gl_* |
| 911 | * value is one more than the stored value, since if any of the values |
| 912 | * are zero, then there would be no invocations (and hence no job). If |
| 913 | * there were 0 bits allocated to a given field, then it must be zero, |
| 914 | * and hence the real value is one. |
| 915 | * |
| 916 | * Vertex jobs reuse the same job dispatch mechanism as compute jobs, |
| 917 | * effectively doing glDispatchCompute(1, vertex_count, instance_count) |
| 918 | * where vertex count is the number of vertices. |
| 919 | */ |
| 920 | u32 invocation_count; |
| 921 | |
Alyssa Rosenzweig | 6378797 | 2019-12-12 11:28:08 -0500 | [diff] [blame] | 922 | /* Bitfield for shifts: |
| 923 | * |
| 924 | * size_y_shift : 5 |
| 925 | * size_z_shift : 5 |
| 926 | * workgroups_x_shift : 6 |
| 927 | * workgroups_y_shift : 6 |
| 928 | * workgroups_z_shift : 6 |
| 929 | * workgroups_x_shift_2 : 4 |
| 930 | */ |
| 931 | u32 invocation_shifts; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 932 | |
| 933 | u32 draw_mode : 4; |
| 934 | u32 unknown_draw : 22; |
| 935 | |
| 936 | /* This is the the same as workgroups_x_shift_2 in compute shaders, but |
| 937 | * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has |
| 938 | * something to do with how many quads get put in the same execution |
| 939 | * engine, which is a balance (you don't want to starve the engine, but |
| 940 | * you also want to distribute work evenly). |
| 941 | */ |
| 942 | u32 workgroups_x_shift_3 : 6; |
| 943 | |
| 944 | |
Rohan Garg | 16edd56 | 2019-07-17 18:50:13 +0200 | [diff] [blame] | 945 | /* Negative of min_index. This is used to compute |
| 946 | * the unbiased index in tiler/fragment shader runs. |
| 947 | * |
| 948 | * The hardware adds offset_bias_correction in each run, |
| 949 | * so that absent an index bias, the first vertex processed is |
| 950 | * genuinely the first vertex (0). But with an index bias, |
| 951 | * the first vertex process is numbered the same as the bias. |
| 952 | * |
| 953 | * To represent this more conviniently: |
| 954 | * unbiased_index = lower_bound_index + |
| 955 | * index_bias + |
| 956 | * offset_bias_correction |
| 957 | * |
| 958 | * This is done since the hardware doesn't accept a index_bias |
| 959 | * and this allows it to recover the unbiased index. |
| 960 | */ |
| 961 | int32_t offset_bias_correction; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 962 | u32 zero1; |
| 963 | |
| 964 | /* Like many other strictly nonzero quantities, index_count is |
| 965 | * subtracted by one. For an indexed cube, this is equal to 35 = 6 |
| 966 | * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is, |
| 967 | * for an indexed draw, index_count is the number of actual vertices |
| 968 | * rendered whereas invocation_count is the number of unique vertices |
| 969 | * rendered (the number of times the vertex shader must be invoked). |
| 970 | * For non-indexed draws, this is just equal to invocation_count. */ |
| 971 | |
| 972 | u32 index_count; |
| 973 | |
| 974 | /* No hidden structure; literally just a pointer to an array of uint |
| 975 | * indices (width depends on flags). Thanks, guys, for not making my |
| 976 | * life insane for once! NULL for non-indexed draws. */ |
| 977 | |
Tomeu Vizoso | 5a7688f | 2019-07-11 08:06:41 +0200 | [diff] [blame] | 978 | u64 indices; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 979 | } __attribute__((packed)); |
| 980 | |
| 981 | /* Point size / line width can either be specified as a 32-bit float (for |
| 982 | * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer |
| 983 | * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler |
| 984 | * payload, the contents of varying_pointer will be intepreted as an array of |
| 985 | * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by |
| 986 | * creating a special MALI_R16F varying writing to varying_pointer. */ |
| 987 | |
| 988 | union midgard_primitive_size { |
| 989 | float constant; |
Tomeu Vizoso | 5a7688f | 2019-07-11 08:06:41 +0200 | [diff] [blame] | 990 | u64 pointer; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 991 | }; |
| 992 | |
| 993 | struct bifrost_vertex_only { |
| 994 | u32 unk2; /* =0x2 */ |
| 995 | |
| 996 | u32 zero0; |
| 997 | |
| 998 | u64 zero1; |
| 999 | } __attribute__((packed)); |
| 1000 | |
| 1001 | struct bifrost_tiler_heap_meta { |
| 1002 | u32 zero; |
| 1003 | u32 heap_size; |
| 1004 | /* note: these are just guesses! */ |
| 1005 | mali_ptr tiler_heap_start; |
| 1006 | mali_ptr tiler_heap_free; |
| 1007 | mali_ptr tiler_heap_end; |
| 1008 | |
| 1009 | /* hierarchy weights? but they're still 0 after the job has run... */ |
| 1010 | u32 zeros[12]; |
| 1011 | } __attribute__((packed)); |
| 1012 | |
| 1013 | struct bifrost_tiler_meta { |
| 1014 | u64 zero0; |
Alyssa Rosenzweig | 7f26bb3 | 2019-06-13 10:25:32 -0700 | [diff] [blame] | 1015 | u16 hierarchy_mask; |
| 1016 | u16 flags; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1017 | u16 width; |
| 1018 | u16 height; |
| 1019 | u64 zero1; |
| 1020 | mali_ptr tiler_heap_meta; |
| 1021 | /* TODO what is this used for? */ |
| 1022 | u64 zeros[20]; |
| 1023 | } __attribute__((packed)); |
| 1024 | |
| 1025 | struct bifrost_tiler_only { |
| 1026 | /* 0x20 */ |
| 1027 | union midgard_primitive_size primitive_size; |
| 1028 | |
| 1029 | mali_ptr tiler_meta; |
| 1030 | |
| 1031 | u64 zero1, zero2, zero3, zero4, zero5, zero6; |
| 1032 | |
| 1033 | u32 gl_enables; |
| 1034 | u32 zero7; |
| 1035 | u64 zero8; |
| 1036 | } __attribute__((packed)); |
| 1037 | |
| 1038 | struct bifrost_scratchpad { |
| 1039 | u32 zero; |
| 1040 | u32 flags; // = 0x1f |
| 1041 | /* This is a pointer to a CPU-inaccessible buffer, 16 pages, allocated |
| 1042 | * during startup. It seems to serve the same purpose as the |
| 1043 | * gpu_scratchpad in the SFBD for Midgard, although it's slightly |
| 1044 | * larger. |
| 1045 | */ |
| 1046 | mali_ptr gpu_scratchpad; |
| 1047 | } __attribute__((packed)); |
| 1048 | |
| 1049 | struct mali_vertex_tiler_postfix { |
| 1050 | /* Zero for vertex jobs. Pointer to the position (gl_Position) varying |
| 1051 | * output from the vertex shader for tiler jobs. |
| 1052 | */ |
| 1053 | |
Tomeu Vizoso | 5a7688f | 2019-07-11 08:06:41 +0200 | [diff] [blame] | 1054 | u64 position_varying; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1055 | |
| 1056 | /* An array of mali_uniform_buffer_meta's. The size is given by the |
| 1057 | * shader_meta. |
| 1058 | */ |
Tomeu Vizoso | 5a7688f | 2019-07-11 08:06:41 +0200 | [diff] [blame] | 1059 | u64 uniform_buffers; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1060 | |
| 1061 | /* This is a pointer to an array of pointers to the texture |
| 1062 | * descriptors, number of pointers bounded by number of textures. The |
| 1063 | * indirection is needed to accomodate varying numbers and sizes of |
| 1064 | * texture descriptors */ |
Tomeu Vizoso | 5a7688f | 2019-07-11 08:06:41 +0200 | [diff] [blame] | 1065 | u64 texture_trampoline; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1066 | |
| 1067 | /* For OpenGL, from what I've seen, this is intimately connected to |
| 1068 | * texture_meta. cwabbott says this is not the case under Vulkan, hence |
| 1069 | * why this field is seperate (Midgard is Vulkan capable). Pointer to |
| 1070 | * array of sampler descriptors (which are uniform in size) */ |
Tomeu Vizoso | 5a7688f | 2019-07-11 08:06:41 +0200 | [diff] [blame] | 1071 | u64 sampler_descriptor; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1072 | |
Tomeu Vizoso | 5a7688f | 2019-07-11 08:06:41 +0200 | [diff] [blame] | 1073 | u64 uniforms; |
Alyssa Rosenzweig | fa14cdf | 2019-10-27 19:46:21 -0400 | [diff] [blame] | 1074 | u64 shader; |
Tomeu Vizoso | 5a7688f | 2019-07-11 08:06:41 +0200 | [diff] [blame] | 1075 | u64 attributes; /* struct attribute_buffer[] */ |
| 1076 | u64 attribute_meta; /* attribute_meta[] */ |
| 1077 | u64 varyings; /* struct attr */ |
| 1078 | u64 varying_meta; /* pointer */ |
| 1079 | u64 viewport; |
| 1080 | u64 occlusion_counter; /* A single bit as far as I can tell */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1081 | |
| 1082 | /* Note: on Bifrost, this isn't actually the FBD. It points to |
| 1083 | * bifrost_scratchpad instead. However, it does point to the same thing |
| 1084 | * in vertex and tiler jobs. |
| 1085 | */ |
| 1086 | mali_ptr framebuffer; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1087 | } __attribute__((packed)); |
| 1088 | |
| 1089 | struct midgard_payload_vertex_tiler { |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1090 | struct mali_vertex_tiler_prefix prefix; |
| 1091 | |
Alyssa Rosenzweig | 8d74749 | 2019-06-27 14:13:10 -0700 | [diff] [blame] | 1092 | u16 gl_enables; // 0x5 |
| 1093 | |
| 1094 | /* Both zero for non-instanced draws. For instanced draws, a |
| 1095 | * decomposition of padded_num_vertices. See the comments about the |
| 1096 | * corresponding fields in mali_attr for context. */ |
| 1097 | |
| 1098 | unsigned instance_shift : 5; |
| 1099 | unsigned instance_odd : 3; |
| 1100 | |
| 1101 | u8 zero4; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1102 | |
| 1103 | /* Offset for first vertex in buffer */ |
Rohan Garg | 16edd56 | 2019-07-17 18:50:13 +0200 | [diff] [blame] | 1104 | u32 offset_start; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1105 | |
Tomeu Vizoso | 5a7688f | 2019-07-11 08:06:41 +0200 | [diff] [blame] | 1106 | u64 zero5; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1107 | |
| 1108 | struct mali_vertex_tiler_postfix postfix; |
| 1109 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1110 | union midgard_primitive_size primitive_size; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1111 | } __attribute__((packed)); |
| 1112 | |
| 1113 | struct bifrost_payload_vertex { |
| 1114 | struct mali_vertex_tiler_prefix prefix; |
| 1115 | struct bifrost_vertex_only vertex; |
| 1116 | struct mali_vertex_tiler_postfix postfix; |
| 1117 | } __attribute__((packed)); |
| 1118 | |
| 1119 | struct bifrost_payload_tiler { |
| 1120 | struct mali_vertex_tiler_prefix prefix; |
| 1121 | struct bifrost_tiler_only tiler; |
| 1122 | struct mali_vertex_tiler_postfix postfix; |
| 1123 | } __attribute__((packed)); |
| 1124 | |
| 1125 | struct bifrost_payload_fused { |
| 1126 | struct mali_vertex_tiler_prefix prefix; |
| 1127 | struct bifrost_tiler_only tiler; |
| 1128 | struct mali_vertex_tiler_postfix tiler_postfix; |
Alyssa Rosenzweig | 6b2457e | 2019-05-18 21:04:33 +0000 | [diff] [blame] | 1129 | u64 padding; /* zero */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1130 | struct bifrost_vertex_only vertex; |
| 1131 | struct mali_vertex_tiler_postfix vertex_postfix; |
| 1132 | } __attribute__((packed)); |
| 1133 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1134 | /* Purposeful off-by-one in width, height fields. For example, a (64, 64) |
| 1135 | * texture is stored as (63, 63) in these fields. This adjusts for that. |
| 1136 | * There's an identical pattern in the framebuffer descriptor. Even vertex |
| 1137 | * count fields work this way, hence the generic name -- integral fields that |
| 1138 | * are strictly positive generally need this adjustment. */ |
| 1139 | |
| 1140 | #define MALI_POSITIVE(dim) (dim - 1) |
| 1141 | |
Alyssa Rosenzweig | 5fe5827 | 2019-12-27 12:42:53 -0500 | [diff] [blame] | 1142 | /* Used with wrapping. Unclear what top bit conveys */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1143 | |
| 1144 | enum mali_wrap_mode { |
Alyssa Rosenzweig | 5fe5827 | 2019-12-27 12:42:53 -0500 | [diff] [blame] | 1145 | MALI_WRAP_REPEAT = 0x8 | 0x0, |
| 1146 | MALI_WRAP_CLAMP_TO_EDGE = 0x8 | 0x1, |
| 1147 | MALI_WRAP_CLAMP = 0x8 | 0x2, |
| 1148 | MALI_WRAP_CLAMP_TO_BORDER = 0x8 | 0x3, |
| 1149 | MALI_WRAP_MIRRORED_REPEAT = 0x8 | 0x4 | 0x0, |
| 1150 | MALI_WRAP_MIRRORED_CLAMP_TO_EDGE = 0x8 | 0x4 | 0x1, |
| 1151 | MALI_WRAP_MIRRORED_CLAMP = 0x8 | 0x4 | 0x2, |
| 1152 | MALI_WRAP_MIRRORED_CLAMP_TO_BORDER = 0x8 | 0x4 | 0x3, |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1153 | }; |
| 1154 | |
Alyssa Rosenzweig | 83c02a5 | 2019-06-17 14:26:08 -0700 | [diff] [blame] | 1155 | /* Shared across both command stream and Midgard, and even with Bifrost */ |
| 1156 | |
| 1157 | enum mali_texture_type { |
| 1158 | MALI_TEX_CUBE = 0x0, |
| 1159 | MALI_TEX_1D = 0x1, |
| 1160 | MALI_TEX_2D = 0x2, |
| 1161 | MALI_TEX_3D = 0x3 |
| 1162 | }; |
| 1163 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1164 | /* 8192x8192 */ |
| 1165 | #define MAX_MIP_LEVELS (13) |
| 1166 | |
| 1167 | /* Cubemap bloats everything up */ |
Alyssa Rosenzweig | 83c02a5 | 2019-06-17 14:26:08 -0700 | [diff] [blame] | 1168 | #define MAX_CUBE_FACES (6) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1169 | |
Alyssa Rosenzweig | 416fc3b | 2019-06-07 14:25:28 -0700 | [diff] [blame] | 1170 | /* For each pointer, there is an address and optionally also a stride */ |
| 1171 | #define MAX_ELEMENTS (2) |
| 1172 | |
Alyssa Rosenzweig | 9f15f4d | 2019-08-20 15:36:00 -0700 | [diff] [blame] | 1173 | /* It's not known why there are 4-bits allocated -- this enum is almost |
| 1174 | * certainly incomplete */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1175 | |
Alyssa Rosenzweig | 9f15f4d | 2019-08-20 15:36:00 -0700 | [diff] [blame] | 1176 | enum mali_texture_layout { |
| 1177 | /* For a Z/S texture, this is linear */ |
| 1178 | MALI_TEXTURE_TILED = 0x1, |
| 1179 | |
| 1180 | /* Z/S textures cannot be tiled */ |
| 1181 | MALI_TEXTURE_LINEAR = 0x2, |
| 1182 | |
| 1183 | /* 16x16 sparse */ |
| 1184 | MALI_TEXTURE_AFBC = 0xC |
| 1185 | }; |
| 1186 | |
| 1187 | /* Corresponds to the type passed to glTexImage2D and so forth */ |
Alyssa Rosenzweig | cea93520 | 2019-05-14 22:42:47 +0000 | [diff] [blame] | 1188 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1189 | struct mali_texture_format { |
| 1190 | unsigned swizzle : 12; |
| 1191 | enum mali_format format : 8; |
| 1192 | |
Alyssa Rosenzweig | 83c02a5 | 2019-06-17 14:26:08 -0700 | [diff] [blame] | 1193 | unsigned srgb : 1; |
| 1194 | unsigned unknown1 : 1; |
| 1195 | |
| 1196 | enum mali_texture_type type : 2; |
Alyssa Rosenzweig | 9f15f4d | 2019-08-20 15:36:00 -0700 | [diff] [blame] | 1197 | enum mali_texture_layout layout : 4; |
Alyssa Rosenzweig | 83c02a5 | 2019-06-17 14:26:08 -0700 | [diff] [blame] | 1198 | |
Alyssa Rosenzweig | 9f15f4d | 2019-08-20 15:36:00 -0700 | [diff] [blame] | 1199 | /* Always set */ |
| 1200 | unsigned unknown2 : 1; |
| 1201 | |
| 1202 | /* Set to allow packing an explicit stride */ |
| 1203 | unsigned manual_stride : 1; |
| 1204 | |
| 1205 | unsigned zero : 2; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1206 | } __attribute__((packed)); |
| 1207 | |
| 1208 | struct mali_texture_descriptor { |
| 1209 | uint16_t width; |
| 1210 | uint16_t height; |
| 1211 | uint16_t depth; |
Alyssa Rosenzweig | bdf169a | 2019-06-14 16:23:32 -0700 | [diff] [blame] | 1212 | uint16_t array_size; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1213 | |
| 1214 | struct mali_texture_format format; |
| 1215 | |
| 1216 | uint16_t unknown3; |
| 1217 | |
| 1218 | /* One for non-mipmapped, zero for mipmapped */ |
| 1219 | uint8_t unknown3A; |
| 1220 | |
| 1221 | /* Zero for non-mipmapped, (number of levels - 1) for mipmapped */ |
Alyssa Rosenzweig | 96f6b8a | 2019-08-20 15:24:18 -0700 | [diff] [blame] | 1222 | uint8_t levels; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1223 | |
| 1224 | /* Swizzling is a single 32-bit word, broken up here for convenience. |
| 1225 | * Here, swizzling refers to the ES 3.0 texture parameters for channel |
| 1226 | * level swizzling, not the internal pixel-level swizzling which is |
| 1227 | * below OpenGL's reach */ |
| 1228 | |
| 1229 | unsigned swizzle : 12; |
| 1230 | unsigned swizzle_zero : 20; |
| 1231 | |
| 1232 | uint32_t unknown5; |
| 1233 | uint32_t unknown6; |
| 1234 | uint32_t unknown7; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1235 | } __attribute__((packed)); |
| 1236 | |
Alyssa Rosenzweig | cf6cad3 | 2019-07-31 08:50:02 -0700 | [diff] [blame] | 1237 | /* filter_mode */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1238 | |
Alyssa Rosenzweig | cf6cad3 | 2019-07-31 08:50:02 -0700 | [diff] [blame] | 1239 | #define MALI_SAMP_MAG_NEAREST (1 << 0) |
| 1240 | #define MALI_SAMP_MIN_NEAREST (1 << 1) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1241 | |
Alyssa Rosenzweig | cf6cad3 | 2019-07-31 08:50:02 -0700 | [diff] [blame] | 1242 | /* TODO: What do these bits mean individually? Only seen set together */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1243 | |
Alyssa Rosenzweig | cf6cad3 | 2019-07-31 08:50:02 -0700 | [diff] [blame] | 1244 | #define MALI_SAMP_MIP_LINEAR_1 (1 << 3) |
| 1245 | #define MALI_SAMP_MIP_LINEAR_2 (1 << 4) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1246 | |
Alyssa Rosenzweig | 3e47a11 | 2019-07-31 09:08:07 -0700 | [diff] [blame] | 1247 | /* Flag in filter_mode, corresponding to OpenCL's NORMALIZED_COORDS_TRUE |
| 1248 | * sampler_t flag. For typical OpenGL textures, this is always set. */ |
| 1249 | |
| 1250 | #define MALI_SAMP_NORM_COORDS (1 << 5) |
| 1251 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1252 | /* Used for lod encoding. Thanks @urjaman for pointing out these routines can |
| 1253 | * be cleaned up a lot. */ |
| 1254 | |
| 1255 | #define DECODE_FIXED_16(x) ((float) (x / 256.0)) |
| 1256 | |
Icecream95 | f2f1277 | 2020-01-09 15:13:58 +1300 | [diff] [blame^] | 1257 | static inline int16_t |
| 1258 | FIXED_16(float x, bool allow_negative) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1259 | { |
| 1260 | /* Clamp inputs, accounting for float error */ |
| 1261 | float max_lod = (32.0 - (1.0 / 512.0)); |
Icecream95 | f2f1277 | 2020-01-09 15:13:58 +1300 | [diff] [blame^] | 1262 | float min_lod = allow_negative ? -max_lod : 0.0; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1263 | |
Icecream95 | f2f1277 | 2020-01-09 15:13:58 +1300 | [diff] [blame^] | 1264 | x = ((x > max_lod) ? max_lod : ((x < min_lod) ? min_lod : x)); |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1265 | |
| 1266 | return (int) (x * 256.0); |
| 1267 | } |
| 1268 | |
| 1269 | struct mali_sampler_descriptor { |
Alyssa Rosenzweig | 046097c | 2019-11-20 09:26:48 -0500 | [diff] [blame] | 1270 | uint16_t filter_mode; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1271 | |
Icecream95 | f2f1277 | 2020-01-09 15:13:58 +1300 | [diff] [blame^] | 1272 | /* Fixed point, signed. |
| 1273 | * Upper 7 bits before the decimal point, although it caps [0-31]. |
| 1274 | * Lower 8 bits after the decimal point: int(round(x * 256)) */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1275 | |
Icecream95 | f2f1277 | 2020-01-09 15:13:58 +1300 | [diff] [blame^] | 1276 | int16_t lod_bias; |
| 1277 | int16_t min_lod; |
| 1278 | int16_t max_lod; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1279 | |
Alyssa Rosenzweig | de077c2 | 2019-12-27 12:56:03 -0500 | [diff] [blame] | 1280 | /* All one word in reality, but packed a bit. Comparisons are flipped |
| 1281 | * from OpenGL. */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1282 | |
| 1283 | enum mali_wrap_mode wrap_s : 4; |
| 1284 | enum mali_wrap_mode wrap_t : 4; |
| 1285 | enum mali_wrap_mode wrap_r : 4; |
Alyssa Rosenzweig | de077c2 | 2019-12-27 12:56:03 -0500 | [diff] [blame] | 1286 | enum mali_func compare_func : 3; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1287 | |
Alyssa Rosenzweig | 17adcfc | 2019-06-24 09:16:11 -0700 | [diff] [blame] | 1288 | /* No effect on 2D textures. For cubemaps, set for ES3 and clear for |
| 1289 | * ES2, controlling seamless cubemapping */ |
| 1290 | unsigned seamless_cube_map : 1; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1291 | |
| 1292 | unsigned zero : 16; |
| 1293 | |
| 1294 | uint32_t zero2; |
| 1295 | float border_color[4]; |
| 1296 | } __attribute__((packed)); |
| 1297 | |
Alyssa Rosenzweig | 7b5217a | 2019-05-18 21:01:03 +0000 | [diff] [blame] | 1298 | /* viewport0/viewport1 form the arguments to glViewport. viewport1 is |
| 1299 | * modified by MALI_POSITIVE; viewport0 is as-is. |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1300 | */ |
| 1301 | |
| 1302 | struct mali_viewport { |
Alyssa Rosenzweig | 49985ce | 2019-02-15 06:45:07 +0000 | [diff] [blame] | 1303 | /* XY clipping planes */ |
| 1304 | float clip_minx; |
| 1305 | float clip_miny; |
| 1306 | float clip_maxx; |
| 1307 | float clip_maxy; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1308 | |
Alyssa Rosenzweig | 49985ce | 2019-02-15 06:45:07 +0000 | [diff] [blame] | 1309 | /* Depth clipping planes */ |
| 1310 | float clip_minz; |
| 1311 | float clip_maxz; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1312 | |
| 1313 | u16 viewport0[2]; |
| 1314 | u16 viewport1[2]; |
| 1315 | } __attribute__((packed)); |
| 1316 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1317 | /* From presentations, 16x16 tiles externally. Use shift for fast computation |
| 1318 | * of tile numbers. */ |
| 1319 | |
| 1320 | #define MALI_TILE_SHIFT 4 |
| 1321 | #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT) |
| 1322 | |
| 1323 | /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to |
| 1324 | * each component. Notice that this provides a theoretical upper bound of (1 << |
| 1325 | * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size |
| 1326 | * 65536x65536. Multiplying that together, times another four given that Mali |
| 1327 | * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16 |
| 1328 | * gigabytes of RAM just to store the uncompressed framebuffer itself, let |
| 1329 | * alone rendering in real-time to such a buffer. |
| 1330 | * |
| 1331 | * Nice job, guys.*/ |
| 1332 | |
| 1333 | /* From mali_kbase_10969_workaround.c */ |
| 1334 | #define MALI_X_COORD_MASK 0x00000FFF |
| 1335 | #define MALI_Y_COORD_MASK 0x0FFF0000 |
| 1336 | |
| 1337 | /* Extract parts of a tile coordinate */ |
| 1338 | |
| 1339 | #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK) |
| 1340 | #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1341 | |
| 1342 | /* Helpers to generate tile coordinates based on the boundary coordinates in |
| 1343 | * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these |
| 1344 | * functions would convert it to the bounding tiles (0, 0) to (7, 7). |
| 1345 | * Intentional "off-by-one"; finding the tile number is a form of fencepost |
| 1346 | * problem. */ |
| 1347 | |
| 1348 | #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16)) |
| 1349 | #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT) |
| 1350 | #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias)) |
| 1351 | #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0) |
| 1352 | #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1) |
| 1353 | |
| 1354 | struct mali_payload_fragment { |
| 1355 | u32 min_tile_coord; |
| 1356 | u32 max_tile_coord; |
| 1357 | mali_ptr framebuffer; |
| 1358 | } __attribute__((packed)); |
| 1359 | |
Alyssa Rosenzweig | 7b5217a | 2019-05-18 21:01:03 +0000 | [diff] [blame] | 1360 | /* Single Framebuffer Descriptor */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1361 | |
| 1362 | /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is |
| 1363 | * configured for 4x. With MSAA_8, it is configured for 8x. */ |
| 1364 | |
Tomeu Vizoso | 9447a84 | 2019-10-30 12:05:30 +0100 | [diff] [blame] | 1365 | #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3) |
| 1366 | #define MALI_SFBD_FORMAT_MSAA_A (1 << 4) |
| 1367 | #define MALI_SFBD_FORMAT_MSAA_B (1 << 4) |
| 1368 | #define MALI_SFBD_FORMAT_SRGB (1 << 5) |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1369 | |
| 1370 | /* Fast/slow based on whether all three buffers are cleared at once */ |
| 1371 | |
| 1372 | #define MALI_CLEAR_FAST (1 << 18) |
| 1373 | #define MALI_CLEAR_SLOW (1 << 28) |
| 1374 | #define MALI_CLEAR_SLOW_STENCIL (1 << 31) |
| 1375 | |
Alyssa Rosenzweig | 31fc52a | 2019-07-10 07:22:19 -0700 | [diff] [blame] | 1376 | /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded |
| 1377 | * within the larget framebuffer descriptor). Analogous to |
| 1378 | * bifrost_tiler_heap_meta and bifrost_tiler_meta*/ |
| 1379 | |
Alyssa Rosenzweig | 897110a | 2019-08-19 14:47:50 -0700 | [diff] [blame] | 1380 | /* See pan_tiler.c for derivation */ |
| 1381 | #define MALI_HIERARCHY_MASK ((1 << 9) - 1) |
| 1382 | |
Alyssa Rosenzweig | 9fb0904 | 2019-11-27 08:31:16 -0500 | [diff] [blame] | 1383 | /* Flag disabling the tiler for clear-only jobs, with |
| 1384 | hierarchical tiling */ |
Alyssa Rosenzweig | 897110a | 2019-08-19 14:47:50 -0700 | [diff] [blame] | 1385 | #define MALI_TILER_DISABLED (1 << 12) |
| 1386 | |
Alyssa Rosenzweig | 9fb0904 | 2019-11-27 08:31:16 -0500 | [diff] [blame] | 1387 | /* Flag selecting userspace-generated polygon list, for clear-only jobs without |
| 1388 | * hierarhical tiling. */ |
| 1389 | #define MALI_TILER_USER 0xFFF |
| 1390 | |
| 1391 | /* Absent any geometry, the minimum size of the polygon list header */ |
| 1392 | #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200 |
| 1393 | |
Alyssa Rosenzweig | 31fc52a | 2019-07-10 07:22:19 -0700 | [diff] [blame] | 1394 | struct midgard_tiler_descriptor { |
| 1395 | /* Size of the entire polygon list; see pan_tiler.c for the |
| 1396 | * computation. It's based on hierarchical tiling */ |
| 1397 | |
| 1398 | u32 polygon_list_size; |
| 1399 | |
| 1400 | /* Name known from the replay workaround in the kernel. What exactly is |
| 1401 | * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff) |
| 1402 | * specifies a mask of hierarchy weights, which explains some of the |
| 1403 | * performance mysteries around setting it. We also see the bottom bit |
Alyssa Rosenzweig | 897110a | 2019-08-19 14:47:50 -0700 | [diff] [blame] | 1404 | * of tiler_flags set in the kernel, but no comment why. |
| 1405 | * |
| 1406 | * hierarchy_mask can have the TILER_DISABLED flag */ |
Alyssa Rosenzweig | 31fc52a | 2019-07-10 07:22:19 -0700 | [diff] [blame] | 1407 | |
| 1408 | u16 hierarchy_mask; |
| 1409 | u16 flags; |
| 1410 | |
| 1411 | /* See mali_tiler.c for an explanation */ |
| 1412 | mali_ptr polygon_list; |
| 1413 | mali_ptr polygon_list_body; |
| 1414 | |
| 1415 | /* Names based on we see symmetry with replay jobs which name these |
| 1416 | * explicitly */ |
| 1417 | |
| 1418 | mali_ptr heap_start; /* tiler heap_free_address */ |
| 1419 | mali_ptr heap_end; |
| 1420 | |
| 1421 | /* Hierarchy weights. We know these are weights based on the kernel, |
| 1422 | * but I've never seen them be anything other than zero */ |
| 1423 | u32 weights[8]; |
| 1424 | }; |
| 1425 | |
Tomeu Vizoso | 9447a84 | 2019-10-30 12:05:30 +0100 | [diff] [blame] | 1426 | enum mali_block_format { |
| 1427 | MALI_BLOCK_TILED = 0x0, |
| 1428 | MALI_BLOCK_UNKNOWN = 0x1, |
| 1429 | MALI_BLOCK_LINEAR = 0x2, |
| 1430 | MALI_BLOCK_AFBC = 0x3, |
| 1431 | }; |
| 1432 | |
| 1433 | struct mali_sfbd_format { |
| 1434 | /* 0x1 */ |
| 1435 | unsigned unk1 : 6; |
| 1436 | |
| 1437 | /* mali_channel_swizzle */ |
| 1438 | unsigned swizzle : 12; |
| 1439 | |
| 1440 | /* MALI_POSITIVE */ |
| 1441 | unsigned nr_channels : 2; |
| 1442 | |
| 1443 | /* 0x4 */ |
| 1444 | unsigned unk2 : 6; |
| 1445 | |
| 1446 | enum mali_block_format block : 2; |
| 1447 | |
| 1448 | /* 0xb */ |
| 1449 | unsigned unk3 : 4; |
| 1450 | }; |
| 1451 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1452 | struct mali_single_framebuffer { |
| 1453 | u32 unknown1; |
| 1454 | u32 unknown2; |
Alyssa Rosenzweig | 6c63727 | 2019-12-09 08:41:07 -0500 | [diff] [blame] | 1455 | mali_ptr scratchpad; |
| 1456 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1457 | u64 zero1; |
| 1458 | u64 zero0; |
| 1459 | |
Tomeu Vizoso | 9447a84 | 2019-10-30 12:05:30 +0100 | [diff] [blame] | 1460 | struct mali_sfbd_format format; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1461 | |
| 1462 | u32 clear_flags; |
| 1463 | u32 zero2; |
| 1464 | |
| 1465 | /* Purposeful off-by-one in these fields should be accounted for by the |
| 1466 | * MALI_DIMENSION macro */ |
| 1467 | |
| 1468 | u16 width; |
| 1469 | u16 height; |
| 1470 | |
Tomeu Vizoso | 23fe7cd | 2019-07-12 12:38:50 +0200 | [diff] [blame] | 1471 | u32 zero3[4]; |
| 1472 | mali_ptr checksum; |
| 1473 | u32 checksum_stride; |
| 1474 | u32 zero5; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1475 | |
| 1476 | /* By default, the framebuffer is upside down from OpenGL's |
| 1477 | * perspective. Set framebuffer to the end and negate the stride to |
| 1478 | * flip in the Y direction */ |
| 1479 | |
| 1480 | mali_ptr framebuffer; |
| 1481 | int32_t stride; |
| 1482 | |
| 1483 | u32 zero4; |
| 1484 | |
| 1485 | /* Depth and stencil buffers are interleaved, it appears, as they are |
| 1486 | * set to the same address in captures. Both fields set to zero if the |
| 1487 | * buffer is not being cleared. Depending on GL_ENABLE magic, you might |
| 1488 | * get a zero enable despite the buffer being present; that still is |
| 1489 | * disabled. */ |
| 1490 | |
| 1491 | mali_ptr depth_buffer; // not SAME_VA |
Tomeu Vizoso | 9447a84 | 2019-10-30 12:05:30 +0100 | [diff] [blame] | 1492 | u32 depth_stride_zero : 4; |
| 1493 | u32 depth_stride : 28; |
| 1494 | u32 zero7; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1495 | |
| 1496 | mali_ptr stencil_buffer; // not SAME_VA |
Tomeu Vizoso | 9447a84 | 2019-10-30 12:05:30 +0100 | [diff] [blame] | 1497 | u32 stencil_stride_zero : 4; |
| 1498 | u32 stencil_stride : 28; |
| 1499 | u32 zero8; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1500 | |
| 1501 | u32 clear_color_1; // RGBA8888 from glClear, actually used by hardware |
| 1502 | u32 clear_color_2; // always equal, but unclear function? |
| 1503 | u32 clear_color_3; // always equal, but unclear function? |
| 1504 | u32 clear_color_4; // always equal, but unclear function? |
| 1505 | |
| 1506 | /* Set to zero if not cleared */ |
| 1507 | |
| 1508 | float clear_depth_1; // float32, ditto |
| 1509 | float clear_depth_2; // float32, ditto |
| 1510 | float clear_depth_3; // float32, ditto |
| 1511 | float clear_depth_4; // float32, ditto |
| 1512 | |
| 1513 | u32 clear_stencil; // Exactly as it appears in OpenGL |
| 1514 | |
| 1515 | u32 zero6[7]; |
| 1516 | |
Alyssa Rosenzweig | 31fc52a | 2019-07-10 07:22:19 -0700 | [diff] [blame] | 1517 | struct midgard_tiler_descriptor tiler; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1518 | |
| 1519 | /* More below this, maybe */ |
| 1520 | } __attribute__((packed)); |
| 1521 | |
Alyssa Rosenzweig | 0aa5d89 | 2019-06-19 08:41:51 -0700 | [diff] [blame] | 1522 | /* On Midgard, this "framebuffer descriptor" is used for the framebuffer field |
| 1523 | * of compute jobs. Superficially resembles a single framebuffer descriptor */ |
| 1524 | |
| 1525 | struct mali_compute_fbd { |
Alyssa Rosenzweig | 1607954 | 2019-07-31 07:25:24 -0700 | [diff] [blame] | 1526 | u32 unknown1[8]; |
Alyssa Rosenzweig | 0aa5d89 | 2019-06-19 08:41:51 -0700 | [diff] [blame] | 1527 | } __attribute__((packed)); |
| 1528 | |
Alyssa Rosenzweig | f943047 | 2019-02-24 06:22:23 +0000 | [diff] [blame] | 1529 | /* Format bits for the render target flags */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1530 | |
Alyssa Rosenzweig | d507951 | 2019-06-17 15:53:09 -0700 | [diff] [blame] | 1531 | #define MALI_MFBD_FORMAT_MSAA (1 << 1) |
Alyssa Rosenzweig | 31a4ef8 | 2019-06-17 16:01:24 -0700 | [diff] [blame] | 1532 | #define MALI_MFBD_FORMAT_SRGB (1 << 2) |
Alyssa Rosenzweig | d507951 | 2019-06-17 15:53:09 -0700 | [diff] [blame] | 1533 | |
Alyssa Rosenzweig | f943047 | 2019-02-24 06:22:23 +0000 | [diff] [blame] | 1534 | struct mali_rt_format { |
| 1535 | unsigned unk1 : 32; |
| 1536 | unsigned unk2 : 3; |
| 1537 | |
| 1538 | unsigned nr_channels : 2; /* MALI_POSITIVE */ |
| 1539 | |
Alyssa Rosenzweig | d507951 | 2019-06-17 15:53:09 -0700 | [diff] [blame] | 1540 | unsigned unk3 : 5; |
Tomeu Vizoso | 9447a84 | 2019-10-30 12:05:30 +0100 | [diff] [blame] | 1541 | enum mali_block_format block : 2; |
Alyssa Rosenzweig | d507951 | 2019-06-17 15:53:09 -0700 | [diff] [blame] | 1542 | unsigned flags : 4; |
Alyssa Rosenzweig | f943047 | 2019-02-24 06:22:23 +0000 | [diff] [blame] | 1543 | |
| 1544 | unsigned swizzle : 12; |
| 1545 | |
Alyssa Rosenzweig | b78e04c | 2019-08-14 16:01:38 -0700 | [diff] [blame] | 1546 | unsigned zero : 3; |
| 1547 | |
| 1548 | /* Disables MFBD preload. When this bit is set, the render target will |
| 1549 | * be cleared every frame. When this bit is clear, the hardware will |
| 1550 | * automatically wallpaper the render target back from main memory. |
| 1551 | * Unfortunately, MFBD preload is very broken on Midgard, so in |
| 1552 | * practice, this is a chicken bit that should always be set. |
| 1553 | * Discovered by accident, as all good chicken bits are. */ |
| 1554 | |
| 1555 | unsigned no_preload : 1; |
Alyssa Rosenzweig | f943047 | 2019-02-24 06:22:23 +0000 | [diff] [blame] | 1556 | } __attribute__((packed)); |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1557 | |
| 1558 | struct bifrost_render_target { |
Alyssa Rosenzweig | f943047 | 2019-02-24 06:22:23 +0000 | [diff] [blame] | 1559 | struct mali_rt_format format; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1560 | |
| 1561 | u64 zero1; |
| 1562 | |
Alyssa Rosenzweig | c9b6233 | 2019-08-20 11:06:07 -0700 | [diff] [blame] | 1563 | struct { |
| 1564 | /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled, |
| 1565 | * there is an extra metadata buffer that contains 16 bytes per tile. |
| 1566 | * The framebuffer needs to be the same size as before, since we don't |
| 1567 | * know ahead of time how much space it will take up. The |
| 1568 | * framebuffer_stride is set to 0, since the data isn't stored linearly |
| 1569 | * anymore. |
| 1570 | * |
| 1571 | * When AFBC is disabled, these fields are zero. |
| 1572 | */ |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1573 | |
Alyssa Rosenzweig | c9b6233 | 2019-08-20 11:06:07 -0700 | [diff] [blame] | 1574 | mali_ptr metadata; |
| 1575 | u32 stride; // stride in units of tiles |
| 1576 | u32 unk; // = 0x20000 |
| 1577 | } afbc; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1578 | |
| 1579 | mali_ptr framebuffer; |
| 1580 | |
| 1581 | u32 zero2 : 4; |
| 1582 | u32 framebuffer_stride : 28; // in units of bytes |
| 1583 | u32 zero3; |
| 1584 | |
| 1585 | u32 clear_color_1; // RGBA8888 from glClear, actually used by hardware |
| 1586 | u32 clear_color_2; // always equal, but unclear function? |
| 1587 | u32 clear_color_3; // always equal, but unclear function? |
| 1588 | u32 clear_color_4; // always equal, but unclear function? |
| 1589 | } __attribute__((packed)); |
| 1590 | |
| 1591 | /* An optional part of bifrost_framebuffer. It comes between the main structure |
| 1592 | * and the array of render targets. It must be included if any of these are |
| 1593 | * enabled: |
| 1594 | * |
| 1595 | * - Transaction Elimination |
| 1596 | * - Depth/stencil |
| 1597 | * - TODO: Anything else? |
| 1598 | */ |
| 1599 | |
Alyssa Rosenzweig | 587ad37 | 2019-03-09 00:45:23 +0000 | [diff] [blame] | 1600 | /* Flags field: note, these are guesses */ |
| 1601 | |
| 1602 | #define MALI_EXTRA_PRESENT (0x400) |
| 1603 | #define MALI_EXTRA_AFBC (0x20) |
| 1604 | #define MALI_EXTRA_AFBC_ZS (0x10) |
| 1605 | #define MALI_EXTRA_ZS (0x4) |
| 1606 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1607 | struct bifrost_fb_extra { |
| 1608 | mali_ptr checksum; |
| 1609 | /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */ |
| 1610 | u32 checksum_stride; |
| 1611 | |
Alyssa Rosenzweig | 587ad37 | 2019-03-09 00:45:23 +0000 | [diff] [blame] | 1612 | u32 flags; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1613 | |
| 1614 | union { |
| 1615 | /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */ |
| 1616 | struct { |
| 1617 | mali_ptr depth_stencil_afbc_metadata; |
| 1618 | u32 depth_stencil_afbc_stride; // in units of tiles |
| 1619 | u32 zero1; |
| 1620 | |
| 1621 | mali_ptr depth_stencil; |
| 1622 | |
| 1623 | u64 padding; |
| 1624 | } ds_afbc; |
| 1625 | |
| 1626 | struct { |
| 1627 | /* Depth becomes depth/stencil in case of combined D/S */ |
| 1628 | mali_ptr depth; |
| 1629 | u32 depth_stride_zero : 4; |
| 1630 | u32 depth_stride : 28; |
| 1631 | u32 zero1; |
| 1632 | |
| 1633 | mali_ptr stencil; |
| 1634 | u32 stencil_stride_zero : 4; |
| 1635 | u32 stencil_stride : 28; |
| 1636 | u32 zero2; |
| 1637 | } ds_linear; |
| 1638 | }; |
| 1639 | |
| 1640 | |
| 1641 | u64 zero3, zero4; |
| 1642 | } __attribute__((packed)); |
| 1643 | |
Alyssa Rosenzweig | ac68946 | 2019-06-14 11:14:01 -0700 | [diff] [blame] | 1644 | /* Flags for mfbd_flags */ |
Alyssa Rosenzweig | e57ea53 | 2019-03-09 00:12:07 +0000 | [diff] [blame] | 1645 | |
| 1646 | /* Enables writing depth results back to main memory (rather than keeping them |
| 1647 | * on-chip in the tile buffer and then discarding) */ |
| 1648 | |
| 1649 | #define MALI_MFBD_DEPTH_WRITE (1 << 10) |
| 1650 | |
| 1651 | /* The MFBD contains the extra bifrost_fb_extra section */ |
| 1652 | |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1653 | #define MALI_MFBD_EXTRA (1 << 13) |
| 1654 | |
| 1655 | struct bifrost_framebuffer { |
Alyssa Rosenzweig | e6f8ef9 | 2019-12-09 08:41:33 -0500 | [diff] [blame] | 1656 | u32 stack_shift : 4; |
| 1657 | u32 unk0 : 28; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1658 | |
| 1659 | u32 unknown2; // = 0x1f, same as SFBD |
| 1660 | mali_ptr scratchpad; |
| 1661 | |
| 1662 | /* 0x10 */ |
| 1663 | mali_ptr sample_locations; |
| 1664 | mali_ptr unknown1; |
| 1665 | /* 0x20 */ |
| 1666 | u16 width1, height1; |
| 1667 | u32 zero3; |
| 1668 | u16 width2, height2; |
| 1669 | u32 unk1 : 19; // = 0x01000 |
| 1670 | u32 rt_count_1 : 2; // off-by-one (use MALI_POSITIVE) |
| 1671 | u32 unk2 : 3; // = 0 |
| 1672 | u32 rt_count_2 : 3; // no off-by-one |
| 1673 | u32 zero4 : 5; |
| 1674 | /* 0x30 */ |
| 1675 | u32 clear_stencil : 8; |
Alyssa Rosenzweig | ac68946 | 2019-06-14 11:14:01 -0700 | [diff] [blame] | 1676 | u32 mfbd_flags : 24; // = 0x100 |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1677 | float clear_depth; |
Alyssa Rosenzweig | 85e745f | 2019-06-12 09:33:06 -0700 | [diff] [blame] | 1678 | |
Alyssa Rosenzweig | 31fc52a | 2019-07-10 07:22:19 -0700 | [diff] [blame] | 1679 | struct midgard_tiler_descriptor tiler; |
Alyssa Rosenzweig | 61d3ae6 | 2019-01-29 05:46:07 +0000 | [diff] [blame] | 1680 | |
| 1681 | /* optional: struct bifrost_fb_extra extra */ |
| 1682 | /* struct bifrost_render_target rts[] */ |
| 1683 | } __attribute__((packed)); |
| 1684 | |
| 1685 | #endif /* __PANFROST_JOB_H__ */ |