blob: a120f3dd849cf7f0b5707fa9449b7a2aebe9ab91 [file] [log] [blame]
Niklas Schulze878fed42017-02-08 15:29:21 +01001/*
2 * Copyright 2017 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7#ifdef DRV_VC4
8
9#include <stdio.h>
10#include <string.h>
11#include <sys/mman.h>
12#include <vc4_drm.h>
13#include <xf86drm.h>
14
15#include "drv_priv.h"
16#include "helpers.h"
17#include "util.h"
18
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080019static const uint32_t supported_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
20 DRM_FORMAT_XRGB8888 };
Niklas Schulze878fed42017-02-08 15:29:21 +010021
22static int vc4_init(struct driver *drv)
23{
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080024 return drv_add_linear_combinations(drv, supported_formats, ARRAY_SIZE(supported_formats));
Niklas Schulze878fed42017-02-08 15:29:21 +010025}
26
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080027static int vc4_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
28 uint32_t flags)
Niklas Schulze878fed42017-02-08 15:29:21 +010029{
30 int ret;
31 size_t plane;
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070032 uint32_t stride;
Niklas Schulze878fed42017-02-08 15:29:21 +010033 struct drm_vc4_create_bo bo_create;
34
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070035 /*
36 * Since the ARM L1 cache line size is 64 bytes, align to that as a
37 * performance optimization.
38 */
39 stride = drv_stride_from_format(format, width, 0);
40 stride = ALIGN(stride, 64);
41 drv_bo_from_format(bo, stride, height, format);
Niklas Schulze878fed42017-02-08 15:29:21 +010042
43 memset(&bo_create, 0, sizeof(bo_create));
44 bo_create.size = bo->total_size;
45
46 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VC4_CREATE_BO, &bo_create);
47 if (ret) {
Gurchetan Singh085bff12017-03-20 13:05:49 -070048 fprintf(stderr, "drv: DRM_IOCTL_VC4_GEM_CREATE failed (size=%zu)\n",
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080049 bo->total_size);
Niklas Schulze878fed42017-02-08 15:29:21 +010050 return ret;
51 }
52
53 for (plane = 0; plane < bo->num_planes; plane++)
54 bo->handles[plane].u32 = bo_create.handle;
55
56 return 0;
57}
58
59static void *vc4_bo_map(struct bo *bo, struct map_info *data, size_t plane)
60{
61 int ret;
62 struct drm_vc4_mmap_bo bo_map;
63
64 memset(&bo_map, 0, sizeof(bo_map));
65 bo_map.handle = bo->handles[0].u32;
66
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080067 ret = drmCommandWriteRead(bo->drv->fd, DRM_VC4_MMAP_BO, &bo_map, sizeof(bo_map));
Niklas Schulze878fed42017-02-08 15:29:21 +010068 if (ret) {
69 fprintf(stderr, "drv: DRM_VC4_MMAP_BO failed\n");
70 return MAP_FAILED;
71 }
72
73 data->length = bo->total_size;
74
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080075 return mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->drv->fd,
76 bo_map.offset);
Niklas Schulze878fed42017-02-08 15:29:21 +010077}
78
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080079struct backend backend_vc4 = {
Niklas Schulze878fed42017-02-08 15:29:21 +010080 .name = "vc4",
81 .init = vc4_init,
82 .bo_create = vc4_bo_create,
83 .bo_import = drv_prime_bo_import,
84 .bo_destroy = drv_gem_bo_destroy,
85 .bo_map = vc4_bo_map,
86};
87
88#endif