blob: ab59e9a5b87cd513716039070e2beb94ac8bedf8 [file] [log] [blame]
JB Tsai0c16a0f2015-03-19 14:30:31 +08001/*
2 * Copyright 2015 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Gurchetan Singh46faf6b2016-08-05 14:40:07 -07007#ifdef DRV_MEDIATEK
JB Tsai0c16a0f2015-03-19 14:30:31 +08008
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -07009#include <stdio.h>
JB Tsai0c16a0f2015-03-19 14:30:31 +080010#include <string.h>
Gurchetan Singhef920532016-08-12 16:38:25 -070011#include <sys/mman.h>
JB Tsai0c16a0f2015-03-19 14:30:31 +080012#include <xf86drm.h>
13#include <mediatek_drm.h>
Gurchetan Singhef920532016-08-12 16:38:25 -070014
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070015#include "drv_priv.h"
JB Tsai0c16a0f2015-03-19 14:30:31 +080016#include "helpers.h"
Gurchetan Singh179687e2016-10-28 10:07:35 -070017#include "util.h"
18
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080019static const uint32_t supported_formats[] = {
20 DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
Gurchetan Singh03f13562017-02-08 15:21:14 -080021 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, DRM_FORMAT_YVU420,
22 DRM_FORMAT_YVU420_ANDROID
Gurchetan Singh179687e2016-10-28 10:07:35 -070023};
24
25static int mediatek_init(struct driver *drv)
26{
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080027 return drv_add_linear_combinations(drv, supported_formats,
28 ARRAY_SIZE(supported_formats));
Gurchetan Singh179687e2016-10-28 10:07:35 -070029}
JB Tsai0c16a0f2015-03-19 14:30:31 +080030
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -070031static int mediatek_bo_create(struct bo *bo, uint32_t width, uint32_t height,
32 uint32_t format, uint32_t flags)
JB Tsai0c16a0f2015-03-19 14:30:31 +080033{
JB Tsai0c16a0f2015-03-19 14:30:31 +080034 int ret;
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070035 size_t plane;
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070036 uint32_t stride;
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070037 struct drm_mtk_gem_create gem_create;
JB Tsai0c16a0f2015-03-19 14:30:31 +080038
Gurchetan Singh6ea14ba2017-02-08 15:09:13 -080039 /*
40 * Since the ARM L1 cache line size is 64 bytes, align to that as a
41 * performance optimization.
42 */
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070043 stride = drv_stride_from_format(format, width, 0);
44 stride = ALIGN(stride, 64);
45 drv_bo_from_format(bo, stride, height, format);
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050046
JB Tsai0c16a0f2015-03-19 14:30:31 +080047 memset(&gem_create, 0, sizeof(gem_create));
Gurchetan Singha40ca9e2016-08-29 19:51:45 -070048 gem_create.size = bo->total_size;
JB Tsai0c16a0f2015-03-19 14:30:31 +080049
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070050 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MTK_GEM_CREATE, &gem_create);
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -070051 if (ret) {
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070052 fprintf(stderr, "drv: DRM_IOCTL_MTK_GEM_CREATE failed "
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070053 "(size=%llu)\n", gem_create.size);
JB Tsai0c16a0f2015-03-19 14:30:31 +080054 return ret;
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -070055 }
JB Tsai0c16a0f2015-03-19 14:30:31 +080056
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070057 for (plane = 0; plane < bo->num_planes; plane++)
58 bo->handles[plane].u32 = gem_create.handle;
JB Tsai0c16a0f2015-03-19 14:30:31 +080059
60 return 0;
61}
62
Gurchetan Singh1a31e602016-10-06 10:58:00 -070063static void *mediatek_bo_map(struct bo *bo, struct map_info *data, size_t plane)
Gurchetan Singhef920532016-08-12 16:38:25 -070064{
65 int ret;
66 struct drm_mtk_gem_map_off gem_map;
67
68 memset(&gem_map, 0, sizeof(gem_map));
69 gem_map.handle = bo->handles[0].u32;
70
71 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MTK_GEM_MAP_OFFSET, &gem_map);
72 if (ret) {
73 fprintf(stderr,"drv: DRM_IOCTL_MTK_GEM_MAP_OFFSET failed\n");
74 return MAP_FAILED;
75 }
76
Gurchetan Singh1a31e602016-10-06 10:58:00 -070077 data->length = bo->total_size;
78
Gurchetan Singha40ca9e2016-08-29 19:51:45 -070079 return mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED,
Gurchetan Singhef920532016-08-12 16:38:25 -070080 bo->drv->fd, gem_map.offset);
81}
82
Gurchetan Singhf3b22da2016-11-21 10:46:38 -080083static uint32_t mediatek_resolve_format(uint32_t format)
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070084{
85 switch (format) {
Gurchetan Singhf3b22da2016-11-21 10:46:38 -080086 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070087 /*HACK: See b/28671744 */
Gurchetan Singhf3b22da2016-11-21 10:46:38 -080088 return DRM_FORMAT_XBGR8888;
89 case DRM_FORMAT_FLEX_YCbCr_420_888:
Gurchetan Singh03f13562017-02-08 15:21:14 -080090 return DRM_FORMAT_YVU420_ANDROID;
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070091 default:
92 return format;
93 }
94}
95
Gurchetan Singh179687e2016-10-28 10:07:35 -070096struct backend backend_mediatek =
JB Tsai0c16a0f2015-03-19 14:30:31 +080097{
98 .name = "mediatek",
Gurchetan Singh179687e2016-10-28 10:07:35 -070099 .init = mediatek_init,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700100 .bo_create = mediatek_bo_create,
Gurchetan Singh46faf6b2016-08-05 14:40:07 -0700101 .bo_destroy = drv_gem_bo_destroy,
Gurchetan Singh71611d62017-01-03 16:49:56 -0800102 .bo_import = drv_prime_bo_import,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700103 .bo_map = mediatek_bo_map,
Gurchetan Singh42cc6d62016-08-29 18:19:19 -0700104 .resolve_format = mediatek_resolve_format,
JB Tsai0c16a0f2015-03-19 14:30:31 +0800105};
106
107#endif