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Zach Reizner85c4c5f2017-10-04 13:15:57 -07001/*
2 * Copyright 2017 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Zach Reizner85c4c5f2017-10-04 13:15:57 -07007#include <errno.h>
8#include <stdint.h>
9#include <stdio.h>
10#include <string.h>
11#include <sys/mman.h>
12#include <virtgpu_drm.h>
13#include <xf86drm.h>
14
15#include "drv_priv.h"
16#include "helpers.h"
17#include "util.h"
18#include "virgl_hw.h"
19
Tao Wu33815882018-03-12 18:07:43 -070020#ifndef PAGE_SIZE
Zach Reizner85c4c5f2017-10-04 13:15:57 -070021#define PAGE_SIZE 0x1000
Tao Wu33815882018-03-12 18:07:43 -070022#endif
Zach Reizner85c4c5f2017-10-04 13:15:57 -070023#define PIPE_TEXTURE_2D 2
24
Lepton Wu249e8632018-04-05 12:50:03 -070025#define MESA_LLVMPIPE_TILE_ORDER 6
26#define MESA_LLVMPIPE_TILE_SIZE (1 << MESA_LLVMPIPE_TILE_ORDER)
27
Zach Reizner85c4c5f2017-10-04 13:15:57 -070028static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
Gurchetan Singh71bc6652018-09-17 17:42:05 -070029 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
30 DRM_FORMAT_XRGB8888 };
Zach Reizner85c4c5f2017-10-04 13:15:57 -070031
Lepton Wu249e8632018-04-05 12:50:03 -070032static const uint32_t dumb_texture_source_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_YVU420,
Gurchetan Singh3f3e5f92019-07-08 09:50:01 -070033 DRM_FORMAT_YVU420_ANDROID };
Lepton Wu249e8632018-04-05 12:50:03 -070034
Gurchetan Singhf5d280d2019-06-04 19:43:41 -070035static const uint32_t texture_source_formats[] = { DRM_FORMAT_NV12, DRM_FORMAT_R8, DRM_FORMAT_RG88,
36 DRM_FORMAT_YVU420_ANDROID };
Zach Reizner85c4c5f2017-10-04 13:15:57 -070037
Lepton Wu249e8632018-04-05 12:50:03 -070038struct virtio_gpu_priv {
39 int has_3d;
40};
41
Zach Reizner85c4c5f2017-10-04 13:15:57 -070042static uint32_t translate_format(uint32_t drm_fourcc, uint32_t plane)
43{
44 switch (drm_fourcc) {
45 case DRM_FORMAT_XRGB8888:
46 return VIRGL_FORMAT_B8G8R8X8_UNORM;
47 case DRM_FORMAT_ARGB8888:
48 return VIRGL_FORMAT_B8G8R8A8_UNORM;
49 case DRM_FORMAT_XBGR8888:
50 return VIRGL_FORMAT_R8G8B8X8_UNORM;
51 case DRM_FORMAT_ABGR8888:
52 return VIRGL_FORMAT_R8G8B8A8_UNORM;
53 case DRM_FORMAT_RGB565:
54 return VIRGL_FORMAT_B5G6R5_UNORM;
55 case DRM_FORMAT_R8:
56 return VIRGL_FORMAT_R8_UNORM;
57 case DRM_FORMAT_RG88:
58 return VIRGL_FORMAT_R8G8_UNORM;
Gurchetan Singhf5d280d2019-06-04 19:43:41 -070059 case DRM_FORMAT_NV12:
60 return VIRGL_FORMAT_NV12;
61 case DRM_FORMAT_YVU420:
62 case DRM_FORMAT_YVU420_ANDROID:
63 return VIRGL_FORMAT_YV12;
Zach Reizner85c4c5f2017-10-04 13:15:57 -070064 default:
65 return 0;
66 }
67}
68
Lepton Wu249e8632018-04-05 12:50:03 -070069static int virtio_dumb_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
70 uint64_t use_flags)
Zach Reizner85c4c5f2017-10-04 13:15:57 -070071{
Keiichi Watanabea13dda72018-08-02 22:45:05 +090072 if (bo->format != DRM_FORMAT_R8) {
73 width = ALIGN(width, MESA_LLVMPIPE_TILE_SIZE);
74 height = ALIGN(height, MESA_LLVMPIPE_TILE_SIZE);
75 }
Zach Reizner85c4c5f2017-10-04 13:15:57 -070076
Lepton Wu249e8632018-04-05 12:50:03 -070077 return drv_dumb_bo_create(bo, width, height, format, use_flags);
Zach Reizner85c4c5f2017-10-04 13:15:57 -070078}
79
Lepton Wudbab0832019-04-19 12:26:39 -070080static inline void handle_flag(uint64_t *flag, uint64_t check_flag, uint32_t *bind,
81 uint32_t virgl_bind)
82{
83 if ((*flag) & check_flag) {
84 (*flag) &= ~check_flag;
85 (*bind) |= virgl_bind;
86 }
87}
88
89static uint32_t use_flags_to_bind(uint64_t use_flags)
90{
91 uint32_t bind = 0;
92
93 handle_flag(&use_flags, BO_USE_TEXTURE, &bind, VIRGL_BIND_SAMPLER_VIEW);
94 handle_flag(&use_flags, BO_USE_RENDERING, &bind, VIRGL_BIND_RENDER_TARGET);
95 handle_flag(&use_flags, BO_USE_SCANOUT, &bind, VIRGL_BIND_SCANOUT);
96 // TODO (b/12983436): handle other use flags.
97 if (use_flags) {
98 drv_log("Unhandled bo use flag: %llx\n", (unsigned long long)use_flags);
99 }
100 return bind;
101}
102
Lepton Wu249e8632018-04-05 12:50:03 -0700103static int virtio_virgl_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
104 uint64_t use_flags)
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700105{
106 int ret;
107 ssize_t plane;
108 ssize_t num_planes = drv_num_planes_from_format(format);
109 uint32_t stride0;
Lepton Wudbab0832019-04-19 12:26:39 -0700110 uint32_t bind = use_flags_to_bind(use_flags);
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700111
112 for (plane = 0; plane < num_planes; plane++) {
113 uint32_t stride = drv_stride_from_format(format, width, plane);
114 uint32_t size = drv_size_from_format(format, stride, height, plane);
115 uint32_t res_format = translate_format(format, plane);
116 struct drm_virtgpu_resource_create res_create;
117
118 memset(&res_create, 0, sizeof(res_create));
119 size = ALIGN(size, PAGE_SIZE);
120 /*
121 * Setting the target is intended to ensure this resource gets bound as a 2D
122 * texture in the host renderer's GL state. All of these resource properties are
123 * sent unchanged by the kernel to the host, which in turn sends them unchanged to
124 * virglrenderer. When virglrenderer makes a resource, it will convert the target
125 * enum to the equivalent one in GL and then bind the resource to that target.
126 */
127 res_create.target = PIPE_TEXTURE_2D;
128 res_create.format = res_format;
Lepton Wudbab0832019-04-19 12:26:39 -0700129 res_create.bind = bind;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700130 res_create.width = width;
131 res_create.height = height;
132 res_create.depth = 1;
133 res_create.array_size = 1;
134 res_create.last_level = 0;
135 res_create.nr_samples = 0;
136 res_create.stride = stride;
137 res_create.size = size;
138
139 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_CREATE, &res_create);
140 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700141 drv_log("DRM_IOCTL_VIRTGPU_RESOURCE_CREATE failed with %s\n",
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700142 strerror(errno));
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -0700143 ret = -errno;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700144 goto fail;
145 }
146
147 bo->handles[plane].u32 = res_create.bo_handle;
148 }
149
150 stride0 = drv_stride_from_format(format, width, 0);
151 drv_bo_from_format(bo, stride0, height, format);
152
153 for (plane = 0; plane < num_planes; plane++)
154 bo->offsets[plane] = 0;
155
156 return 0;
157
158fail:
159 for (plane--; plane >= 0; plane--) {
160 struct drm_gem_close gem_close;
161 memset(&gem_close, 0, sizeof(gem_close));
162 gem_close.handle = bo->handles[plane].u32;
163 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
164 }
165
166 return ret;
167}
168
Lepton Wu249e8632018-04-05 12:50:03 -0700169static void *virtio_virgl_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700170{
171 int ret;
172 struct drm_virtgpu_map gem_map;
173
174 memset(&gem_map, 0, sizeof(gem_map));
175 gem_map.handle = bo->handles[0].u32;
176
177 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_MAP, &gem_map);
178 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700179 drv_log("DRM_IOCTL_VIRTGPU_MAP failed with %s\n", strerror(errno));
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700180 return MAP_FAILED;
181 }
182
Tao Wu33815882018-03-12 18:07:43 -0700183 vma->length = bo->total_size;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700184 return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
185 gem_map.offset);
186}
187
Lepton Wu249e8632018-04-05 12:50:03 -0700188static int virtio_gpu_init(struct driver *drv)
189{
190 int ret;
191 struct virtio_gpu_priv *priv;
192 struct drm_virtgpu_getparam args;
193
194 priv = calloc(1, sizeof(*priv));
195 drv->priv = priv;
196
197 memset(&args, 0, sizeof(args));
198 args.param = VIRTGPU_PARAM_3D_FEATURES;
199 args.value = (uint64_t)(uintptr_t)&priv->has_3d;
200 ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GETPARAM, &args);
201 if (ret) {
202 drv_log("virtio 3D acceleration is not available\n");
203 /* Be paranoid */
204 priv->has_3d = 0;
205 }
206
Lepton Wudbab0832019-04-19 12:26:39 -0700207 /* This doesn't mean host can scanout everything, it just means host
208 * hypervisor can show it. */
Lepton Wu249e8632018-04-05 12:50:03 -0700209 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
Lepton Wudbab0832019-04-19 12:26:39 -0700210 &LINEAR_METADATA, BO_USE_RENDER_MASK | BO_USE_SCANOUT);
Lepton Wu249e8632018-04-05 12:50:03 -0700211
Gurchetan Singh3f3e5f92019-07-08 09:50:01 -0700212 if (priv->has_3d) {
Lepton Wu249e8632018-04-05 12:50:03 -0700213 drv_add_combinations(drv, texture_source_formats,
214 ARRAY_SIZE(texture_source_formats), &LINEAR_METADATA,
215 BO_USE_TEXTURE_MASK);
Gurchetan Singh3f3e5f92019-07-08 09:50:01 -0700216 } else {
Lepton Wu249e8632018-04-05 12:50:03 -0700217 drv_add_combinations(drv, dumb_texture_source_formats,
218 ARRAY_SIZE(dumb_texture_source_formats), &LINEAR_METADATA,
219 BO_USE_TEXTURE_MASK);
Gurchetan Singh3f3e5f92019-07-08 09:50:01 -0700220 drv_add_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
221 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SW_MASK |
222 BO_USE_LINEAR);
223 }
Lepton Wu249e8632018-04-05 12:50:03 -0700224
Gurchetan Singh71bc6652018-09-17 17:42:05 -0700225 /* Android CTS tests require this. */
226 drv_add_combination(drv, DRM_FORMAT_BGR888, &LINEAR_METADATA, BO_USE_SW_MASK);
227
Keiichi Watanabea13dda72018-08-02 22:45:05 +0900228 drv_modify_combination(drv, DRM_FORMAT_R8, &LINEAR_METADATA,
229 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
230
Lepton Wu249e8632018-04-05 12:50:03 -0700231 return drv_modify_linear_combinations(drv);
232}
233
234static void virtio_gpu_close(struct driver *drv)
235{
236 free(drv->priv);
237 drv->priv = NULL;
238}
239
240static int virtio_gpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
241 uint64_t use_flags)
242{
243 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
244 if (priv->has_3d)
245 return virtio_virgl_bo_create(bo, width, height, format, use_flags);
246 else
247 return virtio_dumb_bo_create(bo, width, height, format, use_flags);
248}
249
250static int virtio_gpu_bo_destroy(struct bo *bo)
251{
252 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
253 if (priv->has_3d)
254 return drv_gem_bo_destroy(bo);
255 else
256 return drv_dumb_bo_destroy(bo);
257}
258
259static void *virtio_gpu_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
260{
261 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
262 if (priv->has_3d)
263 return virtio_virgl_bo_map(bo, vma, plane, map_flags);
264 else
265 return drv_dumb_bo_map(bo, vma, plane, map_flags);
266}
267
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700268static int virtio_gpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
269{
270 int ret;
271 struct drm_virtgpu_3d_transfer_from_host xfer;
Lepton Wu249e8632018-04-05 12:50:03 -0700272 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
273
274 if (!priv->has_3d)
275 return 0;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700276
277 memset(&xfer, 0, sizeof(xfer));
278 xfer.bo_handle = mapping->vma->handle;
279 xfer.box.x = mapping->rect.x;
280 xfer.box.y = mapping->rect.y;
281 xfer.box.w = mapping->rect.width;
282 xfer.box.h = mapping->rect.height;
283 xfer.box.d = 1;
284
285 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST, &xfer);
286 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700287 drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST failed with %s\n", strerror(errno));
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -0700288 return -errno;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700289 }
290
291 return 0;
292}
293
294static int virtio_gpu_bo_flush(struct bo *bo, struct mapping *mapping)
295{
296 int ret;
297 struct drm_virtgpu_3d_transfer_to_host xfer;
Lepton Wu249e8632018-04-05 12:50:03 -0700298 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
299
300 if (!priv->has_3d)
301 return 0;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700302
303 if (!(mapping->vma->map_flags & BO_MAP_WRITE))
304 return 0;
305
306 memset(&xfer, 0, sizeof(xfer));
307 xfer.bo_handle = mapping->vma->handle;
308 xfer.box.x = mapping->rect.x;
309 xfer.box.y = mapping->rect.y;
310 xfer.box.w = mapping->rect.width;
311 xfer.box.h = mapping->rect.height;
312 xfer.box.d = 1;
313
314 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST, &xfer);
315 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700316 drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST failed with %s\n", strerror(errno));
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -0700317 return -errno;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700318 }
319
320 return 0;
321}
322
Gurchetan Singh0d44d482019-06-04 19:39:51 -0700323static uint32_t virtio_gpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700324{
Gurchetan Singhf5d280d2019-06-04 19:43:41 -0700325 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
326
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700327 switch (format) {
328 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
Keiichi Watanabea13dda72018-08-02 22:45:05 +0900329 /* Camera subsystem requires NV12. */
330 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
331 return DRM_FORMAT_NV12;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700332 /*HACK: See b/28671744 */
333 return DRM_FORMAT_XBGR8888;
Lepton Wu249e8632018-04-05 12:50:03 -0700334 case DRM_FORMAT_FLEX_YCbCr_420_888:
Gurchetan Singhf5d280d2019-06-04 19:43:41 -0700335 /*
336 * All of our host drivers prefer NV12 as their flexible media format.
337 * If that changes, this will need to be modified.
338 */
339 if (priv->has_3d)
340 return DRM_FORMAT_NV12;
341 else
342 return DRM_FORMAT_YVU420;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700343 default:
344 return format;
345 }
346}
347
Lepton Wu249e8632018-04-05 12:50:03 -0700348const struct backend backend_virtio_gpu = {
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700349 .name = "virtio_gpu",
350 .init = virtio_gpu_init,
Lepton Wu249e8632018-04-05 12:50:03 -0700351 .close = virtio_gpu_close,
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700352 .bo_create = virtio_gpu_bo_create,
Lepton Wu249e8632018-04-05 12:50:03 -0700353 .bo_destroy = virtio_gpu_bo_destroy,
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700354 .bo_import = drv_prime_bo_import,
Lepton Wu249e8632018-04-05 12:50:03 -0700355 .bo_map = virtio_gpu_bo_map,
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700356 .bo_unmap = drv_bo_munmap,
357 .bo_invalidate = virtio_gpu_bo_invalidate,
358 .bo_flush = virtio_gpu_bo_flush,
359 .resolve_format = virtio_gpu_resolve_format,
360};