Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 1 | /* |
Daniele Castagna | 7a755de | 2016-12-16 17:32:30 -0500 | [diff] [blame] | 2 | * Copyright 2016 The Chromium OS Authors. All rights reserved. |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 3 | * Use of this source code is governed by a BSD-style license that can be |
| 4 | * found in the LICENSE file. |
| 5 | */ |
| 6 | #ifdef DRV_AMDGPU |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 7 | #include <amdgpu.h> |
| 8 | #include <amdgpu_drm.h> |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 9 | #include <errno.h> |
| 10 | #include <stdio.h> |
| 11 | #include <stdlib.h> |
| 12 | #include <string.h> |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 13 | #include <sys/mman.h> |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 14 | #include <xf86drm.h> |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 15 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 16 | #include "dri.h" |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 17 | #include "drv_priv.h" |
| 18 | #include "helpers.h" |
| 19 | #include "util.h" |
| 20 | |
Gurchetan Singh | cf9ed9d | 2019-12-13 09:37:01 -0800 | [diff] [blame] | 21 | // clang-format off |
| 22 | #define DRI_PATH STRINGIZE(DRI_DRIVER_DIR/radeonsi_dri.so) |
| 23 | // clang-format on |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 24 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 25 | #define TILE_TYPE_LINEAR 0 |
| 26 | /* DRI backend decides tiling in this case. */ |
| 27 | #define TILE_TYPE_DRI 1 |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 28 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 29 | struct amdgpu_priv { |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 30 | struct dri_driver dri; |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 31 | int drm_version; |
| 32 | }; |
| 33 | |
Gurchetan Singh | 767c538 | 2018-05-05 00:42:12 +0000 | [diff] [blame] | 34 | const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, |
Drew Davenport | 293d9e3 | 2018-06-20 15:46:50 -0600 | [diff] [blame] | 35 | DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888, |
| 36 | DRM_FORMAT_XRGB8888 }; |
Gurchetan Singh | 179687e | 2016-10-28 10:07:35 -0700 | [diff] [blame] | 37 | |
Gurchetan Singh | 8d88474 | 2020-03-24 13:48:54 -0700 | [diff] [blame] | 38 | const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, |
| 39 | DRM_FORMAT_NV21, DRM_FORMAT_NV12, |
Hirokazu Honda | 3b8d4d0 | 2019-07-31 16:35:52 +0900 | [diff] [blame] | 40 | DRM_FORMAT_YVU420_ANDROID, DRM_FORMAT_YVU420 }; |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 41 | |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 42 | static int amdgpu_init(struct driver *drv) |
| 43 | { |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 44 | struct amdgpu_priv *priv; |
| 45 | drmVersionPtr drm_version; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 46 | struct format_metadata metadata; |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 47 | uint64_t use_flags = BO_USE_RENDER_MASK; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 48 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 49 | priv = calloc(1, sizeof(struct amdgpu_priv)); |
| 50 | if (!priv) |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 51 | return -ENOMEM; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 52 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 53 | drm_version = drmGetVersion(drv_get_fd(drv)); |
| 54 | if (!drm_version) { |
| 55 | free(priv); |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 56 | return -ENODEV; |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | priv->drm_version = drm_version->version_minor; |
| 60 | drmFreeVersion(drm_version); |
| 61 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 62 | drv->priv = priv; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 63 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 64 | if (dri_init(drv, DRI_PATH, "radeonsi")) { |
| 65 | free(priv); |
| 66 | drv->priv = NULL; |
| 67 | return -ENODEV; |
| 68 | } |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 69 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 70 | metadata.tiling = TILE_TYPE_LINEAR; |
| 71 | metadata.priority = 1; |
Kristian H. Kristensen | bc8c593 | 2017-10-24 18:36:32 -0700 | [diff] [blame] | 72 | metadata.modifier = DRM_FORMAT_MOD_LINEAR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 73 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 74 | drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 75 | &metadata, use_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 76 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 77 | drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats), |
| 78 | &metadata, BO_USE_TEXTURE_MASK); |
| 79 | |
Hirokazu Honda | 3b8d4d0 | 2019-07-31 16:35:52 +0900 | [diff] [blame] | 80 | /* |
| 81 | * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the |
| 82 | * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future. |
| 83 | */ |
| 84 | drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER); |
| 85 | drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, BO_USE_HW_VIDEO_ENCODER); |
| 86 | |
Gurchetan Singh | 71bc665 | 2018-09-17 17:42:05 -0700 | [diff] [blame] | 87 | /* Android CTS tests require this. */ |
| 88 | drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK); |
| 89 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 90 | /* Linear formats supported by display. */ |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 91 | drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
| 92 | drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
Drew Davenport | 5d21524 | 2019-03-25 09:18:42 -0600 | [diff] [blame] | 93 | drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 94 | drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 95 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 96 | /* YUV formats for camera and display. */ |
| 97 | drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, |
Miguel Casas | dea0ccb | 2018-07-02 09:40:25 -0400 | [diff] [blame] | 98 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT | |
| 99 | BO_USE_HW_VIDEO_DECODER); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 100 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 101 | drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 102 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 103 | /* |
| 104 | * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots |
| 105 | * from camera. |
| 106 | */ |
| 107 | drv_modify_combination(drv, DRM_FORMAT_R8, &metadata, |
| 108 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); |
| 109 | |
| 110 | /* |
| 111 | * The following formats will be allocated by the DRI backend and may be potentially tiled. |
| 112 | * Since format modifier support hasn't been implemented fully yet, it's not |
| 113 | * possible to enumerate the different types of buffers (like i915 can). |
| 114 | */ |
| 115 | use_flags &= ~BO_USE_RENDERSCRIPT; |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 116 | use_flags &= ~BO_USE_SW_WRITE_OFTEN; |
| 117 | use_flags &= ~BO_USE_SW_READ_OFTEN; |
| 118 | use_flags &= ~BO_USE_LINEAR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 119 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 120 | metadata.tiling = TILE_TYPE_DRI; |
| 121 | metadata.priority = 2; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 122 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 123 | drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 124 | &metadata, use_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 125 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 126 | /* Potentially tiled formats supported by display. */ |
| 127 | drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
| 128 | drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
Bas Nieuwenhuizen | 582bdbf | 2019-04-03 18:12:12 +0200 | [diff] [blame] | 129 | drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 130 | drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 131 | return 0; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | static void amdgpu_close(struct driver *drv) |
| 135 | { |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 136 | dri_close(drv); |
| 137 | free(drv->priv); |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 138 | drv->priv = NULL; |
| 139 | } |
| 140 | |
ChromeOS Developer | 9b367b3 | 2020-03-02 13:08:53 +0100 | [diff] [blame] | 141 | static int amdgpu_create_bo_linear(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, |
| 142 | uint64_t use_flags) |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 143 | { |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 144 | int ret; |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 145 | uint32_t plane, stride; |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 146 | union drm_amdgpu_gem_create gem_create; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 147 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 148 | stride = drv_stride_from_format(format, width, 0); |
Keiichi Watanabe | 79155d7 | 2018-08-13 16:44:54 +0900 | [diff] [blame] | 149 | stride = ALIGN(stride, 256); |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 150 | |
| 151 | drv_bo_from_format(bo, stride, height, format); |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 152 | |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 153 | memset(&gem_create, 0, sizeof(gem_create)); |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 154 | gem_create.in.bo_size = bo->meta.total_size; |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 155 | gem_create.in.alignment = 256; |
Dominik Behr | fa17cdd | 2017-11-30 12:23:06 -0800 | [diff] [blame] | 156 | gem_create.in.domain_flags = 0; |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 157 | |
Gurchetan Singh | 71bc665 | 2018-09-17 17:42:05 -0700 | [diff] [blame] | 158 | if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK)) |
Dominik Behr | fa17cdd | 2017-11-30 12:23:06 -0800 | [diff] [blame] | 159 | gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; |
| 160 | |
Deepak Sharma | 62a9c4e | 2018-05-01 12:11:27 -0700 | [diff] [blame] | 161 | gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT; |
Bas Nieuwenhuizen | 91d3697 | 2020-04-27 19:59:29 +0000 | [diff] [blame] | 162 | if (!(use_flags & (BO_USE_SW_READ_OFTEN | BO_USE_SCANOUT))) |
Jao-ke Chin-Lee | 5481e3c | 2020-04-10 00:12:12 +0000 | [diff] [blame] | 163 | gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC; |
Dominik Behr | fa17cdd | 2017-11-30 12:23:06 -0800 | [diff] [blame] | 164 | |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 165 | /* Allocate the buffer with the preferred heap. */ |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 166 | ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create, |
| 167 | sizeof(gem_create)); |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 168 | if (ret < 0) |
| 169 | return ret; |
| 170 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 171 | for (plane = 0; plane < bo->meta.num_planes; plane++) |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 172 | bo->handles[plane].u32 = gem_create.out.handle; |
| 173 | |
Bas Nieuwenhuizen | 7119d33 | 2020-02-07 20:20:30 +0100 | [diff] [blame] | 174 | bo->meta.format_modifiers[0] = DRM_FORMAT_MOD_LINEAR; |
| 175 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 176 | return 0; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 177 | } |
| 178 | |
ChromeOS Developer | 9b367b3 | 2020-03-02 13:08:53 +0100 | [diff] [blame] | 179 | static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, |
| 180 | uint64_t use_flags) |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 181 | { |
| 182 | struct combination *combo; |
ChromeOS Developer | 9b367b3 | 2020-03-02 13:08:53 +0100 | [diff] [blame] | 183 | |
| 184 | combo = drv_get_combination(bo->drv, format, use_flags); |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 185 | if (!combo) |
| 186 | return -EINVAL; |
| 187 | |
ChromeOS Developer | 9b367b3 | 2020-03-02 13:08:53 +0100 | [diff] [blame] | 188 | if (combo->metadata.tiling == TILE_TYPE_DRI) { |
| 189 | bool needs_alignment = false; |
| 190 | #ifdef __ANDROID__ |
| 191 | /* |
| 192 | * Currently, the gralloc API doesn't differentiate between allocation time and map |
| 193 | * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at |
| 194 | * allocation time. |
| 195 | * |
| 196 | * See b/115946221,b/117942643 |
| 197 | */ |
| 198 | if (use_flags & (BO_USE_SW_MASK)) |
| 199 | needs_alignment = true; |
| 200 | #endif |
| 201 | // See b/122049612 |
| 202 | if (use_flags & (BO_USE_SCANOUT)) |
| 203 | needs_alignment = true; |
| 204 | |
| 205 | if (needs_alignment) { |
| 206 | uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0); |
| 207 | width = ALIGN(width, 256 / bytes_per_pixel); |
| 208 | } |
| 209 | |
| 210 | return dri_bo_create(bo, width, height, format, use_flags); |
| 211 | } |
| 212 | |
| 213 | return amdgpu_create_bo_linear(bo, width, height, format, use_flags); |
| 214 | } |
| 215 | |
| 216 | static int amdgpu_create_bo_with_modifiers(struct bo *bo, uint32_t width, uint32_t height, |
| 217 | uint32_t format, const uint64_t *modifiers, |
| 218 | uint32_t count) |
| 219 | { |
| 220 | bool only_use_linear = true; |
| 221 | |
| 222 | for (uint32_t i = 0; i < count; ++i) |
| 223 | if (modifiers[i] != DRM_FORMAT_MOD_LINEAR) |
| 224 | only_use_linear = false; |
| 225 | |
| 226 | if (only_use_linear) |
| 227 | return amdgpu_create_bo_linear(bo, width, height, format, BO_USE_SCANOUT); |
| 228 | |
| 229 | return dri_bo_create_with_modifiers(bo, width, height, format, modifiers, count); |
| 230 | } |
| 231 | |
| 232 | static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data) |
| 233 | { |
| 234 | bool dri_tiling = data->format_modifiers[0] != DRM_FORMAT_MOD_LINEAR; |
| 235 | if (data->format_modifiers[0] == DRM_FORMAT_MOD_INVALID) { |
| 236 | struct combination *combo; |
| 237 | combo = drv_get_combination(bo->drv, data->format, data->use_flags); |
| 238 | if (!combo) |
| 239 | return -EINVAL; |
| 240 | |
| 241 | dri_tiling = combo->metadata.tiling == TILE_TYPE_DRI; |
| 242 | } |
| 243 | |
| 244 | if (dri_tiling) |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 245 | return dri_bo_import(bo, data); |
| 246 | else |
| 247 | return drv_prime_bo_import(bo, data); |
| 248 | } |
| 249 | |
| 250 | static int amdgpu_destroy_bo(struct bo *bo) |
| 251 | { |
| 252 | if (bo->priv) |
| 253 | return dri_bo_destroy(bo); |
| 254 | else |
| 255 | return drv_gem_bo_destroy(bo); |
| 256 | } |
| 257 | |
| 258 | static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags) |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 259 | { |
| 260 | int ret; |
| 261 | union drm_amdgpu_gem_mmap gem_map; |
| 262 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 263 | if (bo->priv) |
| 264 | return dri_bo_map(bo, vma, plane, map_flags); |
| 265 | |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 266 | memset(&gem_map, 0, sizeof(gem_map)); |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 267 | gem_map.in.handle = bo->handles[plane].u32; |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 268 | |
| 269 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map); |
| 270 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 271 | drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n"); |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 272 | return MAP_FAILED; |
| 273 | } |
Gurchetan Singh | cfb8876 | 2017-09-28 17:14:50 -0700 | [diff] [blame] | 274 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 275 | vma->length = bo->meta.total_size; |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 276 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 277 | return mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd, |
Gurchetan Singh | cfb8876 | 2017-09-28 17:14:50 -0700 | [diff] [blame] | 278 | gem_map.out.addr_ptr); |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 279 | } |
| 280 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 281 | static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma) |
| 282 | { |
| 283 | if (bo->priv) |
| 284 | return dri_bo_unmap(bo, vma); |
| 285 | else |
| 286 | return munmap(vma->addr, vma->length); |
| 287 | } |
| 288 | |
Deepak Sharma | ff66c80 | 2018-11-16 12:10:54 -0800 | [diff] [blame] | 289 | static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping) |
| 290 | { |
| 291 | int ret; |
| 292 | union drm_amdgpu_gem_wait_idle wait_idle; |
| 293 | |
| 294 | if (bo->priv) |
| 295 | return 0; |
| 296 | |
| 297 | memset(&wait_idle, 0, sizeof(wait_idle)); |
| 298 | wait_idle.in.handle = bo->handles[0].u32; |
| 299 | wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE; |
| 300 | |
| 301 | ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle, |
| 302 | sizeof(wait_idle)); |
| 303 | |
| 304 | if (ret < 0) { |
| 305 | drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret); |
| 306 | return ret; |
| 307 | } |
| 308 | |
| 309 | if (ret == 0 && wait_idle.out.status) |
| 310 | drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n"); |
| 311 | |
| 312 | return 0; |
| 313 | } |
| 314 | |
Gurchetan Singh | 0d44d48 | 2019-06-04 19:39:51 -0700 | [diff] [blame] | 315 | static uint32_t amdgpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags) |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 316 | { |
| 317 | switch (format) { |
Ricky Liang | 0b78e07 | 2017-11-10 09:17:17 +0800 | [diff] [blame] | 318 | case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED: |
| 319 | /* Camera subsystem requires NV12. */ |
| 320 | if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)) |
| 321 | return DRM_FORMAT_NV12; |
| 322 | /*HACK: See b/28671744 */ |
| 323 | return DRM_FORMAT_XBGR8888; |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 324 | case DRM_FORMAT_FLEX_YCbCr_420_888: |
| 325 | return DRM_FORMAT_NV12; |
| 326 | default: |
| 327 | return format; |
| 328 | } |
| 329 | } |
| 330 | |
Gurchetan Singh | 3e9d383 | 2017-10-31 10:36:25 -0700 | [diff] [blame] | 331 | const struct backend backend_amdgpu = { |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 332 | .name = "amdgpu", |
| 333 | .init = amdgpu_init, |
| 334 | .close = amdgpu_close, |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 335 | .bo_create = amdgpu_create_bo, |
ChromeOS Developer | 9b367b3 | 2020-03-02 13:08:53 +0100 | [diff] [blame] | 336 | .bo_create_with_modifiers = amdgpu_create_bo_with_modifiers, |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 337 | .bo_destroy = amdgpu_destroy_bo, |
| 338 | .bo_import = amdgpu_import_bo, |
| 339 | .bo_map = amdgpu_map_bo, |
| 340 | .bo_unmap = amdgpu_unmap_bo, |
Deepak Sharma | ff66c80 | 2018-11-16 12:10:54 -0800 | [diff] [blame] | 341 | .bo_invalidate = amdgpu_bo_invalidate, |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 342 | .resolve_format = amdgpu_resolve_format, |
ChromeOS Developer | 44588bb | 2020-03-02 16:32:09 +0100 | [diff] [blame] | 343 | .num_planes_from_modifier = dri_num_planes_from_modifier, |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 344 | }; |
| 345 | |
| 346 | #endif |