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Zach Reizner85c4c5f2017-10-04 13:15:57 -07001/*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#ifndef VIRGL_HW_H
24#define VIRGL_HW_H
25
Gurchetan Singh51e785f2019-06-05 08:48:02 -070026#include <stdint.h>
27
Zach Reizner85c4c5f2017-10-04 13:15:57 -070028struct virgl_box {
29 uint32_t x, y, z;
30 uint32_t w, h, d;
31};
32
33/* formats known by the HW device - based on gallium subset */
34enum virgl_formats {
35 VIRGL_FORMAT_B8G8R8A8_UNORM = 1,
36 VIRGL_FORMAT_B8G8R8X8_UNORM = 2,
37 VIRGL_FORMAT_A8R8G8B8_UNORM = 3,
38 VIRGL_FORMAT_X8R8G8B8_UNORM = 4,
39 VIRGL_FORMAT_B5G5R5A1_UNORM = 5,
40 VIRGL_FORMAT_B4G4R4A4_UNORM = 6,
41 VIRGL_FORMAT_B5G6R5_UNORM = 7,
Gurchetan Singh51e785f2019-06-05 08:48:02 -070042 VIRGL_FORMAT_R10G10B10A2_UNORM = 8,
Zach Reizner85c4c5f2017-10-04 13:15:57 -070043 VIRGL_FORMAT_L8_UNORM = 9, /**< ubyte luminance */
44 VIRGL_FORMAT_A8_UNORM = 10, /**< ubyte alpha */
45 VIRGL_FORMAT_L8A8_UNORM = 12, /**< ubyte alpha, luminance */
46 VIRGL_FORMAT_L16_UNORM = 13, /**< ushort luminance */
47
48 VIRGL_FORMAT_Z16_UNORM = 16,
49 VIRGL_FORMAT_Z32_UNORM = 17,
50 VIRGL_FORMAT_Z32_FLOAT = 18,
51 VIRGL_FORMAT_Z24_UNORM_S8_UINT = 19,
52 VIRGL_FORMAT_S8_UINT_Z24_UNORM = 20,
53 VIRGL_FORMAT_Z24X8_UNORM = 21,
54 VIRGL_FORMAT_S8_UINT = 23, /**< ubyte stencil */
55
56 VIRGL_FORMAT_R32_FLOAT = 28,
57 VIRGL_FORMAT_R32G32_FLOAT = 29,
58 VIRGL_FORMAT_R32G32B32_FLOAT = 30,
59 VIRGL_FORMAT_R32G32B32A32_FLOAT = 31,
60
61 VIRGL_FORMAT_R16_UNORM = 48,
62 VIRGL_FORMAT_R16G16_UNORM = 49,
63
64 VIRGL_FORMAT_R16G16B16A16_UNORM = 51,
65
66 VIRGL_FORMAT_R16_SNORM = 56,
67 VIRGL_FORMAT_R16G16_SNORM = 57,
68 VIRGL_FORMAT_R16G16B16A16_SNORM = 59,
69
70 VIRGL_FORMAT_R8_UNORM = 64,
71 VIRGL_FORMAT_R8G8_UNORM = 65,
Marissa Wall1476c7e2020-01-24 15:05:57 -080072 VIRGL_FORMAT_R8G8B8_UNORM = 66,
Zach Reizner85c4c5f2017-10-04 13:15:57 -070073 VIRGL_FORMAT_R8G8B8A8_UNORM = 67,
74
75 VIRGL_FORMAT_R8_SNORM = 74,
76 VIRGL_FORMAT_R8G8_SNORM = 75,
77 VIRGL_FORMAT_R8G8B8_SNORM = 76,
78 VIRGL_FORMAT_R8G8B8A8_SNORM = 77,
79
80 VIRGL_FORMAT_R16_FLOAT = 91,
81 VIRGL_FORMAT_R16G16_FLOAT = 92,
82 VIRGL_FORMAT_R16G16B16_FLOAT = 93,
83 VIRGL_FORMAT_R16G16B16A16_FLOAT = 94,
84
85 VIRGL_FORMAT_L8_SRGB = 95,
86 VIRGL_FORMAT_L8A8_SRGB = 96,
87 VIRGL_FORMAT_B8G8R8A8_SRGB = 100,
88 VIRGL_FORMAT_B8G8R8X8_SRGB = 101,
Gurchetan Singh51e785f2019-06-05 08:48:02 -070089 VIRGL_FORMAT_R8G8B8A8_SRGB = 104,
Zach Reizner85c4c5f2017-10-04 13:15:57 -070090
91 /* compressed formats */
92 VIRGL_FORMAT_DXT1_RGB = 105,
93 VIRGL_FORMAT_DXT1_RGBA = 106,
94 VIRGL_FORMAT_DXT3_RGBA = 107,
95 VIRGL_FORMAT_DXT5_RGBA = 108,
96
97 /* sRGB, compressed */
98 VIRGL_FORMAT_DXT1_SRGB = 109,
99 VIRGL_FORMAT_DXT1_SRGBA = 110,
100 VIRGL_FORMAT_DXT3_SRGBA = 111,
101 VIRGL_FORMAT_DXT5_SRGBA = 112,
102
103 /* rgtc compressed */
104 VIRGL_FORMAT_RGTC1_UNORM = 113,
105 VIRGL_FORMAT_RGTC1_SNORM = 114,
106 VIRGL_FORMAT_RGTC2_UNORM = 115,
107 VIRGL_FORMAT_RGTC2_SNORM = 116,
108
109 VIRGL_FORMAT_A8B8G8R8_UNORM = 121,
110 VIRGL_FORMAT_B5G5R5X1_UNORM = 122,
111 VIRGL_FORMAT_R11G11B10_FLOAT = 124,
112 VIRGL_FORMAT_R9G9B9E5_FLOAT = 125,
113 VIRGL_FORMAT_Z32_FLOAT_S8X24_UINT = 126,
114
115 VIRGL_FORMAT_B10G10R10A2_UNORM = 131,
116 VIRGL_FORMAT_R8G8B8X8_UNORM = 134,
117 VIRGL_FORMAT_B4G4R4X4_UNORM = 135,
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700118 VIRGL_FORMAT_X24S8_UINT = 136,
119 VIRGL_FORMAT_S8X24_UINT = 137,
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700120 VIRGL_FORMAT_B2G3R3_UNORM = 139,
121
122 VIRGL_FORMAT_L16A16_UNORM = 140,
123 VIRGL_FORMAT_A16_UNORM = 141,
124
125 VIRGL_FORMAT_A8_SNORM = 147,
126 VIRGL_FORMAT_L8_SNORM = 148,
127 VIRGL_FORMAT_L8A8_SNORM = 149,
128
129 VIRGL_FORMAT_A16_SNORM = 151,
130 VIRGL_FORMAT_L16_SNORM = 152,
131 VIRGL_FORMAT_L16A16_SNORM = 153,
132
133 VIRGL_FORMAT_A16_FLOAT = 155,
134 VIRGL_FORMAT_L16_FLOAT = 156,
135 VIRGL_FORMAT_L16A16_FLOAT = 157,
136
137 VIRGL_FORMAT_A32_FLOAT = 159,
138 VIRGL_FORMAT_L32_FLOAT = 160,
139 VIRGL_FORMAT_L32A32_FLOAT = 161,
140
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700141 VIRGL_FORMAT_YV12 = 163,
142 VIRGL_FORMAT_YV16 = 164,
143 VIRGL_FORMAT_IYUV = 165, /**< aka I420 */
144 VIRGL_FORMAT_NV12 = 166,
145 VIRGL_FORMAT_NV21 = 167,
146
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700147 VIRGL_FORMAT_R8_UINT = 177,
148 VIRGL_FORMAT_R8G8_UINT = 178,
149 VIRGL_FORMAT_R8G8B8_UINT = 179,
150 VIRGL_FORMAT_R8G8B8A8_UINT = 180,
151
152 VIRGL_FORMAT_R8_SINT = 181,
153 VIRGL_FORMAT_R8G8_SINT = 182,
154 VIRGL_FORMAT_R8G8B8_SINT = 183,
155 VIRGL_FORMAT_R8G8B8A8_SINT = 184,
156
157 VIRGL_FORMAT_R16_UINT = 185,
158 VIRGL_FORMAT_R16G16_UINT = 186,
159 VIRGL_FORMAT_R16G16B16_UINT = 187,
160 VIRGL_FORMAT_R16G16B16A16_UINT = 188,
161
162 VIRGL_FORMAT_R16_SINT = 189,
163 VIRGL_FORMAT_R16G16_SINT = 190,
164 VIRGL_FORMAT_R16G16B16_SINT = 191,
165 VIRGL_FORMAT_R16G16B16A16_SINT = 192,
166 VIRGL_FORMAT_R32_UINT = 193,
167 VIRGL_FORMAT_R32G32_UINT = 194,
168 VIRGL_FORMAT_R32G32B32_UINT = 195,
169 VIRGL_FORMAT_R32G32B32A32_UINT = 196,
170
171 VIRGL_FORMAT_R32_SINT = 197,
172 VIRGL_FORMAT_R32G32_SINT = 198,
173 VIRGL_FORMAT_R32G32B32_SINT = 199,
174 VIRGL_FORMAT_R32G32B32A32_SINT = 200,
175
176 VIRGL_FORMAT_A8_UINT = 201,
177 VIRGL_FORMAT_L8_UINT = 203,
178 VIRGL_FORMAT_L8A8_UINT = 204,
179
180 VIRGL_FORMAT_A8_SINT = 205,
181 VIRGL_FORMAT_L8_SINT = 207,
182 VIRGL_FORMAT_L8A8_SINT = 208,
183
184 VIRGL_FORMAT_A16_UINT = 209,
185 VIRGL_FORMAT_L16_UINT = 211,
186 VIRGL_FORMAT_L16A16_UINT = 212,
187
188 VIRGL_FORMAT_A16_SINT = 213,
189 VIRGL_FORMAT_L16_SINT = 215,
190 VIRGL_FORMAT_L16A16_SINT = 216,
191
192 VIRGL_FORMAT_A32_UINT = 217,
193 VIRGL_FORMAT_L32_UINT = 219,
194 VIRGL_FORMAT_L32A32_UINT = 220,
195
196 VIRGL_FORMAT_A32_SINT = 221,
197 VIRGL_FORMAT_L32_SINT = 223,
198 VIRGL_FORMAT_L32A32_SINT = 224,
199
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700200 VIRGL_FORMAT_B10G10R10A2_UINT = 225,
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700201 VIRGL_FORMAT_R8G8B8X8_SNORM = 229,
202
203 VIRGL_FORMAT_R8G8B8X8_SRGB = 230,
204
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700205 VIRGL_FORMAT_R8G8B8X8_UINT = 231,
206 VIRGL_FORMAT_R8G8B8X8_SINT = 232,
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700207 VIRGL_FORMAT_B10G10R10X2_UNORM = 233,
208 VIRGL_FORMAT_R16G16B16X16_UNORM = 234,
209 VIRGL_FORMAT_R16G16B16X16_SNORM = 235,
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700210 VIRGL_FORMAT_R16G16B16X16_FLOAT = 236,
211 VIRGL_FORMAT_R16G16B16X16_UINT = 237,
212 VIRGL_FORMAT_R16G16B16X16_SINT = 238,
213
214 VIRGL_FORMAT_R10G10B10A2_UINT = 253,
215
216 VIRGL_FORMAT_BPTC_RGBA_UNORM = 255,
217 VIRGL_FORMAT_BPTC_SRGBA = 256,
218 VIRGL_FORMAT_BPTC_RGB_FLOAT = 257,
219 VIRGL_FORMAT_BPTC_RGB_UFLOAT = 258,
220
221 VIRGL_FORMAT_R10G10B10X2_UNORM = 308,
222 VIRGL_FORMAT_A4B4G4R4_UNORM = 311,
223
224 VIRGL_FORMAT_R8_SRGB = 312,
225 VIRGL_FORMAT_MAX /* = PIPE_FORMAT_COUNT */,
226
227 /* Below formats must not be used in the guest. */
228 VIRGL_FORMAT_B8G8R8X8_UNORM_EMULATED,
229 VIRGL_FORMAT_B8G8R8A8_UNORM_EMULATED,
230 VIRGL_FORMAT_MAX_EXTENDED
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700231};
232
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700233/* These are used by the capability_bits field in virgl_caps_v2. */
234#define VIRGL_CAP_NONE 0
235#define VIRGL_CAP_TGSI_INVARIANT (1 << 0)
236#define VIRGL_CAP_TEXTURE_VIEW (1 << 1)
237#define VIRGL_CAP_SET_MIN_SAMPLES (1 << 2)
238#define VIRGL_CAP_COPY_IMAGE (1 << 3)
239#define VIRGL_CAP_TGSI_PRECISE (1 << 4)
240#define VIRGL_CAP_TXQS (1 << 5)
241#define VIRGL_CAP_MEMORY_BARRIER (1 << 6)
242#define VIRGL_CAP_COMPUTE_SHADER (1 << 7)
243#define VIRGL_CAP_FB_NO_ATTACH (1 << 8)
244#define VIRGL_CAP_ROBUST_BUFFER_ACCESS (1 << 9)
245#define VIRGL_CAP_TGSI_FBFETCH (1 << 10)
246#define VIRGL_CAP_SHADER_CLOCK (1 << 11)
247#define VIRGL_CAP_TEXTURE_BARRIER (1 << 12)
248#define VIRGL_CAP_TGSI_COMPONENTS (1 << 13)
249#define VIRGL_CAP_GUEST_MAY_INIT_LOG (1 << 14)
250#define VIRGL_CAP_SRGB_WRITE_CONTROL (1 << 15)
251#define VIRGL_CAP_QBO (1 << 16)
252#define VIRGL_CAP_TRANSFER (1 << 17)
253#define VIRGL_CAP_FBO_MIXED_COLOR_FORMATS (1 << 18)
254#define VIRGL_CAP_FAKE_FP64 (1 << 19)
255#define VIRGL_CAP_BIND_COMMAND_ARGS (1 << 20)
256#define VIRGL_CAP_MULTI_DRAW_INDIRECT (1 << 21)
257#define VIRGL_CAP_INDIRECT_PARAMS (1 << 22)
258#define VIRGL_CAP_TRANSFORM_FEEDBACK3 (1 << 23)
259#define VIRGL_CAP_3D_ASTC (1 << 24)
260#define VIRGL_CAP_INDIRECT_INPUT_ADDR (1 << 25)
261#define VIRGL_CAP_COPY_TRANSFER (1 << 26)
262#define VIRGL_CAP_CLIP_HALFZ (1 << 27)
263#define VIRGL_CAP_APP_TWEAK_SUPPORT (1 << 28)
264#define VIRGL_CAP_BGRA_SRGB_IS_EMULATED (1 << 29)
265
266/* virgl bind flags - these are compatible with mesa 10.5 gallium.
267 * but are fixed, no other should be passed to virgl either.
268 */
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700269#define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
270#define VIRGL_BIND_RENDER_TARGET (1 << 1)
271#define VIRGL_BIND_SAMPLER_VIEW (1 << 3)
272#define VIRGL_BIND_VERTEX_BUFFER (1 << 4)
273#define VIRGL_BIND_INDEX_BUFFER (1 << 5)
274#define VIRGL_BIND_CONSTANT_BUFFER (1 << 6)
275#define VIRGL_BIND_DISPLAY_TARGET (1 << 7)
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700276#define VIRGL_BIND_COMMAND_ARGS (1 << 8)
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700277#define VIRGL_BIND_STREAM_OUTPUT (1 << 11)
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700278#define VIRGL_BIND_SHADER_BUFFER (1 << 14)
279#define VIRGL_BIND_QUERY_BUFFER (1 << 15)
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700280#define VIRGL_BIND_CURSOR (1 << 16)
281#define VIRGL_BIND_CUSTOM (1 << 17)
282#define VIRGL_BIND_SCANOUT (1 << 18)
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700283/* Used for buffers that are backed by guest storage and
284 * are only read by the host.
285 */
286#define VIRGL_BIND_STAGING (1 << 19)
287#define VIRGL_BIND_SHARED (1 << 20)
288
289#define VIRGL_BIND_PREFER_EMULATED_BGRA (1 << 21)
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700290
David Stevens55a6cf92019-09-03 10:45:33 +0900291#define VIRGL_BIND_LINEAR (1 << 22)
292
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700293struct virgl_caps_bool_set1 {
294 unsigned indep_blend_enable:1;
295 unsigned indep_blend_func:1;
296 unsigned cube_map_array:1;
297 unsigned shader_stencil_export:1;
298 unsigned conditional_render:1;
299 unsigned start_instance:1;
300 unsigned primitive_restart:1;
301 unsigned blend_eq_sep:1;
302 unsigned instanceid:1;
303 unsigned vertex_element_instance_divisor:1;
304 unsigned seamless_cube_map:1;
305 unsigned occlusion_query:1;
306 unsigned timer_query:1;
307 unsigned streamout_pause_resume:1;
308 unsigned texture_multisample:1;
309 unsigned fragment_coord_conventions:1;
310 unsigned depth_clip_disable:1;
311 unsigned seamless_cube_map_per_texture:1;
312 unsigned ubo:1;
313 unsigned color_clamping:1; /* not in GL 3.1 core profile */
314 unsigned poly_stipple:1; /* not in GL 3.1 core profile */
315 unsigned mirror_clamp:1;
316 unsigned texture_query_lod:1;
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700317 unsigned has_fp64:1;
318 unsigned has_tessellation_shaders:1;
319 unsigned has_indirect_draw:1;
320 unsigned has_sample_shading:1;
321 unsigned has_cull:1;
322 unsigned conditional_render_inverted:1;
323 unsigned derivative_control:1;
324 unsigned polygon_offset_clamp:1;
325 unsigned transform_feedback_overflow_query:1;
326 /* DO NOT ADD ANYMORE MEMBERS - need to add another 32-bit to v2 caps */
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700327};
328
329/* endless expansion capabilites - current gallium has 252 formats */
330struct virgl_supported_format_mask {
331 uint32_t bitmask[16];
332};
333/* capabilities set 2 - version 1 - 32-bit and float values */
334struct virgl_caps_v1 {
335 uint32_t max_version;
336 struct virgl_supported_format_mask sampler;
337 struct virgl_supported_format_mask render;
338 struct virgl_supported_format_mask depthstencil;
339 struct virgl_supported_format_mask vertexbuffer;
340 struct virgl_caps_bool_set1 bset;
341 uint32_t glsl_level;
342 uint32_t max_texture_array_layers;
343 uint32_t max_streamout_buffers;
344 uint32_t max_dual_source_render_targets;
345 uint32_t max_render_targets;
346 uint32_t max_samples;
347 uint32_t prim_mask;
348 uint32_t max_tbo_size;
349 uint32_t max_uniform_blocks;
350 uint32_t max_viewports;
351 uint32_t max_texture_gather_components;
352};
353
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700354/*
355 * This struct should be growable when used in capset 2,
356 * so we shouldn't have to add a v3 ever.
357 */
358struct virgl_caps_v2 {
359 struct virgl_caps_v1 v1;
360 float min_aliased_point_size;
361 float max_aliased_point_size;
362 float min_smooth_point_size;
363 float max_smooth_point_size;
364 float min_aliased_line_width;
365 float max_aliased_line_width;
366 float min_smooth_line_width;
367 float max_smooth_line_width;
368 float max_texture_lod_bias;
369 uint32_t max_geom_output_vertices;
370 uint32_t max_geom_total_output_components;
371 uint32_t max_vertex_outputs;
372 uint32_t max_vertex_attribs;
373 uint32_t max_shader_patch_varyings;
374 int32_t min_texel_offset;
375 int32_t max_texel_offset;
376 int32_t min_texture_gather_offset;
377 int32_t max_texture_gather_offset;
378 uint32_t texture_buffer_offset_alignment;
379 uint32_t uniform_buffer_offset_alignment;
380 uint32_t shader_buffer_offset_alignment;
381 uint32_t capability_bits;
382 uint32_t sample_locations[8];
383 uint32_t max_vertex_attrib_stride;
384 uint32_t max_shader_buffer_frag_compute;
385 uint32_t max_shader_buffer_other_stages;
386 uint32_t max_shader_image_frag_compute;
387 uint32_t max_shader_image_other_stages;
388 uint32_t max_image_samples;
389 uint32_t max_compute_work_group_invocations;
390 uint32_t max_compute_shared_memory_size;
391 uint32_t max_compute_grid_size[3];
392 uint32_t max_compute_block_size[3];
393 uint32_t max_texture_2d_size;
394 uint32_t max_texture_3d_size;
395 uint32_t max_texture_cube_size;
396 uint32_t max_combined_shader_buffers;
397 uint32_t max_atomic_counters[6];
398 uint32_t max_atomic_counter_buffers[6];
399 uint32_t max_combined_atomic_counters;
400 uint32_t max_combined_atomic_counter_buffers;
401 uint32_t host_feature_check_version;
402 struct virgl_supported_format_mask supported_readback_formats;
Lepton Wueebce652020-02-26 15:13:34 -0800403 struct virgl_supported_format_mask scanout;
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700404};
405
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700406union virgl_caps {
407 uint32_t max_version;
408 struct virgl_caps_v1 v1;
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700409 struct virgl_caps_v2 v2;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700410};
411
412enum virgl_errors {
413 VIRGL_ERROR_NONE,
414 VIRGL_ERROR_UNKNOWN,
415 VIRGL_ERROR_UNKNOWN_RESOURCE_FORMAT,
416};
417
418enum virgl_ctx_errors {
419 VIRGL_ERROR_CTX_NONE,
420 VIRGL_ERROR_CTX_UNKNOWN,
421 VIRGL_ERROR_CTX_ILLEGAL_SHADER,
422 VIRGL_ERROR_CTX_ILLEGAL_HANDLE,
423 VIRGL_ERROR_CTX_ILLEGAL_RESOURCE,
424 VIRGL_ERROR_CTX_ILLEGAL_SURFACE,
425 VIRGL_ERROR_CTX_ILLEGAL_VERTEX_FORMAT,
426 VIRGL_ERROR_CTX_ILLEGAL_CMD_BUFFER,
Gurchetan Singh51e785f2019-06-05 08:48:02 -0700427 VIRGL_ERROR_CTX_GLES_HAVE_TES_BUT_MISS_TCS,
428 VIRGL_ERROR_GL_ANY_SAMPLES_PASSED,
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700429};
430
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700431#define VIRGL_RESOURCE_Y_0_TOP (1 << 0)
432#endif