Armando Montanez | 5104cd6 | 2019-12-10 14:36:43 -0800 | [diff] [blame] | 1 | // Copyright 2019 The Pigweed Authors |
| 2 | // |
| 3 | // Licensed under the Apache License, Version 2.0 (the "License"); you may not |
| 4 | // use this file except in compliance with the License. You may obtain a copy of |
| 5 | // the License at |
| 6 | // |
| 7 | // https://www.apache.org/licenses/LICENSE-2.0 |
| 8 | // |
| 9 | // Unless required by applicable law or agreed to in writing, software |
| 10 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 11 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the |
| 12 | // License for the specific language governing permissions and limitations under |
| 13 | // the License. |
| 14 | |
| 15 | #include <cstdint> |
| 16 | |
| 17 | #include "pw_cpu_exception/cpu_exception.h" |
| 18 | #include "pw_cpu_exception_armv7m/cpu_state.h" |
| 19 | #include "pw_preprocessor/compiler.h" |
| 20 | |
| 21 | namespace pw::cpu_exception { |
| 22 | namespace { |
| 23 | |
| 24 | // CMSIS/Cortex-M/ARMv7 related constants. |
| 25 | // These values are from the ARMv7-M Architecture Reference Manual DDI 0403E.b. |
| 26 | // https://static.docs.arm.com/ddi0403/e/DDI0403E_B_armv7m_arm.pdf |
| 27 | |
| 28 | // Masks for individual bits of CFSR. (ARMv7-M Section B3.2.15) |
| 29 | constexpr uint32_t kMemFaultStart = 0x1u; |
| 30 | constexpr uint32_t kMStkErrMask = kMemFaultStart << 4; |
| 31 | constexpr uint32_t kBusFaultStart = 0x1u << 8; |
| 32 | constexpr uint32_t kStkErrMask = kBusFaultStart << 4; |
| 33 | |
| 34 | // Bit masks for an exception return value. (ARMv7-M Section B1.5.8) |
| 35 | constexpr uint32_t kExcReturnStackMask = (0x1u << 2); |
| 36 | constexpr uint32_t kExcReturnBasicFrameMask = (0x1u << 4); |
| 37 | |
| 38 | // Memory mapped registers. (ARMv7-M Section B3.2.2, Table B3-4) |
| 39 | volatile uint32_t& arm_v7m_icsr = |
| 40 | *reinterpret_cast<volatile uint32_t*>(0xE000ED04u); |
| 41 | volatile uint32_t& arm_v7m_cfsr = |
| 42 | *reinterpret_cast<volatile uint32_t*>(0xE000ED28u); |
| 43 | volatile uint32_t& arm_v7m_mmfar = |
| 44 | *reinterpret_cast<volatile uint32_t*>(0xE000ED34u); |
| 45 | volatile uint32_t& arm_v7m_bfar = |
| 46 | *reinterpret_cast<volatile uint32_t*>(0xE000ED38u); |
| 47 | |
| 48 | // If the CPU fails to capture some registers, the captured struct members will |
| 49 | // be populated with this value. The only registers that this value should be |
| 50 | // loaded into are pc, lr, and psr when the CPU fails to push an exception |
| 51 | // context frame. |
| 52 | // |
| 53 | // 0xFFFFFFFF is an illegal lr value, which is why it was selected for this |
| 54 | // purpose. pc and psr values of 0xFFFFFFFF are dubious too, so this constant |
| 55 | // is clear enough at expressing that the registers weren't properly captured. |
| 56 | constexpr uint32_t kInvalidRegisterValue = 0xFFFFFFFF; |
| 57 | |
| 58 | // Checks exc_return in the captured CPU state to determine which stack pointer |
| 59 | // was in use prior to entering the exception handler. |
| 60 | bool PspWasActive(const CpuState& cpu_state) { |
| 61 | return cpu_state.extended.exc_return & kExcReturnStackMask; |
| 62 | } |
| 63 | |
| 64 | // Checks exc_return to determine if FPU state was pushed to the stack in |
| 65 | // addition to the base CPU context frame. |
| 66 | bool FpuStateWasPushed(const CpuState& cpu_state) { |
| 67 | return !(cpu_state.extended.exc_return & kExcReturnBasicFrameMask); |
| 68 | } |
| 69 | |
| 70 | // If the CPU successfully pushed context on exception, copy it into cpu_state. |
| 71 | // |
| 72 | // For more information see (See ARMv7-M Section B1.5.11, derived exceptions |
| 73 | // on exception entry). |
| 74 | void CloneBaseRegistersFromPsp(CpuState* cpu_state) { |
| 75 | // If CPU succeeded in pushing context to PSP, copy it to the MSP. |
| 76 | if (!(cpu_state->extended.cfsr & kStkErrMask) && |
| 77 | !(cpu_state->extended.cfsr & kMStkErrMask)) { |
| 78 | // TODO(amontanez): {r0-r3,r12} are captured in pw_CpuExceptionEntry(), |
| 79 | // so this only really needs to copy pc, lr, and psr. Could |
| 80 | // (possibly) improve speed, but would add marginally more |
| 81 | // complexity. |
| 82 | std::memcpy(&cpu_state->base, |
| 83 | reinterpret_cast<void*>(cpu_state->extended.psp), |
| 84 | sizeof(ArmV7mFaultRegisters)); |
| 85 | } else { |
| 86 | // If CPU context wasn't pushed to stack on exception entry, we can't |
| 87 | // recover psr, lr, and pc from exception-time. Make these values clearly |
| 88 | // invalid. |
| 89 | cpu_state->base.lr = kInvalidRegisterValue; |
| 90 | cpu_state->base.pc = kInvalidRegisterValue; |
| 91 | cpu_state->base.psr = kInvalidRegisterValue; |
| 92 | } |
| 93 | } |
| 94 | |
| 95 | // If the CPU successfully pushed context on exception, restore it from |
| 96 | // cpu_state. Otherwise, don't attempt to restore state. |
| 97 | // |
| 98 | // For more information see (See ARMv7-M Section B1.5.11, derived exceptions |
| 99 | // on exception entry). |
| 100 | void RestoreBaseRegistersToPsp(CpuState* cpu_state) { |
| 101 | // If CPU succeeded in pushing context to PSP on exception entry, restore the |
| 102 | // contents of cpu_state to the CPU-pushed register frame so the CPU can |
| 103 | // continue. Otherwise, don't attempt as we'll likely end up in an escalated |
| 104 | // hard fault. |
| 105 | if (!(cpu_state->extended.cfsr & kStkErrMask) && |
| 106 | !(cpu_state->extended.cfsr & kMStkErrMask)) { |
| 107 | std::memcpy(reinterpret_cast<void*>(cpu_state->extended.psp), |
| 108 | &cpu_state->base, |
| 109 | sizeof(ArmV7mFaultRegisters)); |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | // Determines the size of the CPU-pushed context frame. |
| 114 | uint32_t CpuContextSize(const CpuState& cpu_state) { |
| 115 | uint32_t cpu_context_size = sizeof(ArmV7mFaultRegisters); |
| 116 | if (FpuStateWasPushed(cpu_state)) { |
| 117 | cpu_context_size += sizeof(ArmV7mFaultRegistersFpu); |
| 118 | } |
| 119 | if (cpu_state.base.psr & kPsrExtraStackAlignBit) { |
| 120 | // Account for the extra 4-bytes the processor |
| 121 | // added to keep the stack pointer 8-byte aligned |
| 122 | cpu_context_size += 4; |
| 123 | } |
| 124 | |
| 125 | return cpu_context_size; |
| 126 | } |
| 127 | |
| 128 | // On exception entry, the Program Stack Pointer is patched to reflect the state |
| 129 | // at exception-time. On exception return, it is restored to the appropriate |
| 130 | // location. This calculates the delta that is used for these patch operations. |
| 131 | uint32_t CalculatePspDelta(const CpuState& cpu_state) { |
| 132 | // If CPU context was not pushed to program stack (because program stack |
| 133 | // wasn't in use, or an error occurred when pushing context), the PSP doesn't |
| 134 | // need to be shifted. |
| 135 | if (!PspWasActive(cpu_state) || (cpu_state.extended.cfsr & kStkErrMask) || |
| 136 | (cpu_state.extended.cfsr & kMStkErrMask)) { |
| 137 | return 0; |
| 138 | } |
| 139 | |
| 140 | return CpuContextSize(cpu_state); |
| 141 | } |
| 142 | |
| 143 | // On exception entry, the Main Stack Pointer is patched to reflect the state |
| 144 | // at exception-time. On exception return, it is restored to the appropriate |
| 145 | // location. This calculates the delta that is used for these patch operations. |
| 146 | uint32_t CalculateMspDelta(const CpuState& cpu_state) { |
| 147 | if (PspWasActive(cpu_state)) { |
| 148 | // TODO(amontanez): Since FPU state isn't captured at this time, we ignore |
| 149 | // it when patching MSP. To add FPU capture support, |
| 150 | // delete this if block as CpuContextSize() will include |
| 151 | // FPU context size in the calculation. |
| 152 | return sizeof(ArmV7mFaultRegisters) + sizeof(ArmV7mExtraRegisters); |
| 153 | } |
| 154 | |
| 155 | return CpuContextSize(cpu_state) + sizeof(ArmV7mExtraRegisters); |
| 156 | } |
| 157 | |
| 158 | } // namespace |
| 159 | |
| 160 | extern "C" { |
| 161 | |
| 162 | // Collect remaining CPU state (memory mapped registers), populate memory mapped |
| 163 | // registers, and call application exception handler. |
| 164 | PW_USED void pw_PackageAndHandleCpuException(CpuState* cpu_state) { |
| 165 | // Capture memory mapped registers. |
| 166 | cpu_state->extended.cfsr = arm_v7m_cfsr; |
| 167 | cpu_state->extended.icsr = arm_v7m_icsr; |
| 168 | cpu_state->extended.bfar = arm_v7m_bfar; |
| 169 | cpu_state->extended.mmfar = arm_v7m_mmfar; |
| 170 | |
| 171 | // CPU may have automatically pushed state to the program stack. If it did, |
| 172 | // the values can be copied into in the CpuState struct that is passed |
| 173 | // to HandleCpuException(). The cpu_state passed to the handler is ALWAYS |
| 174 | // stored on the main stack (MSP). |
| 175 | if (PspWasActive(*cpu_state)) { |
| 176 | CloneBaseRegistersFromPsp(cpu_state); |
| 177 | // If PSP wasn't active, this delta is 0. |
| 178 | cpu_state->extended.psp += CalculatePspDelta(*cpu_state); |
| 179 | } |
| 180 | |
| 181 | // Patch captured stack pointers so they reflect the state at exception time. |
| 182 | cpu_state->extended.msp += CalculateMspDelta(*cpu_state); |
| 183 | |
| 184 | // Call application-level exception handler. |
| 185 | HandleCpuException(cpu_state); |
| 186 | |
| 187 | // Restore program stack pointer so exception return can restore state if |
| 188 | // needed. |
| 189 | // Note: The default behavior of NOT subtracting a delta from MSP is |
| 190 | // intentional. This simplifies the assembly to pop the exception state |
| 191 | // off the main stack on exception return (since MSP currently reflects |
| 192 | // exception-time state). |
| 193 | cpu_state->extended.psp -= CalculatePspDelta(*cpu_state); |
| 194 | |
| 195 | // If PSP was active and the CPU pushed a context frame, we must copy the |
| 196 | // potentially modified state from cpu_state back to the PSP so the CPU can |
| 197 | // resume execution with the modified values. |
| 198 | if (PspWasActive(*cpu_state)) { |
| 199 | // In this case, there's no need to touch the MSP as it's at the location |
| 200 | // before we entering the exception (effectively popping the state initially |
| 201 | // pushed to the main stack). |
| 202 | RestoreBaseRegistersToPsp(cpu_state); |
| 203 | } else { |
| 204 | // Since we're restoring context from MSP, we DO need to adjust MSP to point |
| 205 | // to CPU-pushed context frame so it can be properly restored. |
| 206 | // No need to adjust PSP since nothing was pushed to program stack. |
| 207 | cpu_state->extended.msp -= CpuContextSize(*cpu_state); |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | // Captures faulting CPU state on the main stack (MSP), then calls the exception |
| 212 | // handlers. |
| 213 | // This function should be called immediately after an exception. |
| 214 | void pw_CpuExceptionEntry(void) { |
| 215 | asm volatile( |
| 216 | // If PSP was in use at the time of exception, it's possible the CPU |
| 217 | // wasn't able to push CPU state. To be safe, this first captures scratch |
| 218 | // registers before moving forward. |
| 219 | // |
| 220 | // Stack flag is bit index 2 (0x4) of exc_return value stored in lr. When |
| 221 | // this bit is set, the Process Stack Pointer (PSP) was in use. Otherwise, |
| 222 | // the Main Stack Pointer (MSP) was in use. (See ARMv7-M Section B1.5.8 |
| 223 | // for more details) |
| 224 | // The following block of assembly is equivalent to: |
| 225 | // if (lr & (1 << 2)) { |
| 226 | // msp -= sizeof(ArmV7mFaultRegisters); |
| 227 | // ArmV7mFaultRegisters* state = (ArmV7mFaultRegisters*) msp; |
| 228 | // state->r0 = r0; |
| 229 | // state->r1 = r1; |
| 230 | // state->r2 = r2; |
| 231 | // state->r3 = r3; |
| 232 | // state->r12 = r12; |
| 233 | // } |
| 234 | // |
| 235 | " tst lr, #(1 << 2) \n" |
| 236 | " itt ne \n" |
| 237 | " subne sp, sp, %[base_state_size] \n" |
| 238 | " stmne sp, {r0-r3, r12} \n" |
| 239 | |
| 240 | // Reserve stack space for additional registers. Since we're in exception |
| 241 | // handler mode, the main stack pointer is currently in use. |
| 242 | // r0 will temporarily store the end of captured_cpu_state to simplify |
| 243 | // assembly for copying additional registers. |
| 244 | " mrs r0, msp \n" |
| 245 | " sub sp, sp, %[extra_state_size] \n" |
| 246 | |
| 247 | // Store GPRs to stack. |
| 248 | " stmdb r0!, {r4-r11} \n" |
| 249 | |
| 250 | // Load special registers. |
| 251 | " mov r1, lr \n" |
| 252 | " mrs r2, msp \n" |
| 253 | " mrs r3, psp \n" |
| 254 | " mrs r4, control \n" |
| 255 | |
| 256 | // Store special registers to stack. |
| 257 | " stmdb r0!, {r1-r4} \n" |
| 258 | |
| 259 | // Store a pointer to the beginning of special registers in r4 so they can |
| 260 | // be restored later. |
| 261 | " mov r4, r0 \n" |
| 262 | |
| 263 | // Restore captured_cpu_state pointer to r0. This makes adding more |
| 264 | // memory mapped registers easier in the future since they're skipped in |
| 265 | // this assembly. |
| 266 | " mrs r0, msp \n" |
| 267 | |
| 268 | // Call intermediate handler that packages data. |
| 269 | " ldr r3, =pw_PackageAndHandleCpuException \n" |
| 270 | " blx r3 \n" |
| 271 | |
| 272 | // Restore state and exit exception handler. |
| 273 | // Pointer to saved CPU state was stored in r4. |
| 274 | " mov r0, r4 \n" |
| 275 | |
| 276 | // Restore special registers. |
| 277 | " ldm r0!, {r1-r4} \n" |
| 278 | " mov lr, r1 \n" |
| 279 | " msr control, r4 \n" |
| 280 | |
| 281 | // Restore GPRs. |
| 282 | " ldm r0, {r4-r11} \n" |
| 283 | |
| 284 | // Restore stack pointers. |
| 285 | " msr msp, r2 \n" |
| 286 | " msr psp, r3 \n" |
| 287 | |
| 288 | // Exit exception. |
| 289 | " bx lr \n" |
| 290 | // clang-format off |
| 291 | : /*output=*/ |
| 292 | : /*input=*/[base_state_size]"i"(sizeof(ArmV7mFaultRegisters)), |
| 293 | [extra_state_size]"i"(sizeof(ArmV7mExtraRegisters)) |
| 294 | // clang-format on |
| 295 | ); |
| 296 | } |
| 297 | |
| 298 | } // extern "C" |
| 299 | } // namespace pw::cpu_exception |