blob: a1a262a5deb3e85e104b08e3013851b0a8972d88 [file] [log] [blame]
cliechtib1055802004-04-16 01:10:29 +00001class BitaccessMeta(type):
2 """meta class that adds bit access properties to a
3 parallel port implementation"""
4
5 def __new__(self, classname, bases, classdict):
6 klass = type.__new__(self, classname, bases, classdict)
7 #status lines
8 klass.paperOut = property(klass.getInPaperOut, None, "Read the PaperOut signal")
9 #control lines
10 klass.dataStrobe = property(None, klass.setDataStrobe, "Set the DataStrobe signal")
11 #XXX ... other bits
12 #data bits
13 for bit in range(8):
14 mask = (1<<bit)
15 def getter(self, mask=mask):
16 return (self.getData() & mask) != 0
17 def setter(self, b, mask=mask):
18 if b:
19 self.setData(self.getData() | mask)
20 else:
21 self.setData(self.getData() & ~mask)
22 setattr(klass, "D%d" % bit, property(getter, setter, "Access databit %d" % bit))
23 #nibbles
24 for name, shift, width in [('D0_D3', 0, 4), ('D4_D7', 4, 4)]:
25 mask = (1<<width) - 1
26 def getter(self, shift=shift, mask=mask):
27 return (self.getData() >> shift) & mask
28 def setter(self, b, shift=shift, mask=mask):
29 self.setData((self.getData() & ~(mask<<shift)) | ((b&mask) << shift))
30 setattr(klass, name, property(getter, setter, "Access to %s" % name))
31 return klass
32
33class VirtualParallelPort:
34 """provides a virtual parallel port implementation, useful
35 for tests and simulations without real hardware"""
36
37 __metaclass__ = BitaccessMeta
38
39 def __init__(self, port=None):
40 self._data = 0
41
42 def setData(self, value):
43 self._data = value
44
45 def getData(self):
46 return self._data
47
48 #inputs return dummy value
49 def getInPaperOut(self): return self._dummy
50 #...
51 #outputs just store a tuple with (action, value) pair
52 def setDataStrobe(self, value): self._last = ('setDataStrobe', value)
53 #...
54
55#testing
56if __name__ == '__main__':
57 import unittest, sys
58
59 class TestBitaccess(unittest.TestCase):
60 """Tests a port with no timeout"""
61 def setUp(self):
62 self.p = VirtualParallelPort()
63
64 def testDatabits(self):
65 """bit by bit D0..D7"""
66 p = self.p
67 p.D0 = p.D2 = p.D4 = p.D6 = 1
68 self.failUnlessEqual(p._data, 0x55)
69 self.failUnlessEqual(
70 [p.D7, p.D6, p.D5, p.D4, p.D3, p.D2, p.D1, p.D0],
71 [0, 1, 0, 1, 0, 1, 0, 1]
72 )
73 p._data <<= 1
74 self.failUnlessEqual(
75 [p.D7, p.D6, p.D5, p.D4, p.D3, p.D2, p.D1, p.D0],
76 [1, 0, 1, 0, 1, 0, 1, 0]
77 )
78
79 def testDatabitsGroups(self):
80 """nibbles D0..D7"""
81 p = self.p
82 p.D0_D3 = 14
83 self.failUnlessEqual(p._data, 0x0e)
84 p.D0_D3 = 0
85 p.D4_D7 = 13
86 self.failUnlessEqual(p._data, 0xd0)
87 p.D0_D3 = p.D4_D7 = 0xa
88 self.failUnlessEqual(p._data, 0xaa)
89 #test bit patterns
90 for x in range(256):
91 #test getting
92 p._data = x
93 self.failUnlessEqual((p.D4_D7, p.D0_D3), (((x>>4) & 0xf), (x & 0xf)))
94 #test setting
95 p._data = 0
96 (p.D4_D7, p.D0_D3) = (((x>>4) & 0xf), (x & 0xf))
97 self.failUnlessEqual(p._data, x)
98
99 def testStatusbits(self):
100 """bit by bit status lines"""
101 #read the property:
102 self.p._dummy = 0
103 self.failUnlessEqual(self.p.paperOut, 0)
104
105 self.p._dummy = 1
106 self.failUnlessEqual(self.p.paperOut, 1)
107
108 #read only, must not be writable:
109 self.failUnlessRaises(AttributeError, setattr, self.p, 'paperOut', 1)
110
111 def testControlbits(self):
112 """bit by bit control lines"""
113 self.p.dataStrobe = 0
114 self.failUnlessEqual(self.p._last, ('setDataStrobe', 0))
115 self.p.dataStrobe = 1
116 self.failUnlessEqual(self.p._last, ('setDataStrobe', 1))
117
118 #write only, must not be writable:
119 self.failUnlessRaises(AttributeError, getattr, self.p, 'dataStrobe')
120
121 sys.argv.append('-v')
122 # When this module is executed from the command-line, it runs all its tests
123 unittest.main()
124