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cliechti88641262002-07-29 02:09:04 +00001#pyparallel driver for win32
2#see __init__.py
3#
4#(C) 2002 Chris Liechti <cliechti@gmx.net>
5# this is distributed under a free software license, see license.txt
6#
7# thanks to Dincer Aydin dinceraydin@altavista.net for his work on the
8# winioport module: www.geocities.com/dinceraydin/ the graphic below is
9# borrowed form him ;-)
10
11
12# LPT1 = 0x0378 or 0x03BC
13# LPT2 = 0x0278 or 0x0378
14# LPT3 = 0x0278
15#
16# Data Register (base + 0) ........ outputs
17#
18# 7 6 5 4 3 2 1 0
19# . . . . . . . * D0 ........... (pin 2), 1=High, 0=Low (true)
20# . . . . . . * . D1 ........... (pin 3), 1=High, 0=Low (true)
21# . . . . . * . . D2 ........... (pin 4), 1=High, 0=Low (true)
22# . . . . * . . . D3 ........... (pin 5), 1=High, 0=Low (true)
23# . . . * . . . . D4 ........... (pin 6), 1=High, 0=Low (true)
24# . . * . . . . . D5 ........... (pin 7), 1=High, 0=Low (true)
25# . * . . . . . . D6 ........... (pin 8), 1=High, 0=Low (true)
26# * . . . . . . . D7 ........... (pin 9), 1=High, 0=Low (true)
27#
28# Status Register (base + 1) ...... inputs
29#
30# 7 6 5 4 3 2 1 0
31# . . . . . * * * Undefined
32# . . . . * . . . Error ........ (pin 15), high=1, low=0 (true)
33# . . . * . . . . Selected ..... (pin 13), high=1, low=0 (true)
34# . . * . . . . . No paper ..... (pin 12), high=1, low=0 (true)
35# . * . . . . . . Ack .......... (pin 10), high=1, low=0 (true)
36# * . . . . . . . Busy ......... (pin 11), high=0, low=1 (inverted)
37#
38# ctrl Register (base + 2) ..... outputs
39#
40# 7 6 5 4 3 2 1 0
41# . . . . . . . * Strobe ....... (pin 1), 1=low, 0=high (inverted)
42# . . . . . . * . Auto Feed .... (pin 14), 1=low, 0=high (inverted)
cliechti619e4562002-07-31 00:53:06 +000043# . . . . . * . . Initialize ... (pin 16), 1=high,0=low (true)
cliechti88641262002-07-29 02:09:04 +000044# . . . . * . . . Select ....... (pin 17), 1=low, 0=high (inverted)
45# * * * * . . . . Unused
46
47LPT1 = 0
48LPT2 = 1
49
50LPT1_base = 0x0378
51LPT2_base = 0x0278
52
53import _pyparallel
54
55class Parallel:
56 def __init__(self, port = LPT1):
57 if port == LPT1:
58 self.dataRegAdr = LPT1_base
cliechti619e4562002-07-31 00:53:06 +000059 elif port == LPT2:
cliechti88641262002-07-29 02:09:04 +000060 self.dataRegAdr = LPT2_base
61 else:
62 raise ValueError("No such port available - expecting a number")
63 self.statusRegAdr = self.dataRegAdr + 1
64 self.ctrlRegAdr = self.dataRegAdr + 2
cliechtie7d23fe2003-05-26 19:42:23 +000065 self.ctrlReg = _pyparallel.inp(self.ctrlRegAdr)
cliechti88641262002-07-29 02:09:04 +000066
67 def setData(self, value):
68 _pyparallel.outp(self.dataRegAdr, value)
69
70 # control register output functions
cliechti619e4562002-07-31 00:53:06 +000071 def setDataStrobe(self, level):
cliechti88641262002-07-29 02:09:04 +000072 """data strobe bit"""
cliechti619e4562002-07-31 00:53:06 +000073 if level:
cliechti88641262002-07-29 02:09:04 +000074 self.ctrlReg = self.ctrlReg & ~0x01
cliechti619e4562002-07-31 00:53:06 +000075 else:
76 self.ctrlReg = self.ctrlReg | 0x01
cliechti88641262002-07-29 02:09:04 +000077 _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
78
cliechti619e4562002-07-31 00:53:06 +000079 def setAutoFeed(self, level):
cliechti88641262002-07-29 02:09:04 +000080 """auto feed bit"""
cliechti619e4562002-07-31 00:53:06 +000081 if level:
cliechti88641262002-07-29 02:09:04 +000082 self.ctrlReg = self.ctrlReg & ~0x02
cliechti619e4562002-07-31 00:53:06 +000083 else:
84 self.ctrlReg = self.ctrlReg | 0x02
cliechti88641262002-07-29 02:09:04 +000085 _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
86
cliechti619e4562002-07-31 00:53:06 +000087 def setInitOut(self, level):
cliechti88641262002-07-29 02:09:04 +000088 """initialize bit"""
cliechti619e4562002-07-31 00:53:06 +000089 if level:
cliechti88641262002-07-29 02:09:04 +000090 self.ctrlReg = self.ctrlReg | 0x04
cliechti619e4562002-07-31 00:53:06 +000091 else:
92 self.ctrlReg = self.ctrlReg & ~0x04
cliechti88641262002-07-29 02:09:04 +000093 _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
94
cliechti619e4562002-07-31 00:53:06 +000095 def setSelect(self, level):
cliechti88641262002-07-29 02:09:04 +000096 """select bit"""
cliechti619e4562002-07-31 00:53:06 +000097 if level:
cliechti88641262002-07-29 02:09:04 +000098 self.ctrlReg = self.ctrlReg & ~0x08
cliechti619e4562002-07-31 00:53:06 +000099 else:
100 self.ctrlReg = self.ctrlReg | 0x08
cliechti88641262002-07-29 02:09:04 +0000101 _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
102
103 def getInError(self):
104 """Error pin"""
105 return _pyparallel.inp(self.statusRegAdr) & 0x08 and 1
106
cliechtie7d23fe2003-05-26 19:42:23 +0000107 def getInSelected(self):
cliechti88641262002-07-29 02:09:04 +0000108 """select pin"""
109 return _pyparallel.inp(self.statusRegAdr) & 0x10 and 1
110
111 def getInPaperOut(self):
112 """paper out pin"""
113 return _pyparallel.inp(self.statusRegAdr) & 0x20 and 1
114
115 def getInAcknowledge(self):
116 """Acknowledge pin"""
117 return _pyparallel.inp(self.statusRegAdr) & 0x40 and 1
118
119 def getInBusy(self):
120 """input from busy pin"""
cliechti619e4562002-07-31 00:53:06 +0000121 return not (_pyparallel.inp(self.statusRegAdr) & 0x80)