| Mike Klein | 267f507 | 2019-06-03 16:27:46 -0500 | [diff] [blame] | 1 | A8 over A8 |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 2 | 14 values (originally 16): |
| 3 | ↑ v0 = splat 3B808081 (0.0039215689) |
| 4 | v1 = load8 arg(0) |
| Mike Klein | a6434a5 | 2020-01-08 14:06:52 -0600 | [diff] [blame] | 5 | v2 = to_f32 v1 |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 6 | v3 = mul_f32 v0 v2 |
| Mike Klein | 57bdb24 | 2020-01-08 15:25:07 -0600 | [diff] [blame] | 7 | v4 = load8 arg(1) |
| 8 | v5 = to_f32 v4 |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 9 | v6 = mul_f32 v0 v5 |
| Mike Klein | 57bdb24 | 2020-01-08 15:25:07 -0600 | [diff] [blame] | 10 | ↑ v7 = splat 3F800000 (1) |
| 11 | v8 = sub_f32 v7 v3 |
| 12 | v9 = mad_f32 v6 v8 v3 |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 13 | ↑ v10 = splat 437F0000 (255) |
| 14 | v11 = mul_f32 v9 v10 |
| 15 | v12 = round v11 |
| 16 | store8 arg(1) v12 |
| Mike Klein | 8c1e0ef | 2019-11-12 09:07:23 -0600 | [diff] [blame] | 17 | |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 18 | 6 registers, 14 instructions: |
| 19 | 0 r0 = splat 3B808081 (0.0039215689) |
| 20 | 1 r1 = splat 3F800000 (1) |
| 21 | 2 r2 = splat 437F0000 (255) |
| Mike Klein | 8c1e0ef | 2019-11-12 09:07:23 -0600 | [diff] [blame] | 22 | loop: |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 23 | 3 r3 = load8 arg(0) |
| 24 | 4 r3 = to_f32 r3 |
| 25 | 5 r3 = mul_f32 r0 r3 |
| 26 | 6 r4 = load8 arg(1) |
| 27 | 7 r4 = to_f32 r4 |
| 28 | 8 r4 = mul_f32 r0 r4 |
| 29 | 9 r5 = sub_f32 r1 r3 |
| 30 | 10 r3 = mad_f32 r4 r5 r3 |
| 31 | 11 r3 = mul_f32 r3 r2 |
| 32 | 12 r3 = round r3 |
| 33 | 13 store8 arg(1) r3 |
| Mike Klein | 8c1e0ef | 2019-11-12 09:07:23 -0600 | [diff] [blame] | 34 | |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 35 | A8 over G8 |
| 36 | 20 values (originally 22): |
| 37 | ↑ v0 = splat 3B808081 (0.0039215689) |
| 38 | v1 = load8 arg(1) |
| Mike Klein | a6434a5 | 2020-01-08 14:06:52 -0600 | [diff] [blame] | 39 | v2 = to_f32 v1 |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 40 | v3 = mul_f32 v0 v2 |
| 41 | v4 = load8 arg(0) |
| 42 | v5 = to_f32 v4 |
| 43 | v6 = mul_f32 v0 v5 |
| 44 | ↑ v7 = splat 3F800000 (1) |
| 45 | v8 = sub_f32 v7 v6 |
| 46 | v9 = mul_f32 v3 v8 |
| 47 | ↑ v10 = splat 3E59B3D0 (0.21259999) |
| 48 | ↑ v11 = splat 3F371759 (0.71520001) |
| 49 | ↑ v12 = splat 3D93DD98 (0.0722) |
| 50 | v13 = mul_f32 v9 v12 |
| 51 | v14 = mad_f32 v9 v11 v13 |
| 52 | v15 = mad_f32 v9 v10 v14 |
| 53 | ↑ v16 = splat 437F0000 (255) |
| 54 | v17 = mul_f32 v15 v16 |
| 55 | v18 = round v17 |
| 56 | store8 arg(1) v18 |
| 57 | |
| 58 | 8 registers, 20 instructions: |
| 59 | 0 r0 = splat 3B808081 (0.0039215689) |
| 60 | 1 r1 = splat 3F800000 (1) |
| 61 | 2 r2 = splat 3E59B3D0 (0.21259999) |
| 62 | 3 r3 = splat 3F371759 (0.71520001) |
| 63 | 4 r4 = splat 3D93DD98 (0.0722) |
| 64 | 5 r5 = splat 437F0000 (255) |
| 65 | loop: |
| 66 | 6 r6 = load8 arg(1) |
| 67 | 7 r6 = to_f32 r6 |
| 68 | 8 r6 = mul_f32 r0 r6 |
| 69 | 9 r7 = load8 arg(0) |
| 70 | 10 r7 = to_f32 r7 |
| 71 | 11 r7 = mul_f32 r0 r7 |
| 72 | 12 r7 = sub_f32 r1 r7 |
| 73 | 13 r7 = mul_f32 r6 r7 |
| 74 | 14 r6 = mul_f32 r7 r4 |
| 75 | 15 r6 = mad_f32 r7 r3 r6 |
| 76 | 16 r6 = mad_f32 r7 r2 r6 |
| 77 | 17 r6 = mul_f32 r6 r5 |
| 78 | 18 r6 = round r6 |
| 79 | 19 store8 arg(1) r6 |
| 80 | |
| 81 | A8 over RGBA_8888 |
| 82 | 39 values (originally 40): |
| 83 | ↑ v0 = splat 3B808081 (0.0039215689) |
| 84 | v1 = load32 arg(1) |
| 85 | ↑ v2 = splat FF (3.5733111e-43) |
| 86 | v3 = bit_and v2 v1 |
| 87 | v4 = to_f32 v3 |
| 88 | v5 = mul_f32 v0 v4 |
| 89 | v6 = load8 arg(0) |
| 90 | v7 = to_f32 v6 |
| 91 | v8 = mul_f32 v0 v7 |
| 92 | ↑ v9 = splat 3F800000 (1) |
| 93 | v10 = sub_f32 v9 v8 |
| 94 | v11 = mul_f32 v5 v10 |
| 95 | ↑ v12 = splat 437F0000 (255) |
| 96 | v13 = mul_f32 v11 v12 |
| 97 | v14 = round v13 |
| 98 | v15 = shr_i32 v1 8 |
| 99 | v16 = bit_and v2 v15 |
| 100 | v17 = to_f32 v16 |
| 101 | v18 = mul_f32 v0 v17 |
| 102 | v19 = mul_f32 v18 v10 |
| 103 | v20 = mul_f32 v19 v12 |
| 104 | v21 = round v20 |
| 105 | v22 = pack v14 v21 8 |
| 106 | v23 = shr_i32 v1 16 |
| 107 | v24 = bit_and v2 v23 |
| 108 | v25 = to_f32 v24 |
| 109 | v26 = mul_f32 v0 v25 |
| 110 | v27 = mul_f32 v26 v10 |
| 111 | v28 = mul_f32 v27 v12 |
| 112 | v29 = round v28 |
| 113 | v30 = shr_i32 v1 24 |
| 114 | v31 = to_f32 v30 |
| 115 | v32 = mul_f32 v0 v31 |
| 116 | v33 = mad_f32 v32 v10 v8 |
| 117 | v34 = mul_f32 v33 v12 |
| 118 | v35 = round v34 |
| 119 | v36 = pack v29 v35 8 |
| 120 | v37 = pack v22 v36 16 |
| 121 | store32 arg(1) v37 |
| 122 | |
| 123 | 9 registers, 39 instructions: |
| 124 | 0 r0 = splat 3B808081 (0.0039215689) |
| 125 | 1 r1 = splat FF (3.5733111e-43) |
| 126 | 2 r2 = splat 3F800000 (1) |
| 127 | 3 r3 = splat 437F0000 (255) |
| 128 | loop: |
| 129 | 4 r4 = load32 arg(1) |
| 130 | 5 r5 = bit_and r1 r4 |
| 131 | 6 r5 = to_f32 r5 |
| 132 | 7 r5 = mul_f32 r0 r5 |
| 133 | 8 r6 = load8 arg(0) |
| 134 | 9 r6 = to_f32 r6 |
| 135 | 10 r6 = mul_f32 r0 r6 |
| 136 | 11 r7 = sub_f32 r2 r6 |
| 137 | 12 r5 = mul_f32 r5 r7 |
| 138 | 13 r5 = mul_f32 r5 r3 |
| 139 | 14 r5 = round r5 |
| 140 | 15 r8 = shr_i32 r4 8 |
| 141 | 16 r8 = bit_and r1 r8 |
| 142 | 17 r8 = to_f32 r8 |
| 143 | 18 r8 = mul_f32 r0 r8 |
| 144 | 19 r8 = mul_f32 r8 r7 |
| 145 | 20 r8 = mul_f32 r8 r3 |
| 146 | 21 r8 = round r8 |
| 147 | 22 r8 = pack r5 r8 8 |
| 148 | 23 r5 = shr_i32 r4 16 |
| 149 | 24 r5 = bit_and r1 r5 |
| 150 | 25 r5 = to_f32 r5 |
| 151 | 26 r5 = mul_f32 r0 r5 |
| 152 | 27 r5 = mul_f32 r5 r7 |
| 153 | 28 r5 = mul_f32 r5 r3 |
| 154 | 29 r5 = round r5 |
| 155 | 30 r4 = shr_i32 r4 24 |
| 156 | 31 r4 = to_f32 r4 |
| 157 | 32 r4 = mul_f32 r0 r4 |
| 158 | 33 r6 = mad_f32 r4 r7 r6 |
| 159 | 34 r6 = mul_f32 r6 r3 |
| 160 | 35 r6 = round r6 |
| 161 | 36 r6 = pack r5 r6 8 |
| 162 | 37 r6 = pack r8 r6 16 |
| 163 | 38 store32 arg(1) r6 |
| 164 | |
| 165 | G8 over A8 |
| 166 | 11 values (originally 15): |
| 167 | ↑ v0 = splat 3F800000 (1) |
| 168 | ↑ v1 = splat 0 (0) |
| 169 | ↑ v2 = splat 3B808081 (0.0039215689) |
| 170 | v3 = load8 arg(1) |
| 171 | v4 = to_f32 v3 |
| 172 | v5 = mul_f32 v2 v4 |
| 173 | v6 = mad_f32 v5 v1 v0 |
| 174 | ↑ v7 = splat 437F0000 (255) |
| 175 | v8 = mul_f32 v6 v7 |
| 176 | v9 = round v8 |
| 177 | store8 arg(1) v9 |
| 178 | |
| 179 | 5 registers, 11 instructions: |
| 180 | 0 r0 = splat 3F800000 (1) |
| 181 | 1 r1 = splat 0 (0) |
| 182 | 2 r2 = splat 3B808081 (0.0039215689) |
| 183 | 3 r3 = splat 437F0000 (255) |
| 184 | loop: |
| 185 | 4 r4 = load8 arg(1) |
| 186 | 5 r4 = to_f32 r4 |
| 187 | 6 r4 = mul_f32 r2 r4 |
| 188 | 7 r4 = mad_f32 r4 r1 r0 |
| 189 | 8 r4 = mul_f32 r4 r3 |
| 190 | 9 r4 = round r4 |
| 191 | 10 store8 arg(1) r4 |
| 192 | |
| 193 | G8 over G8 |
| 194 | 19 values (originally 20): |
| 195 | ↑ v0 = splat 3B808081 (0.0039215689) |
| 196 | v1 = load8 arg(0) |
| 197 | v2 = to_f32 v1 |
| 198 | v3 = mul_f32 v0 v2 |
| Mike Klein | a6434a5 | 2020-01-08 14:06:52 -0600 | [diff] [blame] | 199 | v4 = load8 arg(1) |
| 200 | v5 = to_f32 v4 |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 201 | v6 = mul_f32 v0 v5 |
| 202 | ↑ v7 = splat 0 (0) |
| 203 | v8 = mad_f32 v6 v7 v3 |
| 204 | ↑ v9 = splat 3E59B3D0 (0.21259999) |
| 205 | ↑ v10 = splat 3F371759 (0.71520001) |
| 206 | ↑ v11 = splat 3D93DD98 (0.0722) |
| 207 | v12 = mul_f32 v8 v11 |
| 208 | v13 = mad_f32 v8 v10 v12 |
| 209 | v14 = mad_f32 v8 v9 v13 |
| 210 | ↑ v15 = splat 437F0000 (255) |
| 211 | v16 = mul_f32 v14 v15 |
| 212 | v17 = round v16 |
| 213 | store8 arg(1) v17 |
| Mike Klein | 8c1e0ef | 2019-11-12 09:07:23 -0600 | [diff] [blame] | 214 | |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 215 | 8 registers, 19 instructions: |
| 216 | 0 r0 = splat 3B808081 (0.0039215689) |
| 217 | 1 r1 = splat 0 (0) |
| 218 | 2 r2 = splat 3E59B3D0 (0.21259999) |
| 219 | 3 r3 = splat 3F371759 (0.71520001) |
| 220 | 4 r4 = splat 3D93DD98 (0.0722) |
| 221 | 5 r5 = splat 437F0000 (255) |
| 222 | loop: |
| 223 | 6 r6 = load8 arg(0) |
| 224 | 7 r6 = to_f32 r6 |
| 225 | 8 r6 = mul_f32 r0 r6 |
| 226 | 9 r7 = load8 arg(1) |
| 227 | 10 r7 = to_f32 r7 |
| 228 | 11 r7 = mul_f32 r0 r7 |
| 229 | 12 r6 = mad_f32 r7 r1 r6 |
| 230 | 13 r7 = mul_f32 r6 r4 |
| 231 | 14 r7 = mad_f32 r6 r3 r7 |
| 232 | 15 r7 = mad_f32 r6 r2 r7 |
| 233 | 16 r7 = mul_f32 r7 r5 |
| 234 | 17 r7 = round r7 |
| 235 | 18 store8 arg(1) r7 |
| 236 | |
| 237 | G8 over RGBA_8888 |
| 238 | 39 values (originally 39): |
| 239 | ↑ v0 = splat 3B808081 (0.0039215689) |
| 240 | v1 = load8 arg(0) |
| 241 | v2 = to_f32 v1 |
| 242 | v3 = mul_f32 v0 v2 |
| 243 | v4 = load32 arg(1) |
| 244 | ↑ v5 = splat FF (3.5733111e-43) |
| 245 | v6 = bit_and v5 v4 |
| 246 | v7 = to_f32 v6 |
| 247 | v8 = mul_f32 v0 v7 |
| 248 | ↑ v9 = splat 0 (0) |
| 249 | v10 = mad_f32 v8 v9 v3 |
| 250 | ↑ v11 = splat 437F0000 (255) |
| 251 | v12 = mul_f32 v10 v11 |
| 252 | v13 = round v12 |
| 253 | v14 = shr_i32 v4 8 |
| 254 | v15 = bit_and v5 v14 |
| 255 | v16 = to_f32 v15 |
| 256 | v17 = mul_f32 v0 v16 |
| 257 | v18 = mad_f32 v17 v9 v3 |
| 258 | v19 = mul_f32 v18 v11 |
| 259 | v20 = round v19 |
| 260 | v21 = pack v13 v20 8 |
| 261 | v22 = shr_i32 v4 16 |
| 262 | v23 = bit_and v5 v22 |
| 263 | v24 = to_f32 v23 |
| 264 | v25 = mul_f32 v0 v24 |
| 265 | v26 = mad_f32 v25 v9 v3 |
| 266 | v27 = mul_f32 v26 v11 |
| 267 | v28 = round v27 |
| 268 | ↑ v29 = splat 3F800000 (1) |
| 269 | v30 = shr_i32 v4 24 |
| 270 | v31 = to_f32 v30 |
| 271 | v32 = mul_f32 v0 v31 |
| 272 | v33 = mad_f32 v32 v9 v29 |
| 273 | v34 = mul_f32 v33 v11 |
| 274 | v35 = round v34 |
| 275 | v36 = pack v28 v35 8 |
| 276 | v37 = pack v21 v36 16 |
| 277 | store32 arg(1) v37 |
| 278 | |
| 279 | 9 registers, 39 instructions: |
| 280 | 0 r0 = splat 3B808081 (0.0039215689) |
| 281 | 1 r1 = splat FF (3.5733111e-43) |
| 282 | 2 r2 = splat 0 (0) |
| 283 | 3 r3 = splat 437F0000 (255) |
| 284 | 4 r4 = splat 3F800000 (1) |
| 285 | loop: |
| 286 | 5 r5 = load8 arg(0) |
| 287 | 6 r5 = to_f32 r5 |
| 288 | 7 r5 = mul_f32 r0 r5 |
| 289 | 8 r6 = load32 arg(1) |
| 290 | 9 r7 = bit_and r1 r6 |
| 291 | 10 r7 = to_f32 r7 |
| 292 | 11 r7 = mul_f32 r0 r7 |
| 293 | 12 r7 = mad_f32 r7 r2 r5 |
| 294 | 13 r7 = mul_f32 r7 r3 |
| 295 | 14 r7 = round r7 |
| 296 | 15 r8 = shr_i32 r6 8 |
| 297 | 16 r8 = bit_and r1 r8 |
| 298 | 17 r8 = to_f32 r8 |
| 299 | 18 r8 = mul_f32 r0 r8 |
| 300 | 19 r8 = mad_f32 r8 r2 r5 |
| 301 | 20 r8 = mul_f32 r8 r3 |
| 302 | 21 r8 = round r8 |
| 303 | 22 r8 = pack r7 r8 8 |
| 304 | 23 r7 = shr_i32 r6 16 |
| 305 | 24 r7 = bit_and r1 r7 |
| 306 | 25 r7 = to_f32 r7 |
| 307 | 26 r7 = mul_f32 r0 r7 |
| 308 | 27 r5 = mad_f32 r7 r2 r5 |
| 309 | 28 r5 = mul_f32 r5 r3 |
| 310 | 29 r5 = round r5 |
| 311 | 30 r6 = shr_i32 r6 24 |
| 312 | 31 r6 = to_f32 r6 |
| 313 | 32 r6 = mul_f32 r0 r6 |
| 314 | 33 r6 = mad_f32 r6 r2 r4 |
| 315 | 34 r6 = mul_f32 r6 r3 |
| 316 | 35 r6 = round r6 |
| 317 | 36 r6 = pack r5 r6 8 |
| 318 | 37 r6 = pack r8 r6 16 |
| 319 | 38 store32 arg(1) r6 |
| 320 | |
| 321 | RGBA_8888 over A8 |
| 322 | 15 values (originally 31): |
| 323 | ↑ v0 = splat 3B808081 (0.0039215689) |
| 324 | v1 = load32 arg(0) |
| 325 | v2 = shr_i32 v1 24 |
| 326 | v3 = to_f32 v2 |
| 327 | v4 = mul_f32 v0 v3 |
| 328 | v5 = load8 arg(1) |
| 329 | v6 = to_f32 v5 |
| 330 | v7 = mul_f32 v0 v6 |
| 331 | ↑ v8 = splat 3F800000 (1) |
| 332 | v9 = sub_f32 v8 v4 |
| 333 | v10 = mad_f32 v7 v9 v4 |
| 334 | ↑ v11 = splat 437F0000 (255) |
| 335 | v12 = mul_f32 v10 v11 |
| 336 | v13 = round v12 |
| 337 | store8 arg(1) v13 |
| 338 | |
| 339 | 6 registers, 15 instructions: |
| 340 | 0 r0 = splat 3B808081 (0.0039215689) |
| 341 | 1 r1 = splat 3F800000 (1) |
| 342 | 2 r2 = splat 437F0000 (255) |
| Mike Klein | a630732 | 2019-06-07 15:44:26 -0500 | [diff] [blame] | 343 | loop: |
| Mike Klein | a6434a5 | 2020-01-08 14:06:52 -0600 | [diff] [blame] | 344 | 3 r3 = load32 arg(0) |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 345 | 4 r3 = shr_i32 r3 24 |
| 346 | 5 r3 = to_f32 r3 |
| 347 | 6 r3 = mul_f32 r0 r3 |
| 348 | 7 r4 = load8 arg(1) |
| 349 | 8 r4 = to_f32 r4 |
| 350 | 9 r4 = mul_f32 r0 r4 |
| 351 | 10 r5 = sub_f32 r1 r3 |
| 352 | 11 r3 = mad_f32 r4 r5 r3 |
| 353 | 12 r3 = mul_f32 r3 r2 |
| 354 | 13 r3 = round r3 |
| 355 | 14 store8 arg(1) r3 |
| 356 | |
| 357 | RGBA_8888 over G8 |
| 358 | 35 values (originally 36): |
| 359 | ↑ v0 = splat 3B808081 (0.0039215689) |
| 360 | v1 = load32 arg(0) |
| 361 | ↑ v2 = splat FF (3.5733111e-43) |
| 362 | v3 = bit_and v2 v1 |
| 363 | v4 = to_f32 v3 |
| 364 | v5 = mul_f32 v0 v4 |
| 365 | v6 = load8 arg(1) |
| 366 | v7 = to_f32 v6 |
| 367 | v8 = mul_f32 v0 v7 |
| 368 | v9 = shr_i32 v1 24 |
| 369 | v10 = to_f32 v9 |
| 370 | v11 = mul_f32 v0 v10 |
| 371 | ↑ v12 = splat 3F800000 (1) |
| 372 | v13 = sub_f32 v12 v11 |
| 373 | v14 = mad_f32 v8 v13 v5 |
| 374 | ↑ v15 = splat 3E59B3D0 (0.21259999) |
| 375 | v16 = shr_i32 v1 8 |
| 376 | v17 = bit_and v2 v16 |
| 377 | v18 = to_f32 v17 |
| 378 | v19 = mul_f32 v0 v18 |
| 379 | v20 = mad_f32 v8 v13 v19 |
| 380 | ↑ v21 = splat 3F371759 (0.71520001) |
| 381 | v22 = shr_i32 v1 16 |
| 382 | v23 = bit_and v2 v22 |
| 383 | v24 = to_f32 v23 |
| 384 | v25 = mul_f32 v0 v24 |
| 385 | v26 = mad_f32 v8 v13 v25 |
| 386 | ↑ v27 = splat 3D93DD98 (0.0722) |
| 387 | v28 = mul_f32 v26 v27 |
| 388 | v29 = mad_f32 v20 v21 v28 |
| 389 | v30 = mad_f32 v14 v15 v29 |
| 390 | ↑ v31 = splat 437F0000 (255) |
| 391 | v32 = mul_f32 v30 v31 |
| 392 | v33 = round v32 |
| 393 | store8 arg(1) v33 |
| 394 | |
| 395 | 12 registers, 35 instructions: |
| 396 | 0 r0 = splat 3B808081 (0.0039215689) |
| 397 | 1 r1 = splat FF (3.5733111e-43) |
| 398 | 2 r2 = splat 3F800000 (1) |
| 399 | 3 r3 = splat 3E59B3D0 (0.21259999) |
| 400 | 4 r4 = splat 3F371759 (0.71520001) |
| 401 | 5 r5 = splat 3D93DD98 (0.0722) |
| 402 | 6 r6 = splat 437F0000 (255) |
| 403 | loop: |
| 404 | 7 r7 = load32 arg(0) |
| 405 | 8 r8 = bit_and r1 r7 |
| 406 | 9 r8 = to_f32 r8 |
| 407 | 10 r8 = mul_f32 r0 r8 |
| 408 | 11 r9 = load8 arg(1) |
| 409 | 12 r9 = to_f32 r9 |
| 410 | 13 r9 = mul_f32 r0 r9 |
| 411 | 14 r10 = shr_i32 r7 24 |
| 412 | 15 r10 = to_f32 r10 |
| 413 | 16 r10 = mul_f32 r0 r10 |
| 414 | 17 r10 = sub_f32 r2 r10 |
| 415 | 18 r8 = mad_f32 r9 r10 r8 |
| 416 | 19 r11 = shr_i32 r7 8 |
| 417 | 20 r11 = bit_and r1 r11 |
| 418 | 21 r11 = to_f32 r11 |
| 419 | 22 r11 = mul_f32 r0 r11 |
| 420 | 23 r11 = mad_f32 r9 r10 r11 |
| 421 | 24 r7 = shr_i32 r7 16 |
| 422 | 25 r7 = bit_and r1 r7 |
| 423 | 26 r7 = to_f32 r7 |
| 424 | 27 r7 = mul_f32 r0 r7 |
| 425 | 28 r7 = mad_f32 r9 r10 r7 |
| 426 | 29 r7 = mul_f32 r7 r5 |
| 427 | 30 r7 = mad_f32 r11 r4 r7 |
| 428 | 31 r7 = mad_f32 r8 r3 r7 |
| 429 | 32 r7 = mul_f32 r7 r6 |
| 430 | 33 r7 = round r7 |
| 431 | 34 store8 arg(1) r7 |
| Mike Klein | 8c1e0ef | 2019-11-12 09:07:23 -0600 | [diff] [blame] | 432 | |
| 433 | RGBA_8888 over RGBA_8888 |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 434 | 51 values (originally 51): |
| 435 | ↑ v0 = splat 3B808081 (0.0039215689) |
| 436 | v1 = load32 arg(0) |
| 437 | ↑ v2 = splat FF (3.5733111e-43) |
| 438 | v3 = bit_and v2 v1 |
| 439 | v4 = to_f32 v3 |
| 440 | v5 = mul_f32 v0 v4 |
| 441 | v6 = load32 arg(1) |
| 442 | v7 = bit_and v2 v6 |
| 443 | v8 = to_f32 v7 |
| 444 | v9 = mul_f32 v0 v8 |
| 445 | v10 = shr_i32 v1 24 |
| 446 | v11 = to_f32 v10 |
| 447 | v12 = mul_f32 v0 v11 |
| 448 | ↑ v13 = splat 3F800000 (1) |
| 449 | v14 = sub_f32 v13 v12 |
| 450 | v15 = mad_f32 v9 v14 v5 |
| 451 | ↑ v16 = splat 437F0000 (255) |
| 452 | v17 = mul_f32 v15 v16 |
| 453 | v18 = round v17 |
| 454 | v19 = shr_i32 v1 8 |
| 455 | v20 = bit_and v2 v19 |
| 456 | v21 = to_f32 v20 |
| 457 | v22 = mul_f32 v0 v21 |
| 458 | v23 = shr_i32 v6 8 |
| 459 | v24 = bit_and v2 v23 |
| 460 | v25 = to_f32 v24 |
| 461 | v26 = mul_f32 v0 v25 |
| 462 | v27 = mad_f32 v26 v14 v22 |
| 463 | v28 = mul_f32 v27 v16 |
| 464 | v29 = round v28 |
| 465 | v30 = pack v18 v29 8 |
| 466 | v31 = shr_i32 v1 16 |
| 467 | v32 = bit_and v2 v31 |
| 468 | v33 = to_f32 v32 |
| 469 | v34 = mul_f32 v0 v33 |
| 470 | v35 = shr_i32 v6 16 |
| 471 | v36 = bit_and v2 v35 |
| 472 | v37 = to_f32 v36 |
| 473 | v38 = mul_f32 v0 v37 |
| 474 | v39 = mad_f32 v38 v14 v34 |
| 475 | v40 = mul_f32 v39 v16 |
| 476 | v41 = round v40 |
| 477 | v42 = shr_i32 v6 24 |
| 478 | v43 = to_f32 v42 |
| 479 | v44 = mul_f32 v0 v43 |
| 480 | v45 = mad_f32 v44 v14 v12 |
| 481 | v46 = mul_f32 v45 v16 |
| 482 | v47 = round v46 |
| 483 | v48 = pack v41 v47 8 |
| 484 | v49 = pack v30 v48 16 |
| 485 | store32 arg(1) v49 |
| Mike Klein | 8c1e0ef | 2019-11-12 09:07:23 -0600 | [diff] [blame] | 486 | |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 487 | 11 registers, 51 instructions: |
| 488 | 0 r0 = splat 3B808081 (0.0039215689) |
| 489 | 1 r1 = splat FF (3.5733111e-43) |
| 490 | 2 r2 = splat 3F800000 (1) |
| 491 | 3 r3 = splat 437F0000 (255) |
| Mike Klein | 8c1e0ef | 2019-11-12 09:07:23 -0600 | [diff] [blame] | 492 | loop: |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 493 | 4 r4 = load32 arg(0) |
| 494 | 5 r5 = bit_and r1 r4 |
| 495 | 6 r5 = to_f32 r5 |
| 496 | 7 r5 = mul_f32 r0 r5 |
| 497 | 8 r6 = load32 arg(1) |
| 498 | 9 r7 = bit_and r1 r6 |
| 499 | 10 r7 = to_f32 r7 |
| 500 | 11 r7 = mul_f32 r0 r7 |
| 501 | 12 r8 = shr_i32 r4 24 |
| 502 | 13 r8 = to_f32 r8 |
| 503 | 14 r8 = mul_f32 r0 r8 |
| 504 | 15 r9 = sub_f32 r2 r8 |
| 505 | 16 r5 = mad_f32 r7 r9 r5 |
| 506 | 17 r5 = mul_f32 r5 r3 |
| 507 | 18 r5 = round r5 |
| 508 | 19 r7 = shr_i32 r4 8 |
| 509 | 20 r7 = bit_and r1 r7 |
| 510 | 21 r7 = to_f32 r7 |
| 511 | 22 r7 = mul_f32 r0 r7 |
| 512 | 23 r10 = shr_i32 r6 8 |
| 513 | 24 r10 = bit_and r1 r10 |
| 514 | 25 r10 = to_f32 r10 |
| 515 | 26 r10 = mul_f32 r0 r10 |
| 516 | 27 r7 = mad_f32 r10 r9 r7 |
| 517 | 28 r7 = mul_f32 r7 r3 |
| 518 | 29 r7 = round r7 |
| 519 | 30 r7 = pack r5 r7 8 |
| 520 | 31 r4 = shr_i32 r4 16 |
| 521 | 32 r4 = bit_and r1 r4 |
| 522 | 33 r4 = to_f32 r4 |
| 523 | 34 r4 = mul_f32 r0 r4 |
| 524 | 35 r5 = shr_i32 r6 16 |
| 525 | 36 r5 = bit_and r1 r5 |
| 526 | 37 r5 = to_f32 r5 |
| 527 | 38 r5 = mul_f32 r0 r5 |
| 528 | 39 r4 = mad_f32 r5 r9 r4 |
| 529 | 40 r4 = mul_f32 r4 r3 |
| 530 | 41 r4 = round r4 |
| 531 | 42 r6 = shr_i32 r6 24 |
| 532 | 43 r6 = to_f32 r6 |
| 533 | 44 r6 = mul_f32 r0 r6 |
| 534 | 45 r8 = mad_f32 r6 r9 r8 |
| 535 | 46 r8 = mul_f32 r8 r3 |
| 536 | 47 r8 = round r8 |
| 537 | 48 r8 = pack r4 r8 8 |
| 538 | 49 r8 = pack r7 r8 16 |
| 539 | 50 store32 arg(1) r8 |
| Mike Klein | 267f507 | 2019-06-03 16:27:46 -0500 | [diff] [blame] | 540 | |
| Mike Klein | 397fc88 | 2019-06-20 11:37:10 -0500 | [diff] [blame] | 541 | I32 (Naive) 8888 over 8888 |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 542 | 33 values (originally 33): |
| Mike Klein | c2fb3b4 | 2019-07-17 12:09:09 -0500 | [diff] [blame] | 543 | v0 = load32 arg(0) |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 544 | ↑ v1 = splat FF (3.5733111e-43) |
| 545 | v2 = bit_and v1 v0 |
| 546 | v3 = load32 arg(1) |
| 547 | v4 = bit_and v1 v3 |
| 548 | v5 = shr_i32 v0 24 |
| 549 | ↑ v6 = splat 100 (3.5873241e-43) |
| 550 | v7 = sub_i32 v6 v5 |
| 551 | v8 = mul_i32 v4 v7 |
| 552 | v9 = shr_i32 v8 8 |
| 553 | v10 = add_i32 v2 v9 |
| 554 | v11 = shr_i32 v0 8 |
| 555 | v12 = bit_and v1 v11 |
| 556 | v13 = shr_i32 v3 8 |
| 557 | v14 = bit_and v1 v13 |
| 558 | v15 = mul_i32 v14 v7 |
| 559 | v16 = shr_i32 v15 8 |
| 560 | v17 = add_i32 v12 v16 |
| 561 | v18 = pack v10 v17 8 |
| 562 | v19 = shr_i32 v0 16 |
| 563 | v20 = bit_and v1 v19 |
| 564 | v21 = shr_i32 v3 16 |
| 565 | v22 = bit_and v1 v21 |
| 566 | v23 = mul_i32 v22 v7 |
| 567 | v24 = shr_i32 v23 8 |
| 568 | v25 = add_i32 v20 v24 |
| 569 | v26 = shr_i32 v3 24 |
| 570 | v27 = mul_i32 v26 v7 |
| 571 | v28 = shr_i32 v27 8 |
| 572 | v29 = add_i32 v5 v28 |
| 573 | v30 = pack v25 v29 8 |
| 574 | v31 = pack v18 v30 16 |
| 575 | store32 arg(1) v31 |
| Mike Klein | aab45b5 | 2019-07-02 15:39:23 -0500 | [diff] [blame] | 576 | |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 577 | 9 registers, 33 instructions: |
| 578 | 0 r0 = splat FF (3.5733111e-43) |
| 579 | 1 r1 = splat 100 (3.5873241e-43) |
| Mike Klein | 397fc88 | 2019-06-20 11:37:10 -0500 | [diff] [blame] | 580 | loop: |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 581 | 2 r2 = load32 arg(0) |
| 582 | 3 r3 = bit_and r0 r2 |
| 583 | 4 r4 = load32 arg(1) |
| 584 | 5 r5 = bit_and r0 r4 |
| 585 | 6 r6 = shr_i32 r2 24 |
| 586 | 7 r7 = sub_i32 r1 r6 |
| 587 | 8 r5 = mul_i32 r5 r7 |
| 588 | 9 r5 = shr_i32 r5 8 |
| 589 | 10 r5 = add_i32 r3 r5 |
| 590 | 11 r3 = shr_i32 r2 8 |
| 591 | 12 r3 = bit_and r0 r3 |
| 592 | 13 r8 = shr_i32 r4 8 |
| 593 | 14 r8 = bit_and r0 r8 |
| 594 | 15 r8 = mul_i32 r8 r7 |
| 595 | 16 r8 = shr_i32 r8 8 |
| 596 | 17 r8 = add_i32 r3 r8 |
| 597 | 18 r8 = pack r5 r8 8 |
| 598 | 19 r2 = shr_i32 r2 16 |
| 599 | 20 r2 = bit_and r0 r2 |
| 600 | 21 r5 = shr_i32 r4 16 |
| 601 | 22 r5 = bit_and r0 r5 |
| 602 | 23 r5 = mul_i32 r5 r7 |
| 603 | 24 r5 = shr_i32 r5 8 |
| 604 | 25 r5 = add_i32 r2 r5 |
| 605 | 26 r4 = shr_i32 r4 24 |
| 606 | 27 r7 = mul_i32 r4 r7 |
| 607 | 28 r7 = shr_i32 r7 8 |
| 608 | 29 r7 = add_i32 r6 r7 |
| 609 | 30 r7 = pack r5 r7 8 |
| 610 | 31 r7 = pack r8 r7 16 |
| 611 | 32 store32 arg(1) r7 |
| Mike Klein | 397fc88 | 2019-06-20 11:37:10 -0500 | [diff] [blame] | 612 | |
| Mike Klein | 7b7077c | 2019-06-03 17:10:59 -0500 | [diff] [blame] | 613 | I32 8888 over 8888 |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 614 | 29 values (originally 29): |
| Mike Klein | c2fb3b4 | 2019-07-17 12:09:09 -0500 | [diff] [blame] | 615 | v0 = load32 arg(0) |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 616 | ↑ v1 = splat FF (3.5733111e-43) |
| 617 | v2 = bit_and v0 v1 |
| 618 | v3 = load32 arg(1) |
| 619 | v4 = bit_and v3 v1 |
| 620 | v5 = shr_i32 v0 24 |
| 621 | ↑ v6 = splat 100 (3.5873241e-43) |
| 622 | v7 = sub_i32 v6 v5 |
| 623 | v8 = mul_i16x2 v4 v7 |
| 624 | v9 = shr_i32 v8 8 |
| 625 | v10 = add_i32 v2 v9 |
| 626 | v11 = bytes v0 2 |
| 627 | v12 = bytes v3 2 |
| 628 | v13 = mul_i16x2 v12 v7 |
| 629 | v14 = shr_i32 v13 8 |
| 630 | v15 = add_i32 v11 v14 |
| 631 | v16 = pack v10 v15 8 |
| 632 | v17 = bytes v0 3 |
| 633 | v18 = bytes v3 3 |
| 634 | v19 = mul_i16x2 v18 v7 |
| 635 | v20 = shr_i32 v19 8 |
| 636 | v21 = add_i32 v17 v20 |
| 637 | v22 = shr_i32 v3 24 |
| 638 | v23 = mul_i16x2 v22 v7 |
| 639 | v24 = shr_i32 v23 8 |
| 640 | v25 = add_i32 v5 v24 |
| 641 | v26 = pack v21 v25 8 |
| 642 | v27 = pack v16 v26 16 |
| 643 | store32 arg(1) v27 |
| Mike Klein | aab45b5 | 2019-07-02 15:39:23 -0500 | [diff] [blame] | 644 | |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 645 | 9 registers, 29 instructions: |
| 646 | 0 r0 = splat FF (3.5733111e-43) |
| 647 | 1 r1 = splat 100 (3.5873241e-43) |
| Mike Klein | 754bad3 | 2019-06-05 10:47:46 -0500 | [diff] [blame] | 648 | loop: |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 649 | 2 r2 = load32 arg(0) |
| 650 | 3 r3 = bit_and r2 r0 |
| 651 | 4 r4 = load32 arg(1) |
| 652 | 5 r5 = bit_and r4 r0 |
| 653 | 6 r6 = shr_i32 r2 24 |
| 654 | 7 r7 = sub_i32 r1 r6 |
| 655 | 8 r5 = mul_i16x2 r5 r7 |
| 656 | 9 r5 = shr_i32 r5 8 |
| 657 | 10 r5 = add_i32 r3 r5 |
| 658 | 11 r3 = bytes r2 2 |
| 659 | 12 r8 = bytes r4 2 |
| 660 | 13 r8 = mul_i16x2 r8 r7 |
| 661 | 14 r8 = shr_i32 r8 8 |
| 662 | 15 r8 = add_i32 r3 r8 |
| 663 | 16 r8 = pack r5 r8 8 |
| 664 | 17 r2 = bytes r2 3 |
| 665 | 18 r5 = bytes r4 3 |
| 666 | 19 r5 = mul_i16x2 r5 r7 |
| 667 | 20 r5 = shr_i32 r5 8 |
| 668 | 21 r5 = add_i32 r2 r5 |
| 669 | 22 r4 = shr_i32 r4 24 |
| 670 | 23 r7 = mul_i16x2 r4 r7 |
| 671 | 24 r7 = shr_i32 r7 8 |
| 672 | 25 r7 = add_i32 r6 r7 |
| 673 | 26 r7 = pack r5 r7 8 |
| 674 | 27 r7 = pack r8 r7 16 |
| 675 | 28 store32 arg(1) r7 |
| Mike Klein | 821f5e8 | 2019-06-13 10:56:51 -0500 | [diff] [blame] | 676 | |
| 677 | I32 (SWAR) 8888 over 8888 |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 678 | 15 values (originally 15): |
| Mike Klein | c2fb3b4 | 2019-07-17 12:09:09 -0500 | [diff] [blame] | 679 | v0 = load32 arg(0) |
| 680 | v1 = bytes v0 404 |
| Mike Klein | 5e533c9 | 2019-07-22 13:44:54 -0500 | [diff] [blame] | 681 | ↑ v2 = splat 1000100 (2.3510604e-38) |
| Mike Klein | c2fb3b4 | 2019-07-17 12:09:09 -0500 | [diff] [blame] | 682 | v3 = sub_i16x2 v2 v1 |
| 683 | v4 = load32 arg(1) |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 684 | ↑ v5 = splat FF00FF (2.3418409e-38) |
| 685 | v6 = bit_and v4 v5 |
| 686 | v7 = mul_i16x2 v6 v3 |
| 687 | v8 = shr_i16x2 v7 8 |
| 688 | v9 = shr_i16x2 v4 8 |
| 689 | v10 = mul_i16x2 v9 v3 |
| 690 | v11 = bit_clear v10 v5 |
| 691 | v12 = bit_or v8 v11 |
| 692 | v13 = add_i32 v0 v12 |
| 693 | store32 arg(1) v13 |
| Mike Klein | aab45b5 | 2019-07-02 15:39:23 -0500 | [diff] [blame] | 694 | |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 695 | 6 registers, 15 instructions: |
| Mike Klein | b5c4355 | 2020-01-07 11:39:30 -0600 | [diff] [blame] | 696 | 0 r0 = splat 1000100 (2.3510604e-38) |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 697 | 1 r1 = splat FF00FF (2.3418409e-38) |
| Mike Klein | 821f5e8 | 2019-06-13 10:56:51 -0500 | [diff] [blame] | 698 | loop: |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 699 | 2 r2 = load32 arg(0) |
| 700 | 3 r3 = bytes r2 404 |
| 701 | 4 r3 = sub_i16x2 r0 r3 |
| 702 | 5 r4 = load32 arg(1) |
| 703 | 6 r5 = bit_and r4 r1 |
| 704 | 7 r5 = mul_i16x2 r5 r3 |
| 705 | 8 r5 = shr_i16x2 r5 8 |
| 706 | 9 r4 = shr_i16x2 r4 8 |
| 707 | 10 r3 = mul_i16x2 r4 r3 |
| 708 | 11 r3 = bit_clear r3 r1 |
| 709 | 12 r3 = bit_or r5 r3 |
| 710 | 13 r3 = add_i32 r2 r3 |
| 711 | 14 store32 arg(1) r3 |
| Mike Klein | 7b7077c | 2019-06-03 17:10:59 -0500 | [diff] [blame] | 712 | |
| Mike Klein | ed9b1f1 | 2020-02-06 13:02:32 -0600 | [diff] [blame] | 713 | 6 values (originally 6): |
| Mike Klein | 0f61c12 | 2019-10-16 10:46:01 -0500 | [diff] [blame] | 714 | ↟ v0 = splat 1 (1.4012985e-45) |
| 715 | ↟ v1 = splat 2 (2.8025969e-45) |
| Mike Klein | f996311 | 2019-08-08 15:13:25 -0400 | [diff] [blame] | 716 | ↑ v2 = add_i32 v0 v1 |
| 717 | v3 = load32 arg(0) |
| 718 | v4 = mul_i32 v3 v2 |
| 719 | store32 arg(0) v4 |
| 720 | |
| 721 | 2 registers, 6 instructions: |
| Mike Klein | b5c4355 | 2020-01-07 11:39:30 -0600 | [diff] [blame] | 722 | 0 r0 = splat 1 (1.4012985e-45) |
| 723 | 1 r1 = splat 2 (2.8025969e-45) |
| 724 | 2 r1 = add_i32 r0 r1 |
| Mike Klein | f996311 | 2019-08-08 15:13:25 -0400 | [diff] [blame] | 725 | loop: |
| Mike Klein | b5c4355 | 2020-01-07 11:39:30 -0600 | [diff] [blame] | 726 | 3 r0 = load32 arg(0) |
| 727 | 4 r0 = mul_i32 r0 r1 |
| 728 | 5 store32 arg(0) r0 |
| Mike Klein | f996311 | 2019-08-08 15:13:25 -0400 | [diff] [blame] | 729 | |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 730 | 23 values (originally 23): |
| 731 | ↑ v0 = splat FF (3.5733111e-43) |
| 732 | v1 = load32 arg(0) |
| 733 | v2 = bit_and v0 v1 |
| 734 | v3 = load32 arg(1) |
| 735 | v4 = bit_and v0 v3 |
| 736 | v5 = add_i32 v2 v4 |
| 737 | v6 = shr_i32 v1 8 |
| 738 | v7 = bit_and v0 v6 |
| 739 | v8 = shr_i32 v3 8 |
| 740 | v9 = bit_and v0 v8 |
| 741 | v10 = add_i32 v7 v9 |
| 742 | v11 = pack v5 v10 8 |
| 743 | v12 = shr_i32 v1 16 |
| 744 | v13 = bit_and v0 v12 |
| 745 | v14 = shr_i32 v3 16 |
| 746 | v15 = bit_and v0 v14 |
| 747 | v16 = add_i32 v13 v15 |
| 748 | v17 = shr_i32 v1 24 |
| 749 | v18 = shr_i32 v3 24 |
| 750 | v19 = add_i32 v17 v18 |
| 751 | v20 = pack v16 v19 8 |
| 752 | v21 = pack v11 v20 16 |
| 753 | store32 arg(1) v21 |
| Mike Klein | d48488b | 2019-10-22 12:27:58 -0500 | [diff] [blame] | 754 | |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 755 | 6 registers, 23 instructions: |
| 756 | 0 r0 = splat FF (3.5733111e-43) |
| Mike Klein | d48488b | 2019-10-22 12:27:58 -0500 | [diff] [blame] | 757 | loop: |
| Mike Klein | 5cdeb39 | 2020-02-10 12:10:36 -0600 | [diff] [blame^] | 758 | 1 r1 = load32 arg(0) |
| 759 | 2 r2 = bit_and r0 r1 |
| 760 | 3 r3 = load32 arg(1) |
| 761 | 4 r4 = bit_and r0 r3 |
| 762 | 5 r4 = add_i32 r2 r4 |
| 763 | 6 r2 = shr_i32 r1 8 |
| 764 | 7 r2 = bit_and r0 r2 |
| 765 | 8 r5 = shr_i32 r3 8 |
| 766 | 9 r5 = bit_and r0 r5 |
| 767 | 10 r5 = add_i32 r2 r5 |
| 768 | 11 r5 = pack r4 r5 8 |
| 769 | 12 r4 = shr_i32 r1 16 |
| 770 | 13 r4 = bit_and r0 r4 |
| 771 | 14 r2 = shr_i32 r3 16 |
| 772 | 15 r2 = bit_and r0 r2 |
| 773 | 16 r2 = add_i32 r4 r2 |
| 774 | 17 r1 = shr_i32 r1 24 |
| 775 | 18 r3 = shr_i32 r3 24 |
| 776 | 19 r3 = add_i32 r1 r3 |
| 777 | 20 r3 = pack r2 r3 8 |
| 778 | 21 r3 = pack r5 r3 16 |
| 779 | 22 store32 arg(1) r3 |
| Mike Klein | d48488b | 2019-10-22 12:27:58 -0500 | [diff] [blame] | 780 | |