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//===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
//
// The Subzero Code Generator
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines properties of lowered x86-32 instructions in the
// form of x-macros.
//
//===----------------------------------------------------------------------===//
#ifndef SUBZERO_SRC_ICEINSTX8632_DEF
#define SUBZERO_SRC_ICEINSTX8632_DEF
// NOTE: esp is not considered isInt, to avoid register allocating it.
#define REGX8632_TABLE \
/* val, init, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP */ \
X(Reg_eax, = 0, "eax", "ax", "al", 1, 0, 0, 0, 1, 1, 0) \
X(Reg_ecx, = Reg_eax + 1, "ecx", "cx", "cl", 1, 0, 0, 0, 1, 1, 0) \
X(Reg_edx, = Reg_eax + 2, "edx", "dx", "dl", 1, 0, 0, 0, 1, 1, 0) \
X(Reg_ebx, = Reg_eax + 3, "ebx", "bx", "bl", 0, 1, 0, 0, 1, 1, 0) \
X(Reg_esp, = Reg_eax + 4, "esp", "sp", "" , 0, 0, 1, 0, 0, 0, 0) \
X(Reg_ebp, = Reg_eax + 5, "ebp", "bp", "" , 0, 1, 0, 1, 0, 1, 0) \
X(Reg_esi, = Reg_eax + 6, "esi", "si", "" , 0, 1, 0, 0, 0, 1, 0) \
X(Reg_edi, = Reg_eax + 7, "edi", "di", "" , 0, 1, 0, 0, 0, 1, 0) \
X(Reg_ah, = Reg_edi + 1, "???", "" , "ah", 0, 0, 0, 0, 1, 0, 0) \
X(Reg_xmm0, = Reg_ah + 1, "xmm0", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
//#define X(val, init, name, name16, name8, scratch, preserved, stackptr,
// frameptr, isI8, isInt, isFP)
// X86 segment registers.
#define SEG_REGX8632_TABLE \
/* enum value, name */ \
X(SegReg_CS, "cs") \
X(SegReg_DS, "ds") \
X(SegReg_ES, "es") \
X(SegReg_SS, "ss") \
X(SegReg_FS, "fs") \
X(SegReg_GS, "gs") \
//#define X(val, name)
#define ICEINSTX8632BR_TABLE \
/* enum value, opposite, dump, emit */ \
X(Br_a, Br_be, "a", "ja") \
X(Br_ae, Br_b, "ae", "jae") \
X(Br_b, Br_ae, "b", "jb") \
X(Br_be, Br_a, "be", "jbe") \
X(Br_e, Br_ne, "e", "je") \
X(Br_g, Br_le, "g", "jg") \
X(Br_ge, Br_l, "ge", "jge") \
X(Br_l, Br_ge, "l", "jl") \
X(Br_le, Br_g, "le", "jle") \
X(Br_ne, Br_e, "ne", "jne") \
X(Br_np, Br_p, "np", "jnp") \
X(Br_p, Br_np, "p", "jp") \
//#define X(tag, opp, dump, emit)
#define ICEINSTX8632CMPPS_TABLE \
/* enum value, emit */ \
X(Cmpps_eq, "eq") \
X(Cmpps_lt, "lt") \
X(Cmpps_le, "le") \
X(Cmpps_unord, "unord") \
X(Cmpps_neq, "neq") \
X(Cmpps_nlt, "nlt") \
X(Cmpps_nle, "nle") \
X(Cmpps_ord, "ord") \
//#define X(tag, emit)
#define ICETYPEX8632_TABLE \
/* tag, element type, cvt, sdss, pack, width */ \
X(IceType_void, IceType_void, "?" , "" , "" , "???") \
X(IceType_i1, IceType_void, "si", "" , "" , "byte ptr") \
X(IceType_i8, IceType_void, "si", "" , "" , "byte ptr") \
X(IceType_i16, IceType_void, "si", "" , "" , "word ptr") \
X(IceType_i32, IceType_void, "si", "" , "" , "dword ptr") \
X(IceType_i64, IceType_void, "si", "" , "" , "qword ptr") \
X(IceType_f32, IceType_void, "ss", "ss", "" , "dword ptr") \
X(IceType_f64, IceType_void, "sd", "sd", "" , "qword ptr") \
X(IceType_v4i1, IceType_i32 , "?" , "" , "d", "xmmword ptr") \
X(IceType_v8i1, IceType_i16 , "?" , "" , "w", "xmmword ptr") \
X(IceType_v16i1, IceType_i8 , "?" , "" , "b", "xmmword ptr") \
X(IceType_v16i8, IceType_i8 , "?" , "" , "b", "xmmword ptr") \
X(IceType_v8i16, IceType_i16 , "?" , "" , "w", "xmmword ptr") \
X(IceType_v4i32, IceType_i32 , "dq", "" , "d", "xmmword ptr") \
X(IceType_v4f32, IceType_f32 , "ps", "" , "" , "xmmword ptr") \
//#define X(tag, elementty, cvt, sdss, width)
#endif // SUBZERO_SRC_ICEINSTX8632_DEF