| Nicolas Capens | c07dc4b | 2018-08-06 14:20:45 -0400 | [diff] [blame] | 1 | // Copyright 2016 The SwiftShader Authors. All Rights Reserved. |
| 2 | // |
| 3 | // Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | // you may not use this file except in compliance with the License. |
| 5 | // You may obtain a copy of the License at |
| 6 | // |
| 7 | // http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | // |
| 9 | // Unless required by applicable law or agreed to in writing, software |
| 10 | // distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | // See the License for the specific language governing permissions and |
| 13 | // limitations under the License. |
| 14 | |
| 15 | #ifndef rr_CPUID_hpp |
| 16 | #define rr_CPUID_hpp |
| 17 | |
| 18 | namespace rr |
| 19 | { |
| 20 | #if !defined(__i386__) && defined(_M_IX86) |
| 21 | #define __i386__ 1 |
| 22 | #endif |
| 23 | |
| 24 | #if !defined(__x86_64__) && (defined(_M_AMD64) || defined (_M_X64)) |
| 25 | #define __x86_64__ 1 |
| 26 | #endif |
| 27 | |
| 28 | class CPUID |
| 29 | { |
| 30 | public: |
| 31 | static bool supportsMMX(); |
| 32 | static bool supportsCMOV(); |
| 33 | static bool supportsMMX2(); // MMX instructions added by SSE: pshufw, pmulhuw, pmovmskb, pavgw/b, pextrw, pinsrw, pmaxsw/ub, etc. |
| 34 | static bool supportsSSE(); |
| 35 | static bool supportsSSE2(); |
| 36 | static bool supportsSSE3(); |
| 37 | static bool supportsSSSE3(); |
| 38 | static bool supportsSSE4_1(); |
| 39 | |
| 40 | static void setEnableMMX(bool enable); |
| 41 | static void setEnableCMOV(bool enable); |
| 42 | static void setEnableSSE(bool enable); |
| 43 | static void setEnableSSE2(bool enable); |
| 44 | static void setEnableSSE3(bool enable); |
| 45 | static void setEnableSSSE3(bool enable); |
| 46 | static void setEnableSSE4_1(bool enable); |
| 47 | |
| 48 | private: |
| 49 | static bool MMX; |
| 50 | static bool CMOV; |
| 51 | static bool SSE; |
| 52 | static bool SSE2; |
| 53 | static bool SSE3; |
| 54 | static bool SSSE3; |
| 55 | static bool SSE4_1; |
| 56 | |
| 57 | static bool enableMMX; |
| 58 | static bool enableCMOV; |
| 59 | static bool enableSSE; |
| 60 | static bool enableSSE2; |
| 61 | static bool enableSSE3; |
| 62 | static bool enableSSSE3; |
| 63 | static bool enableSSE4_1; |
| 64 | |
| 65 | static bool detectMMX(); |
| 66 | static bool detectCMOV(); |
| 67 | static bool detectSSE(); |
| 68 | static bool detectSSE2(); |
| 69 | static bool detectSSE3(); |
| 70 | static bool detectSSSE3(); |
| 71 | static bool detectSSE4_1(); |
| 72 | }; |
| 73 | } |
| 74 | |
| 75 | namespace rr |
| 76 | { |
| 77 | inline bool CPUID::supportsMMX() |
| 78 | { |
| 79 | return MMX && enableMMX; |
| 80 | } |
| 81 | |
| 82 | inline bool CPUID::supportsCMOV() |
| 83 | { |
| 84 | return CMOV && enableCMOV; |
| 85 | } |
| 86 | |
| 87 | inline bool CPUID::supportsMMX2() |
| 88 | { |
| 89 | return supportsSSE(); // Coincides with 64-bit integer vector instructions supported by SSE |
| 90 | } |
| 91 | |
| 92 | inline bool CPUID::supportsSSE() |
| 93 | { |
| 94 | return SSE && enableSSE; |
| 95 | } |
| 96 | |
| 97 | inline bool CPUID::supportsSSE2() |
| 98 | { |
| 99 | return SSE2 && enableSSE2; |
| 100 | } |
| 101 | |
| 102 | inline bool CPUID::supportsSSE3() |
| 103 | { |
| 104 | return SSE3 && enableSSE3; |
| 105 | } |
| 106 | |
| 107 | inline bool CPUID::supportsSSSE3() |
| 108 | { |
| 109 | return SSSE3 && enableSSSE3; |
| 110 | } |
| 111 | |
| 112 | inline bool CPUID::supportsSSE4_1() |
| 113 | { |
| 114 | return SSE4_1 && enableSSE4_1; |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | #endif // rr_CPUID_hpp |