John Porto | aff4ccf | 2015-06-10 16:35:06 -0700 | [diff] [blame] | 1 | //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 2 | // |
| 3 | // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 4 | // for details. All rights reserved. Use of this source code is governed by a |
| 5 | // BSD-style license that can be found in the LICENSE file. |
| 6 | // |
| 7 | // Modified by the Subzero authors. |
| 8 | // |
| 9 | //===----------------------------------------------------------------------===// |
| 10 | // |
| 11 | // The Subzero Code Generator |
| 12 | // |
| 13 | // This file is distributed under the University of Illinois Open Source |
| 14 | // License. See LICENSE.TXT for details. |
| 15 | // |
| 16 | //===----------------------------------------------------------------------===// |
Andrew Scull | 9612d32 | 2015-07-06 14:53:25 -0700 | [diff] [blame] | 17 | /// |
| 18 | /// \file |
Jim Stichnoth | 92a6e5b | 2015-12-02 16:52:44 -0800 | [diff] [blame] | 19 | /// \brief Declares the Assembler class for ARM32. |
Andrew Scull | 9612d32 | 2015-07-06 14:53:25 -0700 | [diff] [blame] | 20 | /// |
Karl Schimpf | 85342a7 | 2015-10-13 09:49:31 -0700 | [diff] [blame] | 21 | /// Note: All references to ARM "section" documentation refers to the "ARM |
| 22 | /// Architecture Reference Manual, ARMv7-A and ARMv7-R edition". See: |
| 23 | /// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c |
| 24 | /// |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 25 | //===----------------------------------------------------------------------===// |
| 26 | |
John Porto | aff4ccf | 2015-06-10 16:35:06 -0700 | [diff] [blame] | 27 | #ifndef SUBZERO_SRC_ICEASSEMBLERARM32_H |
| 28 | #define SUBZERO_SRC_ICEASSEMBLERARM32_H |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 29 | |
John Porto | aff4ccf | 2015-06-10 16:35:06 -0700 | [diff] [blame] | 30 | #include "IceAssembler.h" |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 31 | #include "IceConditionCodesARM32.h" |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 32 | #include "IceDefs.h" |
| 33 | #include "IceFixups.h" |
Karl Schimpf | 85342a7 | 2015-10-13 09:49:31 -0700 | [diff] [blame] | 34 | #include "IceInstARM32.h" |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 35 | #include "IceRegistersARM32.h" |
| 36 | #include "IceTargetLowering.h" |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 37 | |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 38 | namespace Ice { |
Jan Voung | 90ccc3f | 2015-04-30 14:15:10 -0700 | [diff] [blame] | 39 | namespace ARM32 { |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 40 | |
Karl Schimpf | 7cb2db3 | 2015-10-29 14:04:12 -0700 | [diff] [blame] | 41 | /// Handles encoding of bottom/top 16 bits of an address using movw/movt. |
Karl Schimpf | 174531e | 2015-11-18 08:19:26 -0800 | [diff] [blame] | 42 | class MoveRelocatableFixup final : public AssemblerFixup { |
Karl Schimpf | 7cb2db3 | 2015-10-29 14:04:12 -0700 | [diff] [blame] | 43 | MoveRelocatableFixup &operator=(const MoveRelocatableFixup &) = delete; |
| 44 | MoveRelocatableFixup(const MoveRelocatableFixup &) = default; |
| 45 | |
| 46 | public: |
| 47 | MoveRelocatableFixup() = default; |
Karl Schimpf | 174531e | 2015-11-18 08:19:26 -0800 | [diff] [blame] | 48 | size_t emit(GlobalContext *Ctx, const Assembler &Asm) const final; |
John Porto | 6e8d3fa | 2016-02-04 10:35:20 -0800 | [diff] [blame] | 49 | void emitOffset(Assembler *Asm) const; |
Karl Schimpf | 174531e | 2015-11-18 08:19:26 -0800 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | /// Handles encoding of branch and link to global location. |
| 53 | class BlRelocatableFixup final : public AssemblerFixup { |
| 54 | BlRelocatableFixup(const BlRelocatableFixup &) = delete; |
| 55 | BlRelocatableFixup &operator=(const BlRelocatableFixup &) = delete; |
| 56 | |
| 57 | public: |
| 58 | BlRelocatableFixup() = default; |
| 59 | size_t emit(GlobalContext *Ctx, const Assembler &Asm) const final; |
John Porto | 6e8d3fa | 2016-02-04 10:35:20 -0800 | [diff] [blame] | 60 | void emitOffset(Assembler *Asm) const; |
Karl Schimpf | 7cb2db3 | 2015-10-29 14:04:12 -0700 | [diff] [blame] | 61 | }; |
| 62 | |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 63 | class AssemblerARM32 : public Assembler { |
| 64 | AssemblerARM32(const AssemblerARM32 &) = delete; |
| 65 | AssemblerARM32 &operator=(const AssemblerARM32 &) = delete; |
| 66 | |
| 67 | public: |
Karl Schimpf | bb0bacf | 2015-11-11 15:42:55 -0800 | [diff] [blame] | 68 | // Rotation values. |
| 69 | enum RotationValue { |
| 70 | kRotateNone, // Omitted |
| 71 | kRotate8, // ror #8 |
| 72 | kRotate16, // ror #16 |
| 73 | kRotate24 // ror #24 |
| 74 | }; |
| 75 | |
Karl Schimpf | 18cce42 | 2016-02-04 13:54:53 -0800 | [diff] [blame] | 76 | // Encoding of the number of D registers in a list of D registers. |
| 77 | enum DRegListSize { |
| 78 | DRegListSize1 = 7, // 0b0111 |
| 79 | DRegListSize2 = 10, // 0b1010 |
| 80 | DRegListSIze3 = 6, // 0b0110 |
| 81 | DRegListSize4 = 2 // 0b0010 |
| 82 | }; |
| 83 | |
Karl Schimpf | 2c68d90 | 2015-11-11 15:37:50 -0800 | [diff] [blame] | 84 | class TargetInfo { |
| 85 | TargetInfo(const TargetInfo &) = delete; |
| 86 | TargetInfo &operator=(const TargetInfo &) = delete; |
| 87 | |
| 88 | public: |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 89 | TargetInfo(bool HasFramePointer, RegNumT FrameOrStackReg) |
David Sehr | 26217e3 | 2015-11-26 13:03:50 -0800 | [diff] [blame] | 90 | : HasFramePointer(HasFramePointer), FrameOrStackReg(FrameOrStackReg) {} |
Karl Schimpf | 2c68d90 | 2015-11-11 15:37:50 -0800 | [diff] [blame] | 91 | explicit TargetInfo(const TargetLowering *Target) |
| 92 | : HasFramePointer(Target->hasFramePointer()), |
David Sehr | 26217e3 | 2015-11-26 13:03:50 -0800 | [diff] [blame] | 93 | FrameOrStackReg(Target->getFrameOrStackReg()) {} |
Karl Schimpf | 2c68d90 | 2015-11-11 15:37:50 -0800 | [diff] [blame] | 94 | const bool HasFramePointer; |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 95 | const RegNumT FrameOrStackReg; |
Karl Schimpf | 2c68d90 | 2015-11-11 15:37:50 -0800 | [diff] [blame] | 96 | }; |
| 97 | |
John Porto | dc61925 | 2016-02-10 15:57:16 -0800 | [diff] [blame] | 98 | explicit AssemblerARM32(bool IsNonsfi, bool use_far_branches = false) |
| 99 | : Assembler(Asm_ARM32), IsNonsfi(IsNonsfi) { |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 100 | // TODO(kschimpf): Add mode if needed when branches are handled. |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 101 | (void)use_far_branches; |
| 102 | } |
Karl Schimpf | 50a3331 | 2015-10-23 09:19:48 -0700 | [diff] [blame] | 103 | ~AssemblerARM32() override { |
| 104 | if (BuildDefs::asserts()) { |
| 105 | for (const Label *Label : CfgNodeLabels) { |
| 106 | Label->finalCheck(); |
| 107 | } |
| 108 | for (const Label *Label : LocalLabels) { |
| 109 | Label->finalCheck(); |
| 110 | } |
| 111 | } |
| 112 | } |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 113 | |
Karl Schimpf | 7cb2db3 | 2015-10-29 14:04:12 -0700 | [diff] [blame] | 114 | MoveRelocatableFixup *createMoveFixup(bool IsMovW, const Constant *Value); |
| 115 | |
Karl Schimpf | 515e8c2 | 2015-11-30 11:19:16 -0800 | [diff] [blame] | 116 | BlRelocatableFixup *createBlFixup(const ConstantRelocatable *BlTarget); |
Karl Schimpf | 174531e | 2015-11-18 08:19:26 -0800 | [diff] [blame] | 117 | |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 118 | void alignFunction() override { |
| 119 | const SizeT Align = 1 << getBundleAlignLog2Bytes(); |
| 120 | SizeT BytesNeeded = Utils::OffsetToAlignment(Buffer.getPosition(), Align); |
Karl Schimpf | 137e62b | 2015-10-27 07:28:09 -0700 | [diff] [blame] | 121 | constexpr SizeT InstSize = sizeof(IValueT); |
Karl Schimpf | 856734c | 2015-11-05 08:18:26 -0800 | [diff] [blame] | 122 | assert(BytesNeeded % InstARM32::InstSize == 0); |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 123 | while (BytesNeeded > 0) { |
Karl Schimpf | 7de2435 | 2015-12-17 08:55:10 -0800 | [diff] [blame] | 124 | trap(); |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 125 | BytesNeeded -= InstSize; |
| 126 | } |
| 127 | } |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 128 | |
| 129 | SizeT getBundleAlignLog2Bytes() const override { return 4; } |
| 130 | |
Andrew Scull | 86df4e9 | 2015-07-30 13:54:44 -0700 | [diff] [blame] | 131 | const char *getAlignDirective() const override { return ".p2alignl"; } |
Jan Voung | b2d5084 | 2015-05-12 09:53:50 -0700 | [diff] [blame] | 132 | |
Karl Schimpf | 7de2435 | 2015-12-17 08:55:10 -0800 | [diff] [blame] | 133 | llvm::ArrayRef<uint8_t> getNonExecBundlePadding() const override; |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 134 | |
Karl Schimpf | 67574d8 | 2015-12-08 15:37:00 -0800 | [diff] [blame] | 135 | void padWithNop(intptr_t Padding) override; |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 136 | |
Jan Voung | c2ec581 | 2015-08-05 09:35:18 -0700 | [diff] [blame] | 137 | Ice::Label *getCfgNodeLabel(SizeT NodeNumber) override { |
Karl Schimpf | 85342a7 | 2015-10-13 09:49:31 -0700 | [diff] [blame] | 138 | assert(NodeNumber < CfgNodeLabels.size()); |
| 139 | return CfgNodeLabels[NodeNumber]; |
Andrew Scull | 86df4e9 | 2015-07-30 13:54:44 -0700 | [diff] [blame] | 140 | } |
| 141 | |
Karl Schimpf | 137e62b | 2015-10-27 07:28:09 -0700 | [diff] [blame] | 142 | Label *getOrCreateCfgNodeLabel(SizeT NodeNumber) { |
| 143 | return getOrCreateLabel(NodeNumber, CfgNodeLabels); |
| 144 | } |
| 145 | |
| 146 | Label *getOrCreateLocalLabel(SizeT Number) { |
| 147 | return getOrCreateLabel(Number, LocalLabels); |
| 148 | } |
Karl Schimpf | 50a3331 | 2015-10-23 09:19:48 -0700 | [diff] [blame] | 149 | |
Karl Schimpf | d469994 | 2016-04-02 09:55:31 -0700 | [diff] [blame] | 150 | void bindLocalLabel(const InstARM32Label *InstL, SizeT Number) { |
| 151 | if (BuildDefs::dump() && !getFlags().getDisableHybridAssembly()) { |
Karl Schimpf | cb504ca | 2015-11-04 08:02:07 -0800 | [diff] [blame] | 152 | constexpr SizeT InstSize = 0; |
Jim Stichnoth | 467ffe5 | 2016-03-29 15:01:06 -0700 | [diff] [blame] | 153 | emitTextInst(InstL->getLabelName() + ":", InstSize); |
Karl Schimpf | cb504ca | 2015-11-04 08:02:07 -0800 | [diff] [blame] | 154 | } |
Karl Schimpf | 50a3331 | 2015-10-23 09:19:48 -0700 | [diff] [blame] | 155 | Label *L = getOrCreateLocalLabel(Number); |
| 156 | if (!getPreliminary()) |
| 157 | this->bind(L); |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | bool fixupIsPCRel(FixupKind Kind) const override { |
Jim Stichnoth | 3e32400 | 2016-03-08 16:18:40 -0800 | [diff] [blame] | 161 | if (Kind == llvm::ELF::R_ARM_MOVW_PREL_NC) |
| 162 | return true; |
| 163 | if (Kind == llvm::ELF::R_ARM_MOVT_PREL) |
| 164 | return true; |
Karl Schimpf | 2fee2a2 | 2015-10-22 08:19:26 -0700 | [diff] [blame] | 165 | return false; |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 166 | } |
Karl Schimpf | 372bdd6 | 2015-10-13 14:39:14 -0700 | [diff] [blame] | 167 | |
Karl Schimpf | 856734c | 2015-11-05 08:18:26 -0800 | [diff] [blame] | 168 | /// Accessors to keep track of the number of bytes generated inside |
| 169 | /// InstARM32::emit() methods, when run inside of |
| 170 | /// InstARM32::emitUsingTextFixup(). |
| 171 | void resetEmitTextSize() { EmitTextSize = 0; } |
| 172 | void incEmitTextSize(size_t Amount) { EmitTextSize += Amount; } |
| 173 | void decEmitTextSize(size_t Amount) { EmitTextSize -= Amount; } |
| 174 | size_t getEmitTextSize() const { return EmitTextSize; } |
| 175 | |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 176 | void bind(Label *label); |
| 177 | |
Karl Schimpf | 372bdd6 | 2015-10-13 14:39:14 -0700 | [diff] [blame] | 178 | // List of instructions implemented by integrated assembler. |
| 179 | |
Karl Schimpf | db09888 | 2015-10-27 07:36:59 -0700 | [diff] [blame] | 180 | void adc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 181 | bool SetFlags, CondARM32::Cond Cond); |
| 182 | |
Karl Schimpf | 372bdd6 | 2015-10-13 14:39:14 -0700 | [diff] [blame] | 183 | void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 184 | bool SetFlags, CondARM32::Cond Cond); |
| 185 | |
Karl Schimpf | c33f7bb | 2015-10-29 15:50:32 -0700 | [diff] [blame] | 186 | void and_(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 187 | bool SetFlags, CondARM32::Cond Cond); |
| 188 | |
Karl Schimpf | 3ac9a49 | 2015-12-08 13:41:38 -0800 | [diff] [blame] | 189 | void asr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 190 | bool SetFlags, CondARM32::Cond Cond); |
| 191 | |
Karl Schimpf | 137e62b | 2015-10-27 07:28:09 -0700 | [diff] [blame] | 192 | void b(Label *L, CondARM32::Cond Cond); |
| 193 | |
Karl Schimpf | 85342a7 | 2015-10-13 09:49:31 -0700 | [diff] [blame] | 194 | void bkpt(uint16_t Imm16); |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 195 | |
Karl Schimpf | 4f8805b | 2015-11-02 15:01:56 -0800 | [diff] [blame] | 196 | void bic(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 197 | bool SetFlags, CondARM32::Cond Cond); |
| 198 | |
Karl Schimpf | 174531e | 2015-11-18 08:19:26 -0800 | [diff] [blame] | 199 | void bl(const ConstantRelocatable *Target); |
| 200 | |
| 201 | void blx(const Operand *Target); |
| 202 | |
| 203 | void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); |
| 204 | |
Karl Schimpf | 65f80d7 | 2015-12-17 08:02:17 -0800 | [diff] [blame] | 205 | void clz(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); |
| 206 | |
Karl Schimpf | 4c435d3 | 2015-12-08 14:45:28 -0800 | [diff] [blame] | 207 | void cmn(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond); |
| 208 | |
Karl Schimpf | 174531e | 2015-11-18 08:19:26 -0800 | [diff] [blame] | 209 | void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond); |
| 210 | |
Karl Schimpf | d3f94f7 | 2015-12-09 07:35:00 -0800 | [diff] [blame] | 211 | void dmb(IValueT Option); // Option is a 4-bit value. |
| 212 | |
Karl Schimpf | 62d367b | 2015-10-30 08:06:44 -0700 | [diff] [blame] | 213 | void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 214 | bool SetFlags, CondARM32::Cond Cond); |
| 215 | |
Karl Schimpf | 2c68d90 | 2015-11-11 15:37:50 -0800 | [diff] [blame] | 216 | void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, |
| 217 | const TargetInfo &TInfo); |
| 218 | |
| 219 | void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, |
| 220 | const TargetLowering *Lowering) { |
| 221 | const TargetInfo TInfo(Lowering); |
| 222 | ldr(OpRt, OpAddress, Cond, TInfo); |
| 223 | } |
Karl Schimpf | 745ad1d | 2015-10-16 10:31:31 -0700 | [diff] [blame] | 224 | |
Karl Schimpf | 4175d45 | 2015-12-17 08:06:01 -0800 | [diff] [blame] | 225 | void ldrex(const Operand *OpRt, const Operand *OpAddress, |
| 226 | CondARM32::Cond Cond, const TargetInfo &TInfo); |
| 227 | |
| 228 | void ldrex(const Operand *OpRt, const Operand *OpAddress, |
| 229 | CondARM32::Cond Cond, const TargetLowering *Lowering) { |
| 230 | const TargetInfo TInfo(Lowering); |
| 231 | ldrex(OpRt, OpAddress, Cond, TInfo); |
| 232 | } |
| 233 | |
Karl Schimpf | f4d0a7a | 2015-11-19 08:10:44 -0800 | [diff] [blame] | 234 | void lsl(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 235 | bool SetFlags, CondARM32::Cond Cond); |
| 236 | |
Karl Schimpf | 4ddce70 | 2015-12-07 10:43:34 -0800 | [diff] [blame] | 237 | void lsr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 238 | bool SetFlags, CondARM32::Cond Cond); |
| 239 | |
Karl Schimpf | 372bdd6 | 2015-10-13 14:39:14 -0700 | [diff] [blame] | 240 | void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); |
Karl Schimpf | 85342a7 | 2015-10-13 09:49:31 -0700 | [diff] [blame] | 241 | |
Karl Schimpf | 7cb2db3 | 2015-10-29 14:04:12 -0700 | [diff] [blame] | 242 | void movw(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); |
| 243 | |
| 244 | void movt(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); |
| 245 | |
Karl Schimpf | 080b65b | 2015-11-05 08:27:51 -0800 | [diff] [blame] | 246 | void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm, |
| 247 | const Operand *OpRa, CondARM32::Cond Cond); |
| 248 | |
Karl Schimpf | a990f0c | 2015-12-18 07:36:02 -0800 | [diff] [blame] | 249 | void mls(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm, |
| 250 | const Operand *OpRa, CondARM32::Cond Cond); |
| 251 | |
Karl Schimpf | b81b901 | 2015-11-04 14:54:52 -0800 | [diff] [blame] | 252 | void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 253 | bool SetFlags, CondARM32::Cond Cond); |
| 254 | |
Karl Schimpf | e559be7 | 2015-11-20 14:26:12 -0800 | [diff] [blame] | 255 | void mvn(const Operand *OpRd, const Operand *OpScc, CondARM32::Cond Cond); |
| 256 | |
Karl Schimpf | 67574d8 | 2015-12-08 15:37:00 -0800 | [diff] [blame] | 257 | void nop(); |
| 258 | |
Karl Schimpf | 9c08bee | 2015-10-30 07:42:00 -0700 | [diff] [blame] | 259 | void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 260 | bool SetFlags, CondARM32::Cond Cond); |
| 261 | |
Karl Schimpf | c411dbf | 2016-01-11 09:59:19 -0800 | [diff] [blame] | 262 | void pop(const Variable *OpRt, CondARM32::Cond Cond); |
Karl Schimpf | f66a85b | 2015-11-10 14:12:35 -0800 | [diff] [blame] | 263 | |
| 264 | // Note: Registers is a bitset, where bit n corresponds to register Rn. |
| 265 | void popList(const IValueT Registers, CondARM32::Cond Cond); |
| 266 | |
Karl Schimpf | 6cab561 | 2015-11-06 09:14:10 -0800 | [diff] [blame] | 267 | void push(const Operand *OpRt, CondARM32::Cond Cond); |
| 268 | |
| 269 | // Note: Registers is a bitset, where bit n corresponds to register Rn. |
| 270 | void pushList(const IValueT Registers, CondARM32::Cond Cond); |
| 271 | |
Karl Schimpf | 17fe194 | 2015-12-18 07:41:06 -0800 | [diff] [blame] | 272 | void rbit(const Operand *OpRd, const Operand *OpRm, CondARM32::Cond Cond); |
| 273 | |
| 274 | void rev(const Operand *OpRd, const Operand *OpRm, CondARM32::Cond Cond); |
Karl Schimpf | 7e87b61 | 2015-12-11 09:32:28 -0800 | [diff] [blame] | 275 | |
Karl Schimpf | dca8674 | 2015-12-04 15:11:43 -0800 | [diff] [blame] | 276 | void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 277 | bool SetFlags, CondARM32::Cond Cond); |
| 278 | |
Karl Schimpf | 337ac9e | 2015-12-11 09:12:07 -0800 | [diff] [blame] | 279 | void rsc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 280 | bool SetFlags, CondARM32::Cond Cond); |
| 281 | |
Karl Schimpf | 3b8a15e | 2015-10-29 09:11:40 -0700 | [diff] [blame] | 282 | void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 283 | bool SetFlags, CondARM32::Cond Cond); |
| 284 | |
Karl Schimpf | 697dc79 | 2015-10-30 13:21:59 -0700 | [diff] [blame] | 285 | void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 286 | CondARM32::Cond Cond); |
| 287 | |
Karl Schimpf | 2c68d90 | 2015-11-11 15:37:50 -0800 | [diff] [blame] | 288 | void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, |
| 289 | const TargetInfo &TInfo); |
| 290 | |
| 291 | void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, |
| 292 | const TargetLowering *Lowering) { |
| 293 | const TargetInfo TInfo(Lowering); |
| 294 | str(OpRt, OpAddress, Cond, TInfo); |
| 295 | } |
Karl Schimpf | 745ad1d | 2015-10-16 10:31:31 -0700 | [diff] [blame] | 296 | |
Karl Schimpf | 4175d45 | 2015-12-17 08:06:01 -0800 | [diff] [blame] | 297 | void strex(const Operand *OpRd, const Operand *OpRt, const Operand *OpAddress, |
| 298 | CondARM32::Cond Cond, const TargetInfo &TInfo); |
| 299 | |
| 300 | void strex(const Operand *OpRd, const Operand *OpRt, const Operand *OpAddress, |
| 301 | CondARM32::Cond Cond, const TargetLowering *Lowering) { |
| 302 | const TargetInfo TInfo(Lowering); |
| 303 | strex(OpRd, OpRt, OpAddress, Cond, TInfo); |
| 304 | } |
| 305 | |
Karl Schimpf | e345505 | 2015-10-14 14:30:21 -0700 | [diff] [blame] | 306 | void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 307 | bool SetFlags, CondARM32::Cond Cond); |
| 308 | |
Karl Schimpf | 1e67f91 | 2015-12-08 11:17:23 -0800 | [diff] [blame] | 309 | // Implements sxtb/sxth depending on type of OpSrc0. |
| 310 | void sxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond); |
| 311 | |
Karl Schimpf | 7de2435 | 2015-12-17 08:55:10 -0800 | [diff] [blame] | 312 | void trap(); |
| 313 | |
Karl Schimpf | b81b901 | 2015-11-04 14:54:52 -0800 | [diff] [blame] | 314 | void tst(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond); |
| 315 | |
Karl Schimpf | 1c28550 | 2015-10-30 15:00:24 -0700 | [diff] [blame] | 316 | void udiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 317 | CondARM32::Cond Cond); |
| 318 | |
Karl Schimpf | 430e844 | 2015-11-09 12:16:20 -0800 | [diff] [blame] | 319 | void umull(const Operand *OpRdLo, const Operand *OpRdHi, const Operand *OpRn, |
| 320 | const Operand *OpRm, CondARM32::Cond Cond); |
| 321 | |
Karl Schimpf | bb0bacf | 2015-11-11 15:42:55 -0800 | [diff] [blame] | 322 | // Implements uxtb/uxth depending on type of OpSrc0. |
| 323 | void uxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond); |
| 324 | |
Karl Schimpf | bd4356d | 2016-02-02 13:35:45 -0800 | [diff] [blame] | 325 | void vabss(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond); |
| 326 | |
Karl Schimpf | 425e06b | 2016-02-17 09:51:23 -0800 | [diff] [blame] | 327 | void vabsd(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond Cond); |
| 328 | |
| 329 | void vabsq(const Operand *OpQd, const Operand *OpQm); |
Karl Schimpf | bd4356d | 2016-02-02 13:35:45 -0800 | [diff] [blame] | 330 | |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 331 | void vaddd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, |
| 332 | CondARM32::Cond Cond); |
| 333 | |
| 334 | void vadds(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, |
| 335 | CondARM32::Cond Cond); |
| 336 | |
Karl Schimpf | 2c0764e | 2016-02-01 13:44:37 -0800 | [diff] [blame] | 337 | // Integer vector add. |
| 338 | void vaddqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 339 | const Operand *OpQn); |
| 340 | |
| 341 | // Float vector add. |
| 342 | void vaddqf(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn); |
| 343 | |
Karl Schimpf | fd7975f | 2016-02-02 11:25:10 -0800 | [diff] [blame] | 344 | void vandq(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn); |
| 345 | |
John Porto | 397f602 | 2016-04-15 06:26:58 -0700 | [diff] [blame] | 346 | void vbslq(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn); |
| 347 | |
John Porto | a4d100a | 2016-04-18 15:32:27 -0700 | [diff] [blame] | 348 | void vceqqi(const Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 349 | const Operand *OpQn); |
| 350 | |
| 351 | void vceqqs(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn); |
| 352 | |
| 353 | void vcgeqi(const Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 354 | const Operand *OpQn); |
| 355 | |
| 356 | void vcugeqi(const Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 357 | const Operand *OpQn); |
| 358 | |
| 359 | void vcgeqs(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn); |
| 360 | |
| 361 | void vcgtqi(const Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 362 | const Operand *OpQn); |
| 363 | |
| 364 | void vcugtqi(const Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 365 | const Operand *OpQn); |
| 366 | |
| 367 | void vcgtqs(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn); |
| 368 | |
Karl Schimpf | cd5e07e | 2016-01-11 10:12:20 -0800 | [diff] [blame] | 369 | void vcmpd(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond cond); |
| 370 | |
| 371 | // Second argument of compare is zero (+0.0). |
| 372 | void vcmpdz(const Operand *OpDd, CondARM32::Cond cond); |
| 373 | |
| 374 | void vcmps(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond cond); |
| 375 | |
| 376 | // Second argument of compare is zero (+0.0). |
| 377 | void vcmpsz(const Operand *OpSd, CondARM32::Cond cond); |
| 378 | |
Karl Schimpf | 6c7181c | 2016-01-08 07:31:08 -0800 | [diff] [blame] | 379 | void vcvtds(const Operand *OpDd, const Operand *OpSm, CondARM32::Cond Cond); |
| 380 | |
Karl Schimpf | 94cc3e6 | 2016-01-22 08:33:50 -0800 | [diff] [blame] | 381 | // vcvt<c>.S32.F32 |
| 382 | void vcvtis(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond); |
| 383 | |
Karl Schimpf | ab389f2 | 2016-01-22 15:08:44 -0800 | [diff] [blame] | 384 | // vcvt<c>.S32.F64 |
| 385 | void vcvtid(const Operand *OpSd, const Operand *OpDm, CondARM32::Cond Cond); |
| 386 | |
| 387 | // vcvt<c>.F64.S32 |
| 388 | void vcvtdi(const Operand *OpDd, const Operand *OpSm, CondARM32::Cond Cond); |
| 389 | |
| 390 | // vcvt<c>.F64.U32 |
| 391 | void vcvtdu(const Operand *OpDd, const Operand *OpSm, CondARM32::Cond Cond); |
| 392 | |
Karl Schimpf | 94cc3e6 | 2016-01-22 08:33:50 -0800 | [diff] [blame] | 393 | void vcvtsd(const Operand *OpSd, const Operand *OpDm, CondARM32::Cond Cond); |
| 394 | |
Karl Schimpf | ab389f2 | 2016-01-22 15:08:44 -0800 | [diff] [blame] | 395 | // vcvt<c>.F32.S32 |
| 396 | void vcvtsi(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond); |
| 397 | |
| 398 | // vcvt<c>.F32.U32 |
| 399 | void vcvtsu(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond); |
| 400 | |
| 401 | // vcvt<c>.U32.F64 |
| 402 | void vcvtud(const Operand *OpSd, const Operand *OpDm, CondARM32::Cond Cond); |
| 403 | |
| 404 | // vcvt<c>.u32.f32 |
| 405 | void vcvtus(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond); |
| 406 | |
John Porto | e88c7de | 2016-04-14 11:51:38 -0700 | [diff] [blame] | 407 | void vcvtqsi(const Operand *OpQd, const Operand *OpQm); |
| 408 | |
| 409 | void vcvtqsu(const Operand *OpQd, const Operand *OpQm); |
| 410 | |
| 411 | void vcvtqis(const Operand *OpQd, const Operand *OpQm); |
| 412 | |
| 413 | void vcvtqus(const Operand *OpQd, const Operand *OpQm); |
| 414 | |
Karl Schimpf | 3dbe780 | 2016-01-07 13:37:39 -0800 | [diff] [blame] | 415 | void vdivd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, |
| 416 | CondARM32::Cond Cond); |
| 417 | |
| 418 | void vdivs(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, |
| 419 | CondARM32::Cond Cond); |
| 420 | |
Karl Schimpf | 53378c1 | 2016-01-21 10:16:43 -0800 | [diff] [blame] | 421 | void veord(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm); |
| 422 | |
Karl Schimpf | 625dfb3 | 2016-02-03 13:21:50 -0800 | [diff] [blame] | 423 | void veorq(const Operand *OpQd, const Operand *OpQn, const Operand *OpQm); |
| 424 | |
Karl Schimpf | e1d7138 | 2016-01-21 09:47:14 -0800 | [diff] [blame] | 425 | void vldrd(const Operand *OpDd, const Operand *OpAddress, |
| 426 | CondARM32::Cond Cond, const TargetInfo &TInfo); |
| 427 | |
| 428 | void vldrd(const Operand *OpDd, const Operand *OpAddress, |
| 429 | CondARM32::Cond Cond, const TargetLowering *Lowering) { |
| 430 | const TargetInfo TInfo(Lowering); |
| 431 | vldrd(OpDd, OpAddress, Cond, TInfo); |
| 432 | } |
| 433 | |
| 434 | void vldrs(const Operand *OpSd, const Operand *OpAddress, |
| 435 | CondARM32::Cond Cond, const TargetInfo &TInfo); |
| 436 | |
| 437 | void vldrs(const Operand *OpSd, const Operand *OpAddress, |
| 438 | CondARM32::Cond Cond, const TargetLowering *Lowering) { |
| 439 | const TargetInfo TInfo(Lowering); |
| 440 | vldrs(OpSd, OpAddress, Cond, TInfo); |
| 441 | } |
| 442 | |
Nicolas Capens | 675e15b | 2017-09-27 15:06:35 -0400 | [diff] [blame] | 443 | void vldrq(const Operand *OpQd, const Operand *OpAddress, |
| 444 | CondARM32::Cond Cond, const TargetInfo &TInfo); |
| 445 | |
| 446 | void vldrq(const Operand *OpQd, const Operand *OpAddress, |
| 447 | CondARM32::Cond Cond, const TargetLowering *Lowering) { |
| 448 | const TargetInfo TInfo(Lowering); |
| 449 | vldrq(OpQd, OpAddress, Cond, TInfo); |
| 450 | } |
| 451 | |
Karl Schimpf | 18cce42 | 2016-02-04 13:54:53 -0800 | [diff] [blame] | 452 | // ElmtSize = #bits in vector element. |
| 453 | void vld1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn, |
| 454 | const TargetInfo &TInfo); |
| 455 | |
Nicolas Capens | 675e15b | 2017-09-27 15:06:35 -0400 | [diff] [blame] | 456 | void vld1(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn, |
| 457 | const TargetInfo &TInfo); |
| 458 | |
Karl Schimpf | 18cce42 | 2016-02-04 13:54:53 -0800 | [diff] [blame] | 459 | void vld1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn, |
| 460 | const TargetLowering *Lowering) { |
| 461 | const TargetInfo TInfo(Lowering); |
| 462 | vld1qr(ElmtSize, OpQd, OpRn, TInfo); |
| 463 | } |
| 464 | |
Nicolas Capens | 675e15b | 2017-09-27 15:06:35 -0400 | [diff] [blame] | 465 | void vld1(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn, |
| 466 | const TargetLowering *Lowering) { |
| 467 | const TargetInfo TInfo(Lowering); |
| 468 | vld1(ElmtSize, OpQd, OpRn, TInfo); |
| 469 | } |
| 470 | |
Karl Schimpf | b627f09 | 2016-04-11 14:32:15 -0700 | [diff] [blame] | 471 | // Qn[i] = Imm for all i in vector. Returns true iff Imm can be defined as an |
| 472 | // Imm8 using AdvSIMDExpandImm(). |
| 473 | bool vmovqc(const Operand *OpQd, const ConstantInteger32 *Imm); |
| 474 | |
Karl Schimpf | 6de32b2 | 2016-02-10 13:30:48 -0800 | [diff] [blame] | 475 | // Dn = FpImm |
Karl Schimpf | c64448f | 2016-01-26 11:12:29 -0800 | [diff] [blame] | 476 | void vmovd(const Operand *OpDn, const OperandARM32FlexFpImm *OpFpImm, |
| 477 | CondARM32::Cond Cond); |
| 478 | |
Karl Schimpf | 6de32b2 | 2016-02-10 13:30:48 -0800 | [diff] [blame] | 479 | // Dd = Dm |
Karl Schimpf | ac186fd | 2016-01-27 15:39:32 -0800 | [diff] [blame] | 480 | void vmovdd(const Operand *OpDd, const Variable *OpDm, CondARM32::Cond Cond); |
Karl Schimpf | 9aedc2e | 2016-01-27 13:36:09 -0800 | [diff] [blame] | 481 | |
Karl Schimpf | 6de32b2 | 2016-02-10 13:30:48 -0800 | [diff] [blame] | 482 | // Dm = Rt:Rt2 |
Karl Schimpf | a880ac8 | 2016-01-29 07:28:05 -0800 | [diff] [blame] | 483 | void vmovdrr(const Operand *OpDm, const Operand *OpRt, const Operand *OpRt2, |
| 484 | CondARM32::Cond Cond); |
| 485 | |
Karl Schimpf | 6de32b2 | 2016-02-10 13:30:48 -0800 | [diff] [blame] | 486 | // Qd[Index] = Rt |
| 487 | void vmovqir(const Operand *OpQd, uint32_t Index, const Operand *OpRt, |
| 488 | CondARM32::Cond Cond); |
| 489 | |
| 490 | // Qd[Index] = Sm |
| 491 | void vmovqis(const Operand *OpQd, uint32_t Indx, const Operand *OpSm, |
| 492 | CondARM32::Cond Cond); |
| 493 | |
| 494 | // Rt = Qm[Index] |
| 495 | void vmovrqi(const Operand *OpRt, const Operand *OpQd, uint32_t Index, |
| 496 | CondARM32::Cond Cond); |
| 497 | |
| 498 | // Rt:Rt2 = Dm |
Karl Schimpf | a880ac8 | 2016-01-29 07:28:05 -0800 | [diff] [blame] | 499 | void vmovrrd(const Operand *OpRt, const Operand *OpRt2, const Operand *OpDm, |
| 500 | CondARM32::Cond Cond); |
| 501 | |
Karl Schimpf | 6de32b2 | 2016-02-10 13:30:48 -0800 | [diff] [blame] | 502 | // Rt = Sn |
Karl Schimpf | e1b6574 | 2016-01-27 15:36:18 -0800 | [diff] [blame] | 503 | void vmovrs(const Operand *OpRt, const Operand *OpSn, CondARM32::Cond Cond); |
| 504 | |
Karl Schimpf | 6de32b2 | 2016-02-10 13:30:48 -0800 | [diff] [blame] | 505 | // Sn = FpImm |
Karl Schimpf | c64448f | 2016-01-26 11:12:29 -0800 | [diff] [blame] | 506 | void vmovs(const Operand *OpSn, const OperandARM32FlexFpImm *OpFpImm, |
| 507 | CondARM32::Cond Cond); |
| 508 | |
Karl Schimpf | 6de32b2 | 2016-02-10 13:30:48 -0800 | [diff] [blame] | 509 | // Sd = Sm |
| 510 | void vmovss(const Operand *OpSd, const Variable *OpSm, CondARM32::Cond Cond); |
Karl Schimpf | 9aedc2e | 2016-01-27 13:36:09 -0800 | [diff] [blame] | 511 | |
Karl Schimpf | 6de32b2 | 2016-02-10 13:30:48 -0800 | [diff] [blame] | 512 | // Sd = Qm[Index] |
| 513 | void vmovsqi(const Operand *OpSd, const Operand *OpQm, uint32_t Index, |
| 514 | CondARM32::Cond Cond); |
| 515 | |
| 516 | // Sn = Rt |
Karl Schimpf | 4ff90be | 2016-01-22 15:15:50 -0800 | [diff] [blame] | 517 | void vmovsr(const Operand *OpSn, const Operand *OpRt, CondARM32::Cond Cond); |
| 518 | |
Karl Schimpf | bd8e28e | 2016-01-26 12:25:43 -0800 | [diff] [blame] | 519 | void vmlad(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, |
| 520 | CondARM32::Cond Cond); |
| 521 | |
| 522 | void vmlas(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, |
| 523 | CondARM32::Cond Cond); |
| 524 | |
Karl Schimpf | 694cdbd | 2016-01-29 07:23:20 -0800 | [diff] [blame] | 525 | void vmlsd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, |
| 526 | CondARM32::Cond Cond); |
| 527 | |
| 528 | void vmlss(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, |
| 529 | CondARM32::Cond Cond); |
| 530 | |
Karl Schimpf | ee71827 | 2016-01-25 09:17:26 -0800 | [diff] [blame] | 531 | // Uses APSR_nzcv as register |
| 532 | void vmrsAPSR_nzcv(CondARM32::Cond Cond); |
| 533 | |
Karl Schimpf | 8a105fd | 2016-01-07 13:46:20 -0800 | [diff] [blame] | 534 | void vmuld(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, |
| 535 | CondARM32::Cond Cond); |
| 536 | |
Karl Schimpf | 341158a | 2016-02-03 13:27:01 -0800 | [diff] [blame] | 537 | // Integer vector multiply. |
| 538 | void vmulqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQn, |
| 539 | const Operand *OpQm); |
| 540 | |
Nicolas Capens | 675e15b | 2017-09-27 15:06:35 -0400 | [diff] [blame] | 541 | // Integer vector multiply high. |
| 542 | void vmulh(Type ElmtTy, const Operand *OpQd, const Operand *OpQn, |
| 543 | const Operand *OpQm, bool Unsigned); |
| 544 | |
| 545 | // Integer vector multiply add pairwise. |
| 546 | void vmlap(Type ElmtTy, const Operand *OpQd, const Operand *OpQn, |
| 547 | const Operand *OpQm); |
| 548 | |
Nicolas Capens | f6951fa | 2017-10-02 10:44:03 -0400 | [diff] [blame] | 549 | // Vector element replication. |
| 550 | void vdup(Type ElmtTy, const Operand *OpQd, const Operand *OpQn, IValueT Idx); |
| 551 | |
| 552 | // Vector interleave lower halves. |
| 553 | void vzip(Type ElmtTy, const Operand *OpQd, const Operand *OpQn, |
| 554 | const Operand *OpQm); |
| 555 | |
Karl Schimpf | 341158a | 2016-02-03 13:27:01 -0800 | [diff] [blame] | 556 | // Float vector multiply. |
| 557 | void vmulqf(const Operand *OpQd, const Operand *OpQn, const Operand *OpQm); |
| 558 | |
Karl Schimpf | 8a105fd | 2016-01-07 13:46:20 -0800 | [diff] [blame] | 559 | void vmuls(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, |
| 560 | CondARM32::Cond Cond); |
| 561 | |
John Porto | a4d100a | 2016-04-18 15:32:27 -0700 | [diff] [blame] | 562 | void vmvnq(const Operand *OpQd, const Operand *OpQm); |
| 563 | |
Nicolas Capens | f6951fa | 2017-10-02 10:44:03 -0400 | [diff] [blame] | 564 | void vmovlq(const Operand *OpQd, const Operand *OpQn, const Operand *OpQm); |
| 565 | void vmovhq(const Operand *OpQd, const Operand *OpQn, const Operand *OpQm); |
| 566 | void vmovhlq(const Operand *OpQd, const Operand *OpQn, const Operand *OpQm); |
| 567 | void vmovlhq(const Operand *OpQd, const Operand *OpQn, const Operand *OpQm); |
| 568 | |
John Porto | a4d100a | 2016-04-18 15:32:27 -0700 | [diff] [blame] | 569 | void vnegqs(const Operand *OpQd, const Operand *OpQm); |
| 570 | |
John Porto | 15e77d4 | 2016-04-13 12:57:14 -0700 | [diff] [blame] | 571 | void vnegqs(Type ElmtTy, const Operand *OpQd, const Operand *OpQm); |
| 572 | |
Karl Schimpf | e295575 | 2016-02-02 12:57:30 -0800 | [diff] [blame] | 573 | void vorrq(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn); |
| 574 | |
Karl Schimpf | a3c3214 | 2015-12-18 08:26:16 -0800 | [diff] [blame] | 575 | void vpop(const Variable *OpBaseReg, SizeT NumConsecRegs, |
| 576 | CondARM32::Cond Cond); |
| 577 | |
| 578 | void vpush(const Variable *OpBaseReg, SizeT NumConsecRegs, |
| 579 | CondARM32::Cond Cond); |
| 580 | |
John Porto | 15e77d4 | 2016-04-13 12:57:14 -0700 | [diff] [blame] | 581 | void vshlqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 582 | const Operand *OpQn); |
| 583 | |
| 584 | void vshlqu(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 585 | const Operand *OpQn); |
| 586 | |
John Porto | e88c7de | 2016-04-14 11:51:38 -0700 | [diff] [blame] | 587 | void vshlqc(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 588 | const ConstantInteger32 *OpQn); |
| 589 | |
Nicolas Capens | 8d90a34 | 2017-09-27 14:33:11 -0400 | [diff] [blame] | 590 | void vshrqc(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 591 | const ConstantInteger32 *OpQn, InstARM32::FPSign Sign); |
John Porto | e88c7de | 2016-04-14 11:51:38 -0700 | [diff] [blame] | 592 | |
Karl Schimpf | 266c5a2 | 2016-01-29 09:54:58 -0800 | [diff] [blame] | 593 | void vsqrtd(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond Cond); |
| 594 | |
| 595 | void vsqrts(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond); |
| 596 | |
Karl Schimpf | 4a55a60 | 2016-01-21 10:02:15 -0800 | [diff] [blame] | 597 | void vstrd(const Operand *OpDd, const Operand *OpAddress, |
| 598 | CondARM32::Cond Cond, const TargetInfo &TInfo); |
| 599 | |
| 600 | void vstrd(const Operand *OpDd, const Operand *OpAddress, |
| 601 | CondARM32::Cond Cond, const TargetLowering *Lowering) { |
| 602 | const TargetInfo TInfo(Lowering); |
| 603 | vstrd(OpDd, OpAddress, Cond, TInfo); |
| 604 | } |
| 605 | |
| 606 | void vstrs(const Operand *OpSd, const Operand *OpAddress, |
| 607 | CondARM32::Cond Cond, const TargetInfo &TInfo); |
| 608 | |
| 609 | void vstrs(const Operand *OpSd, const Operand *OpAddress, |
| 610 | CondARM32::Cond Cond, const TargetLowering *Lowering) { |
| 611 | const TargetInfo TInfo(Lowering); |
| 612 | vstrs(OpSd, OpAddress, Cond, TInfo); |
| 613 | } |
| 614 | |
Nicolas Capens | 675e15b | 2017-09-27 15:06:35 -0400 | [diff] [blame] | 615 | void vstrq(const Operand *OpQd, const Operand *OpAddress, |
| 616 | CondARM32::Cond Cond, const TargetInfo &TInfo); |
| 617 | |
| 618 | void vstrq(const Operand *OpQd, const Operand *OpAddress, |
| 619 | CondARM32::Cond Cond, const TargetLowering *Lowering) { |
| 620 | const TargetInfo TInfo(Lowering); |
| 621 | vstrq(OpQd, OpAddress, Cond, TInfo); |
| 622 | } |
| 623 | |
Karl Schimpf | 18cce42 | 2016-02-04 13:54:53 -0800 | [diff] [blame] | 624 | // ElmtSize = #bits in vector element. |
| 625 | void vst1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpAddress, |
| 626 | const TargetInfo &TInfo); |
| 627 | |
| 628 | void vst1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn, |
| 629 | const TargetLowering *Lowering) { |
| 630 | const TargetInfo TInfo(Lowering); |
| 631 | vst1qr(ElmtSize, OpQd, OpRn, TInfo); |
| 632 | } |
| 633 | |
Nicolas Capens | 675e15b | 2017-09-27 15:06:35 -0400 | [diff] [blame] | 634 | void vst1(size_t ElmtSize, const Operand *OpQd, const Operand *OpAddress, |
| 635 | const TargetInfo &TInfo); |
| 636 | |
| 637 | void vst1(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn, |
| 638 | const TargetLowering *Lowering) { |
| 639 | const TargetInfo TInfo(Lowering); |
| 640 | vst1(ElmtSize, OpQd, OpRn, TInfo); |
| 641 | } |
| 642 | |
Karl Schimpf | b3e2574 | 2016-01-07 10:20:27 -0800 | [diff] [blame] | 643 | void vsubd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, |
| 644 | CondARM32::Cond Cond); |
| 645 | |
Karl Schimpf | 50cfcb0 | 2016-02-02 10:19:20 -0800 | [diff] [blame] | 646 | // Integer vector subtract. |
| 647 | void vsubqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 648 | const Operand *OpQn); |
| 649 | |
Casey Dahlin | b40560b | 2017-06-28 13:58:58 -0700 | [diff] [blame] | 650 | // Integer vector saturating subtract. |
| 651 | void vqsubqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 652 | const Operand *OpQn); |
| 653 | void vqsubqu(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 654 | const Operand *OpQn); |
| 655 | |
| 656 | // Integer vector saturating add. |
| 657 | void vqaddqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 658 | const Operand *OpQn); |
| 659 | void vqaddqu(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 660 | const Operand *OpQn); |
| 661 | |
Nicolas Capens | 675e15b | 2017-09-27 15:06:35 -0400 | [diff] [blame] | 662 | // Integer vector packing with optional saturation. |
| 663 | void vqmovn2(Type ElmtTy, const Operand *OpQd, const Operand *OpQm, |
| 664 | const Operand *OpQn, bool Unsigned, bool Saturating); |
| 665 | |
Karl Schimpf | 50cfcb0 | 2016-02-02 10:19:20 -0800 | [diff] [blame] | 666 | // Float vector subtract |
| 667 | void vsubqf(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn); |
| 668 | |
Karl Schimpf | b3e2574 | 2016-01-07 10:20:27 -0800 | [diff] [blame] | 669 | void vsubs(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, |
| 670 | CondARM32::Cond Cond); |
| 671 | |
John Porto | 2da710c | 2015-06-29 07:57:02 -0700 | [diff] [blame] | 672 | static bool classof(const Assembler *Asm) { |
| 673 | return Asm->getKind() == Asm_ARM32; |
| 674 | } |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 675 | |
Karl Schimpf | 856734c | 2015-11-05 08:18:26 -0800 | [diff] [blame] | 676 | void emitTextInst(const std::string &Text, SizeT InstSize); |
Karl Schimpf | 2fee2a2 | 2015-10-22 08:19:26 -0700 | [diff] [blame] | 677 | |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 678 | private: |
John Porto | 53611e2 | 2015-12-30 07:30:10 -0800 | [diff] [blame] | 679 | ENABLE_MAKE_UNIQUE; |
| 680 | |
John Porto | dc61925 | 2016-02-10 15:57:16 -0800 | [diff] [blame] | 681 | const bool IsNonsfi; |
| 682 | |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 683 | // A vector of pool-allocated x86 labels for CFG nodes. |
| 684 | using LabelVector = std::vector<Label *>; |
| 685 | LabelVector CfgNodeLabels; |
Karl Schimpf | 50a3331 | 2015-10-23 09:19:48 -0700 | [diff] [blame] | 686 | // A vector of pool-allocated x86 labels for Local labels. |
| 687 | LabelVector LocalLabels; |
Karl Schimpf | 856734c | 2015-11-05 08:18:26 -0800 | [diff] [blame] | 688 | // Number of bytes emitted by InstARM32::emit() methods, when run inside |
| 689 | // InstARM32::emitUsingTextFixup(). |
| 690 | size_t EmitTextSize = 0; |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 691 | |
Karl Schimpf | 6cab561 | 2015-11-06 09:14:10 -0800 | [diff] [blame] | 692 | // Load/store multiple addressing mode. |
| 693 | enum BlockAddressMode { |
| 694 | // bit encoding P U W |
| 695 | DA = (0 | 0 | 0) << 21, // decrement after |
| 696 | IA = (0 | 4 | 0) << 21, // increment after |
| 697 | DB = (8 | 0 | 0) << 21, // decrement before |
| 698 | IB = (8 | 4 | 0) << 21, // increment before |
| 699 | DA_W = (0 | 0 | 1) << 21, // decrement after with writeback to base |
| 700 | IA_W = (0 | 4 | 1) << 21, // increment after with writeback to base |
| 701 | DB_W = (8 | 0 | 1) << 21, // decrement before with writeback to base |
| 702 | IB_W = (8 | 4 | 1) << 21 // increment before with writeback to base |
| 703 | }; |
| 704 | |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 705 | Label *getOrCreateLabel(SizeT Number, LabelVector &Labels); |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 706 | |
Karl Schimpf | 137e62b | 2015-10-27 07:28:09 -0700 | [diff] [blame] | 707 | void bindCfgNodeLabel(const CfgNode *Node) override; |
| 708 | |
Karl Schimpf | 425e06b | 2016-02-17 09:51:23 -0800 | [diff] [blame] | 709 | // SIMD encoding for the vector ElmtTy. |
| 710 | static IValueT encodeElmtType(Type ElmtTy); |
| 711 | |
Karl Schimpf | 237afed | 2016-01-25 09:54:20 -0800 | [diff] [blame] | 712 | void emitInst(IValueT Value) { |
| 713 | AssemblerBuffer::EnsureCapacity _(&Buffer); |
| 714 | Buffer.emit<IValueT>(Value); |
| 715 | } |
Karl Schimpf | c5abdc1 | 2015-10-09 13:29:13 -0700 | [diff] [blame] | 716 | |
Karl Schimpf | b81b901 | 2015-11-04 14:54:52 -0800 | [diff] [blame] | 717 | // List of possible checks to apply when calling emitType01() (below). |
Karl Schimpf | f4d0a7a | 2015-11-19 08:10:44 -0800 | [diff] [blame] | 718 | enum EmitChecks { NoChecks, RdIsPcAndSetFlags }; |
| 719 | |
Karl Schimpf | 0437ae8 | 2015-12-04 07:29:10 -0800 | [diff] [blame] | 720 | // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=InstType, |
Karl Schimpf | f4d0a7a | 2015-11-19 08:10:44 -0800 | [diff] [blame] | 721 | // s=SetFlags, oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM |
| 722 | // section A5.2.3). |
Karl Schimpf | 0437ae8 | 2015-12-04 07:29:10 -0800 | [diff] [blame] | 723 | void emitType01(CondARM32::Cond Cond, IValueT InstType, IValueT Opcode, |
Karl Schimpf | f4d0a7a | 2015-11-19 08:10:44 -0800 | [diff] [blame] | 724 | bool SetFlags, IValueT Rn, IValueT Rd, IValueT imm12, |
Karl Schimpf | 0437ae8 | 2015-12-04 07:29:10 -0800 | [diff] [blame] | 725 | EmitChecks RuleChecks, const char *InstName); |
Karl Schimpf | b81b901 | 2015-11-04 14:54:52 -0800 | [diff] [blame] | 726 | |
| 727 | // Converts appropriate representation on a data operation, and then calls |
| 728 | // emitType01 above. |
Karl Schimpf | 0437ae8 | 2015-12-04 07:29:10 -0800 | [diff] [blame] | 729 | void emitType01(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRd, |
| 730 | const Operand *OpRn, const Operand *OpSrc1, bool SetFlags, |
| 731 | EmitChecks RuleChecks, const char *InstName); |
Karl Schimpf | b81b901 | 2015-11-04 14:54:52 -0800 | [diff] [blame] | 732 | |
| 733 | // Same as above, but the value for Rd and Rn have already been converted |
| 734 | // into instruction values. |
Karl Schimpf | 0437ae8 | 2015-12-04 07:29:10 -0800 | [diff] [blame] | 735 | void emitType01(CondARM32::Cond Cond, IValueT Opcode, IValueT OpRd, |
| 736 | IValueT OpRn, const Operand *OpSrc1, bool SetFlags, |
| 737 | EmitChecks RuleChecks, const char *InstName); |
Karl Schimpf | 62d367b | 2015-10-30 08:06:44 -0700 | [diff] [blame] | 738 | |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 739 | void emitType05(CondARM32::Cond Cond, int32_t Offset, bool Link); |
Karl Schimpf | 745ad1d | 2015-10-16 10:31:31 -0700 | [diff] [blame] | 740 | |
Karl Schimpf | 1956788 | 2015-12-02 10:24:15 -0800 | [diff] [blame] | 741 | // Emit ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, |
| 742 | // ooo=InstType, l=isLoad, b=isByte, and |
| 743 | // aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that Address is assumed to be |
| 744 | // defined by decodeAddress() in IceAssemblerARM32.cpp. |
Karl Schimpf | 137e62b | 2015-10-27 07:28:09 -0700 | [diff] [blame] | 745 | void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad, |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 746 | bool IsByte, IValueT Rt, IValueT Address); |
Karl Schimpf | 1956788 | 2015-12-02 10:24:15 -0800 | [diff] [blame] | 747 | |
Karl Schimpf | 17fe194 | 2015-12-18 07:41:06 -0800 | [diff] [blame] | 748 | // Emit ccccxxxxxxxxxxxxddddxxxxxxxxmmmm where cccc=Cond, |
| 749 | // xxxxxxxxxxxx0000xxxxxxxx0000=Opcode, dddd=Rd, and mmmm=Rm. |
| 750 | void emitRdRm(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRd, |
| 751 | const Operand *OpRm, const char *InstName); |
| 752 | |
Karl Schimpf | 1956788 | 2015-12-02 10:24:15 -0800 | [diff] [blame] | 753 | // Emit ldr/ldrb/str/strb instruction with given address. |
| 754 | void emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, IValueT Rt, |
Karl Schimpf | 0437ae8 | 2015-12-04 07:29:10 -0800 | [diff] [blame] | 755 | const Operand *OpAddress, const TargetInfo &TInfo, |
| 756 | const char *InstName); |
Karl Schimpf | 1956788 | 2015-12-02 10:24:15 -0800 | [diff] [blame] | 757 | |
| 758 | // Emit ldrh/ldrd/strh/strd instruction with given address using encoding 3. |
| 759 | void emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode, IValueT Rt, |
Karl Schimpf | 0437ae8 | 2015-12-04 07:29:10 -0800 | [diff] [blame] | 760 | const Operand *OpAddress, const TargetInfo &TInfo, |
| 761 | const char *InstName); |
Karl Schimpf | 137e62b | 2015-10-27 07:28:09 -0700 | [diff] [blame] | 762 | |
Karl Schimpf | 4175d45 | 2015-12-17 08:06:01 -0800 | [diff] [blame] | 763 | // Emit cccc00011xxlnnnndddd11111001tttt where cccc=Cond, xx encodes type |
| 764 | // size, l=IsLoad, nnnn=Rn (as defined by OpAddress), and tttt=Rt. |
| 765 | void emitMemExOp(CondARM32::Cond, Type Ty, bool IsLoad, const Operand *OpRd, |
| 766 | IValueT Rt, const Operand *OpAddress, |
| 767 | const TargetInfo &TInfo, const char *InstName); |
| 768 | |
Karl Schimpf | 6cab561 | 2015-11-06 09:14:10 -0800 | [diff] [blame] | 769 | // Pattern cccc100aaaalnnnnrrrrrrrrrrrrrrrr where cccc=Cond, |
| 770 | // aaaa<<21=AddressMode, l=IsLoad, nnnn=BaseReg, and |
| 771 | // rrrrrrrrrrrrrrrr is bitset of Registers. |
| 772 | void emitMultiMemOp(CondARM32::Cond Cond, BlockAddressMode AddressMode, |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 773 | bool IsLoad, IValueT BaseReg, IValueT Registers); |
Karl Schimpf | 6cab561 | 2015-11-06 09:14:10 -0800 | [diff] [blame] | 774 | |
Karl Schimpf | a3c3214 | 2015-12-18 08:26:16 -0800 | [diff] [blame] | 775 | // Pattern ccccxxxxxDxxxxxxddddxxxxiiiiiiii where cccc=Cond, ddddD=BaseReg, |
| 776 | // iiiiiiii=NumConsecRegs, and xxxxx0xxxxxx0000xxxx00000000=Opcode. |
| 777 | void emitVStackOp(CondARM32::Cond Cond, IValueT Opcode, |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 778 | const Variable *OpBaseReg, SizeT NumConsecRegs); |
Karl Schimpf | a3c3214 | 2015-12-18 08:26:16 -0800 | [diff] [blame] | 779 | |
Karl Schimpf | 6c7181c | 2016-01-08 07:31:08 -0800 | [diff] [blame] | 780 | // Pattern cccc111xxDxxxxxxdddd101xxxMxmmmm where cccc=Cond, ddddD=Sd, |
| 781 | // Mmmmm=Dm, and xx0xxxxxxdddd000xxx0x0000=Opcode. |
| 782 | void emitVFPsd(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, IValueT Dm); |
| 783 | |
| 784 | // Pattern cccc111xxDxxxxxxdddd101xxxMxmmmm where cccc=Cond, Ddddd=Dd, |
| 785 | // mmmmM=Sm, and xx0xxxxxxdddd000xxx0x0000=Opcode. |
| 786 | void emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, IValueT Sm); |
| 787 | |
Karl Schimpf | 18cce42 | 2016-02-04 13:54:53 -0800 | [diff] [blame] | 788 | // Pattern 111100000D00nnnnddddttttssaammmm | Opcode where Ddddd=Dd, nnnn=Rn, |
| 789 | // mmmmm=Rm, tttt=NumDRegs, ElmtSize in {8, 16, 32, 64) and defines ss, and |
| 790 | // aa=Align. |
| 791 | void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm, |
| 792 | DRegListSize NumDRegs, size_t ElmtSize, IValueT Align, |
| 793 | const char *InstName); |
| 794 | |
Nicolas Capens | 675e15b | 2017-09-27 15:06:35 -0400 | [diff] [blame] | 795 | // Pattern 111100000D00nnnnddddss00aaaammmm | Opcode where Ddddd=Dd, nnnn=Rn, |
| 796 | // mmmmm=Rm, ElmtSize in {8, 16, 32) and defines ss, and aa=Align. |
| 797 | void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm, |
| 798 | size_t ElmtSize, IValueT Align, const char *InstName); |
| 799 | |
Karl Schimpf | 697dc79 | 2015-10-30 13:21:59 -0700 | [diff] [blame] | 800 | // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond, |
| 801 | // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm. |
| 802 | void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn, |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 803 | IValueT Rm); |
Karl Schimpf | 697dc79 | 2015-10-30 13:21:59 -0700 | [diff] [blame] | 804 | |
Karl Schimpf | 6de32b2 | 2016-02-10 13:30:48 -0800 | [diff] [blame] | 805 | // cccc1110iiiennnntttt1011Njj10000 where cccc=Cond, tttt=Rt, Ndddd=2*Qn=Dn, |
| 806 | // iii=Opcode1, jj=Opcode2, Opcode1Opcode2 encodes Index and the |
| 807 | // corresponding element size of the vector element, and e=IsExtract. |
| 808 | void emitInsertExtractInt(CondARM32::Cond Cond, const Operand *OpQn, |
| 809 | uint32_t Index, const Operand *OpRt, bool IsExtract, |
| 810 | const char *InstName); |
| 811 | |
| 812 | // cccc11101D110000dddd101001M0mmmm where cccc=Cond, ddddD=Sd, and mmmmM=Sm. |
| 813 | // Assigns Sd the value of Sm. |
| 814 | void emitMoveSS(CondARM32::Cond Cond, IValueT Sd, IValueT Sm); |
| 815 | |
Karl Schimpf | 396de53 | 2015-10-30 07:25:43 -0700 | [diff] [blame] | 816 | // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn, |
Karl Schimpf | f4d0a7a | 2015-11-19 08:10:44 -0800 | [diff] [blame] | 817 | // mmmm=Rm, ssss=Rs, f=SetFlags and xxxxxxx=Opcode. |
Karl Schimpf | 396de53 | 2015-10-30 07:25:43 -0700 | [diff] [blame] | 818 | void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn, |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 819 | IValueT Rm, IValueT Rs, bool SetFlags); |
Karl Schimpf | 396de53 | 2015-10-30 07:25:43 -0700 | [diff] [blame] | 820 | |
Karl Schimpf | 4ddce70 | 2015-12-07 10:43:34 -0800 | [diff] [blame] | 821 | // Pattern cccc0001101s0000ddddxxxxxtt0mmmm where cccc=Cond, s=SetFlags, |
| 822 | // dddd=Rd, mmmm=Rm, tt=Shift, and xxxxx is defined by OpSrc1. OpSrc1 defines |
| 823 | // either xxxxx=Imm5, or xxxxx=ssss0 where ssss=Rs. |
| 824 | void emitShift(const CondARM32::Cond Cond, |
| 825 | const OperandARM32::ShiftKind Shift, const Operand *OpRd, |
| 826 | const Operand *OpRm, const Operand *OpSrc1, |
| 827 | const bool SetFlags, const char *InstName); |
| 828 | |
Karl Schimpf | 1e67f91 | 2015-12-08 11:17:23 -0800 | [diff] [blame] | 829 | // Implements various forms of signed/unsigned extend value, using pattern |
Karl Schimpf | bb0bacf | 2015-11-11 15:42:55 -0800 | [diff] [blame] | 830 | // ccccxxxxxxxxnnnnddddrr000111mmmm where cccc=Cond, xxxxxxxx<<20=Opcode, |
| 831 | // nnnn=Rn, dddd=Rd, rr=Rotation, and mmmm=Rm. |
Karl Schimpf | 1e67f91 | 2015-12-08 11:17:23 -0800 | [diff] [blame] | 832 | void emitSignExtend(CondARM32::Cond, IValueT Opcode, const Operand *OpRd, |
| 833 | const Operand *OpSrc0, const char *InstName); |
Karl Schimpf | bb0bacf | 2015-11-11 15:42:55 -0800 | [diff] [blame] | 834 | |
Karl Schimpf | 2c0764e | 2016-02-01 13:44:37 -0800 | [diff] [blame] | 835 | // Implements various forms of vector (SIMD) operations. Implements pattern |
Karl Schimpf | 425e06b | 2016-02-17 09:51:23 -0800 | [diff] [blame] | 836 | // 111100100D00nnnndddn00F0NQM0mmmm where Dddd=Dd, Nnnn=Dn, Mmmm=Dm, |
| 837 | // Q=UseQRegs, F=IsFloatTy, and Opcode is unioned into the pattern. |
| 838 | void emitSIMDBase(IValueT Opcode, IValueT Dd, IValueT Dn, IValueT Dm, |
| 839 | bool UseQRegs, bool IsFloatTy); |
| 840 | |
| 841 | // Same as emitSIMDBase above, except ElmtShift=20 and ElmtSize is computed |
| 842 | // from ElmtTy. |
Karl Schimpf | 2c0764e | 2016-02-01 13:44:37 -0800 | [diff] [blame] | 843 | void emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd, IValueT Dn, IValueT Dm, |
| 844 | bool UseQRegs); |
| 845 | |
| 846 | // Implements various integer forms of vector (SIMD) operations using Q |
Karl Schimpf | 425e06b | 2016-02-17 09:51:23 -0800 | [diff] [blame] | 847 | // registers. Implements pattern 111100100D00nnn0ddd000F0N1M0mmm0 where |
| 848 | // Dddd=Qd, Nnnn=Qn, Mmmm=Qm, F=IsFloatTy, and Opcode is unioned into the |
| 849 | // pattern. |
| 850 | void emitSIMDqqqBase(IValueT Opcode, const Operand *OpQd, const Operand *OpQn, |
| 851 | const Operand *OpQm, bool IsFloatTy, |
| 852 | const char *OpcodeName); |
| 853 | |
| 854 | // Same as emitSIMD above, except ElmtShift=20 and ElmtSize is computed from |
| 855 | // ElmtTy. |
Karl Schimpf | 2c0764e | 2016-02-01 13:44:37 -0800 | [diff] [blame] | 856 | void emitSIMDqqq(IValueT Opcode, Type ElmtTy, const Operand *OpQd, |
| 857 | const Operand *OpQn, const Operand *OpQm, |
| 858 | const char *OpcodeName); |
| 859 | |
John Porto | e88c7de | 2016-04-14 11:51:38 -0700 | [diff] [blame] | 860 | // Implements various forms of vector (SIMD) shifts using Q registers. |
| 861 | // Implements pattern 111100101Diiiiiidddd010101M1mmmm where Dddd=Qd, Mmmm=Qm, |
| 862 | // iiiiii=Imm6, and Opcode is unioned into the pattern. |
| 863 | void emitSIMDShiftqqc(IValueT Opcode, const Operand *OpQd, |
| 864 | const Operand *OpQm, const IValueT Imm6, |
| 865 | const char *OpcodeName); |
| 866 | |
| 867 | // Implements various forms of vector (SIMD) casts between (signed and |
| 868 | // unsigned) integer and floating point types (f32). Implements pattern |
| 869 | // 111100111D11ss11dddd011ooQM0mmmm where Dddd=Qd, Mmmm=Qm, 10=ss, op=00, 1=Q, |
| 870 | // and Opcode is unioned into the pattern. |
| 871 | void emitSIMDCvtqq(IValueT Opcode, const Operand *OpQd, const Operand *OpQm, |
| 872 | const char *CvtName); |
| 873 | |
Karl Schimpf | b81b901 | 2015-11-04 14:54:52 -0800 | [diff] [blame] | 874 | // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn, |
| 875 | // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from |
| 876 | // OpSrc1, and xxxx=Opcode. |
Karl Schimpf | 0437ae8 | 2015-12-04 07:29:10 -0800 | [diff] [blame] | 877 | void emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRn, |
| 878 | const Operand *OpSrc1, const char *CmpName); |
Karl Schimpf | b81b901 | 2015-11-04 14:54:52 -0800 | [diff] [blame] | 879 | |
Karl Schimpf | 137e62b | 2015-10-27 07:28:09 -0700 | [diff] [blame] | 880 | void emitBranch(Label *L, CondARM32::Cond, bool Link); |
| 881 | |
Karl Schimpf | 137e62b | 2015-10-27 07:28:09 -0700 | [diff] [blame] | 882 | // Returns the offset encoded in the branch instruction Inst. |
| 883 | static IOffsetT decodeBranchOffset(IValueT Inst); |
Karl Schimpf | 5ff0cfb | 2015-11-11 14:47:49 -0800 | [diff] [blame] | 884 | |
Karl Schimpf | 7cfe9a0 | 2015-12-04 15:07:01 -0800 | [diff] [blame] | 885 | // Implements movw/movt, generating pattern ccccxxxxxxxsiiiiddddiiiiiiiiiiii |
| 886 | // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and |
Karl Schimpf | 5ff0cfb | 2015-11-11 14:47:49 -0800 | [diff] [blame] | 887 | // iiiiiiiiiiiiiiii=Imm16. |
Karl Schimpf | 7cfe9a0 | 2015-12-04 15:07:01 -0800 | [diff] [blame] | 888 | void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd, |
| 889 | const Operand *OpSrc, const char *MovName); |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 890 | |
| 891 | // Emit VFP instruction with 3 D registers. |
Karl Schimpf | bd8e28e | 2016-01-26 12:25:43 -0800 | [diff] [blame] | 892 | void emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpDd, |
| 893 | const Operand *OpDn, const Operand *OpDm, |
| 894 | const char *InstName); |
| 895 | |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 896 | void emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, IValueT Dn, |
| 897 | IValueT Dm); |
| 898 | |
| 899 | // Emit VFP instruction with 3 S registers. |
| 900 | void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, IValueT Sn, |
| 901 | IValueT Sm); |
Karl Schimpf | bd8e28e | 2016-01-26 12:25:43 -0800 | [diff] [blame] | 902 | |
| 903 | void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd, |
| 904 | const Operand *OpSn, const Operand *OpSm, |
| 905 | const char *InstName); |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 906 | }; |
| 907 | |
Jan Voung | 90ccc3f | 2015-04-30 14:15:10 -0700 | [diff] [blame] | 908 | } // end of namespace ARM32 |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 909 | } // end of namespace Ice |
| 910 | |
John Porto | aff4ccf | 2015-06-10 16:35:06 -0700 | [diff] [blame] | 911 | #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H |