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gerrit-public.fairphone.software / platform / external / swiftshader / 4474108312ef793520e594fd556a5f95c5df93e8 / . / third_party / subzero / src / IceInstX8632.def
blob: c71d6df56d64d9087e990e04d2376ff8bd92e659 [file] [log] [blame]
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]1//===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
2//
3// The Subzero Code Generator
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines properties of lowered x86-32 instructions in the
11// form of x-macros.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SUBZERO_SRC_ICEINSTX8632_DEF
16#define SUBZERO_SRC_ICEINSTX8632_DEF
17
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]18#include "IceRegList.h"
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]19
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]20// x86-32 ABI:
21// Scratch GPRs: eax, ecx, edx
22// Callee-save GPRs: ebx, ebp, esi, edi
23// Scratch XMMs: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
24// Key to table columns:
25// val: Enum value, when a specific register is needed during lowering.
26// encode: Encoding in the integrated assembler.
27// name: Name used for the external assembler.
28// scratch: Scratch (caller-save) register.
29// preserved: Preserved (callee-save) register.
30// stackptr: This register is used as the stack pointer.
31// frameptr: This register is used as the frame pointer if needed.
32// isGPR: This is a GPR (integer-type).
33// is64: This is a 64-bit GPR.
34// is32: This is a 32-bit GPR.
35// is16: This is a 16-bit GPR.
36// is8: This is an 8-bit GPR.
37// isXmm: This is an XMM register for FP and vector ops.
38// is64To8: A 64-bit GPR truncable to 8-bit.
39// is32To8: A 32-bit GPR truncable to 8-bit.
40// is16To8: A 16-bit GPR truncable to 8-bit.
41// isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to.
42// isAhRcvr: An 8-bit GPR that register "ah" can be assigned to.
43// aliases: List of register aliases, which need not include this register.
44#define REGX8632_BYTEREG_TABLE \
45 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
46 isGPR,is64,is32,is16,is8, isXmm, \
47 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
48 /* 8-bit registers */ \
49 X(Reg_al, 0, "al", Reg_eax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
50 REGLIST2(RegX8632, eax, ax)) \
51 X(Reg_cl, 1, "cl", Reg_ecx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
52 REGLIST2(RegX8632, ecx, cx)) \
53 X(Reg_dl, 2, "dl", Reg_edx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
54 REGLIST2(RegX8632, edx, dx)) \
55 X(Reg_bl, 3, "bl", Reg_ebx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
56 REGLIST2(RegX8632, ebx, bx)) \
57 /* High 8-bit registers */ \
Jim Stichnothc59288b2015-11-09 11:38:40 -0800[diff] [blame]58 X(Reg_ah, 4, "ah", Reg_eax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,0,1, \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]59 REGLIST2(RegX8632, eax, ax)) \
Jim Stichnothc59288b2015-11-09 11:38:40 -0800[diff] [blame]60 X(Reg_ch, 5, "ch", Reg_ecx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,0,1, \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]61 REGLIST2(RegX8632, ecx, cx)) \
Jim Stichnothc59288b2015-11-09 11:38:40 -0800[diff] [blame]62 X(Reg_dh, 6, "dh", Reg_edx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,0,1, \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]63 REGLIST2(RegX8632, edx, dx)) \
Jim Stichnothc59288b2015-11-09 11:38:40 -0800[diff] [blame]64 X(Reg_bh, 7, "bh", Reg_ebx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,0,1, \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]65 REGLIST2(RegX8632, ebx, bx)) \
66 /* End of 8-bit register set */
67//#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
68// isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
69// isTrunc8Rcvr, isAhRcvr, aliases)
70
71#define REGX8632_GPR_TABLE \
72 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
73 isGPR,is64,is32,is16,is8, isXmm, \
74 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
75 /* 32-bit registers */ \
76 X(Reg_eax, 0, "eax", Reg_eax, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
77 REGLIST3(RegX8632, ax, al, ah)) \
78 X(Reg_ecx, 1, "ecx", Reg_ecx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
79 REGLIST3(RegX8632, cx, cl, ch)) \
80 X(Reg_edx, 2, "edx", Reg_edx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
81 REGLIST3(RegX8632, dx, dl, dh)) \
82 X(Reg_ebx, 3, "ebx", Reg_ebx, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
83 REGLIST3(RegX8632, bx, bl, bh)) \
84 X(Reg_esp, 4, "esp", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
85 REGLIST1(RegX8632, sp)) \
86 X(Reg_ebp, 5, "ebp", Reg_ebp, 0,1,0,1, 1,0,1,0,0, 0, 0,0,0,0,0, \
87 REGLIST1(RegX8632, bp)) \
88 X(Reg_esi, 6, "esi", Reg_esi, 0,1,0,0, 1,0,1,0,0, 0, 0,0,0,0,0, \
89 REGLIST1(RegX8632, si)) \
90 X(Reg_edi, 7, "edi", Reg_edi, 0,1,0,0, 1,0,1,0,0, 0, 0,0,0,0,0, \
91 REGLIST1(RegX8632, di)) \
92 /* 16-bit registers */ \
93 X(Reg_ax, 0, "ax", Reg_eax, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
94 REGLIST3(RegX8632, eax, al, ah)) \
95 X(Reg_cx, 1, "cx", Reg_ecx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
96 REGLIST3(RegX8632, ecx, cl, ch)) \
97 X(Reg_dx, 2, "dx", Reg_edx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
98 REGLIST3(RegX8632, edx, dl, dh)) \
99 X(Reg_bx, 3, "bx", Reg_ebx, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
100 REGLIST3(RegX8632, ebx, bl, bh)) \
101 X(Reg_sp, 4, "sp", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
102 REGLIST1(RegX8632, esp)) \
103 X(Reg_bp, 5, "bp", Reg_ebp, 0,1,0,1, 1,0,0,1,0, 0, 0,0,0,0,0, \
104 REGLIST1(RegX8632, ebp)) \
105 X(Reg_si, 6, "si", Reg_esi, 0,1,0,0, 1,0,0,1,0, 0, 0,0,0,0,0, \
106 REGLIST1(RegX8632, esi)) \
107 X(Reg_di, 7, "di", Reg_edi, 0,1,0,0, 1,0,0,1,0, 0, 0,0,0,0,0, \
108 REGLIST1(RegX8632, edi)) \
109 /* 8-bit registers */ \
110 REGX8632_BYTEREG_TABLE \
111 /* End of GPR register set */
112//#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
113// isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
114// isTrunc8Rcvr, isAhRcvr, aliases)
115
116// Note: It would be more appropriate to list the xmm register aliases as
117// REGLIST0(), but the corresponding empty initializer gives a syntax error, so
118// we use REGLIST1() to redundantly assign the register itself as an alias.
119#define REGX8632_XMM_TABLE \
120 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
121 isGPR,is64,is32,is16,is8, isXmm, \
122 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
123 /* xmm registers */ \
124 X(Reg_xmm0, 0, "xmm0", Reg_xmm0, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
John Porto4a308ce2015-12-30 09:55:04 -0800[diff] [blame]125 NO_ALIASES()) \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]126 X(Reg_xmm1, 1, "xmm1", Reg_xmm1, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
John Porto4a308ce2015-12-30 09:55:04 -0800[diff] [blame]127 NO_ALIASES()) \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]128 X(Reg_xmm2, 2, "xmm2", Reg_xmm2, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
John Porto4a308ce2015-12-30 09:55:04 -0800[diff] [blame]129 NO_ALIASES()) \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]130 X(Reg_xmm3, 3, "xmm3", Reg_xmm3, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
John Porto4a308ce2015-12-30 09:55:04 -0800[diff] [blame]131 NO_ALIASES()) \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]132 X(Reg_xmm4, 4, "xmm4", Reg_xmm4, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
John Porto4a308ce2015-12-30 09:55:04 -0800[diff] [blame]133 NO_ALIASES()) \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]134 X(Reg_xmm5, 5, "xmm5", Reg_xmm5, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
John Porto4a308ce2015-12-30 09:55:04 -0800[diff] [blame]135 NO_ALIASES()) \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]136 X(Reg_xmm6, 6, "xmm6", Reg_xmm6, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
John Porto4a308ce2015-12-30 09:55:04 -0800[diff] [blame]137 NO_ALIASES()) \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]138 X(Reg_xmm7, 7, "xmm7", Reg_xmm7, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
John Porto4a308ce2015-12-30 09:55:04 -0800[diff] [blame]139 NO_ALIASES()) \
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]140 /* End of xmm register set */
141//#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
142// isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
143// isTrunc8Rcvr, isAhRcvr, aliases)
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]144
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]145// We also provide a combined table, so that there is a namespace where
146// all of the registers are considered and have distinct numberings.
147// This is in contrast to the above, where the "encode" is based on how
148// the register numbers will be encoded in binaries and values can overlap.
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]149#define REGX8632_TABLE \
150 REGX8632_GPR_TABLE \
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]151 REGX8632_XMM_TABLE
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]152//#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
153// isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
154// isTrunc8Rcvr, isAhRcvr, aliases)
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]155
Jan Voung3bd9f1a2014-06-18 10:50:57 -0700[diff] [blame]156// X86 segment registers.
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]157#define SEG_REGX8632_TABLE \
158 /* val, name, prefix */ \
159 X(SegReg_CS, "cs", 0x2E) \
160 X(SegReg_DS, "ds", 0x3E) \
161 X(SegReg_ES, "es", 0x26) \
162 X(SegReg_SS, "ss", 0x36) \
163 X(SegReg_FS, "fs", 0x64) \
164 X(SegReg_GS, "gs", 0x65)
Jan Voungfe14fb82014-10-13 15:56:32 -0700[diff] [blame]165//#define X(val, name, prefix)
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]166
Jan Voung479e5632014-10-08 21:05:27 -0700[diff] [blame]167// X87 ST(n) registers.
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]168#define X87ST_REGX8632_TABLE \
169 /* val, encode, name */ \
170 X(X87ST_First, 0, "st(0)") \
171 X(X87ST_0, 0, "st(0)") \
172 X(X87ST_1, 1, "st(1)") \
173 X(X87ST_2, 2, "st(2)") \
174 X(X87ST_3, 3, "st(3)") \
175 X(X87ST_4, 4, "st(4)") \
176 X(X87ST_5, 5, "st(5)") \
177 X(X87ST_6, 6, "st(6)") \
178 X(X87ST_7, 7, "st(7)") \
179 X(X87ST_Last, 7, "st(7)")
Jan Voung479e5632014-10-08 21:05:27 -0700[diff] [blame]180//#define X(val, encode, name)
181
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]182#define ICEINSTX8632BR_TABLE \
183 /* val, encode, opposite, dump, emit */ \
184 X(Br_o, 0, Br_no, "o", "jo") \
185 X(Br_no, 1, Br_o, "no", "jno") \
186 X(Br_b, 2, Br_ae, "b", "jb") \
187 X(Br_ae, 3, Br_b, "ae", "jae") \
188 X(Br_e, 4, Br_ne, "e", "je") \
189 X(Br_ne, 5, Br_e, "ne", "jne") \
190 X(Br_be, 6, Br_a, "be", "jbe") \
191 X(Br_a, 7, Br_be, "a", "ja") \
192 X(Br_s, 8, Br_ns, "s", "js") \
193 X(Br_ns, 9, Br_s, "ns", "jns") \
194 X(Br_p, 10, Br_np, "p", "jp") \
195 X(Br_np, 11, Br_p, "np", "jnp") \
196 X(Br_l, 12, Br_ge, "l", "jl") \
197 X(Br_ge, 13, Br_l, "ge", "jge") \
198 X(Br_le, 14, Br_g, "le", "jle") \
199 X(Br_g, 15, Br_le, "g", "jg")
200//#define X(val, encode, opp, dump, emit)
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]201
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]202#define ICEINSTX8632CMPPS_TABLE \
203 /* val, emit */ \
204 X(Cmpps_eq, "eq") \
205 X(Cmpps_lt, "lt") \
206 X(Cmpps_le, "le") \
207 X(Cmpps_unord, "unord") \
208 X(Cmpps_neq, "neq") \
209 X(Cmpps_nlt, "nlt") \
210 X(Cmpps_nle, "nle") \
211 X(Cmpps_ord, "ord")
212//#define X(val, emit)
Matt Walace0ca8f2014-07-24 12:34:20 -0700[diff] [blame]213
Jim Stichnoth5bff61c2015-10-28 09:26:00 -0700[diff] [blame]214#define ICETYPEX8632_TABLE \
Nicolas Capens7638e272016-10-06 11:33:55 -0400[diff] [blame]215 /* tag, elty, cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld */ \
216 X(void, void, "?", "", "", "", "", "", "", "", "") \
217 X(i1, void, "si", "", "", "", "", "", "", "b", "") \
218 X(i8, void, "si", "", "", "", "", "", "", "b", "") \
219 X(i16, void, "si", "", "", "", "", "", "", "w", "") \
220 X(i32, void, "si", "", "", "", "", "", "", "l", "") \
221 X(i64, void, "si", "", "", "", "", "", "", "q", "") \
222 X(f32, void, "ss", "ss", "ps", "ss", "d", "", "", "", "s") \
223 X(f64, void, "sd", "sd", "pd", "sd", "q", "", "", "", "l") \
224 X(v4i1, i32, "?", "", "", "", "d", "dq", "", "", "") \
225 X(v8i1, i16, "?", "", "", "", "w", "wd", "", "", "") \
226 X(v16i1, i8, "?", "", "", "", "b", "bw", "", "", "") \
227 X(v16i8, i8, "?", "", "", "", "b", "bw", "", "", "") \
228 X(v8i16, i16, "?", "", "", "", "w", "wd", "wb", "", "") \
229 X(v4i32, i32, "dq", "", "", "", "d", "dq", "dw", "", "") \
230 X(v4f32, f32, "ps", "", "ps", "ps", "d", "dq", "", "", "")
231//#define X(tag, elty, cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld)
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]232
233#endif // SUBZERO_SRC_ICEINSTX8632_DEF