Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 1 | //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===// |
| 2 | // |
| 3 | // The Subzero Code Generator |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Andrew Scull | 9612d32 | 2015-07-06 14:53:25 -0700 | [diff] [blame] | 9 | /// |
| 10 | /// \file |
Jim Stichnoth | 92a6e5b | 2015-12-02 16:52:44 -0800 | [diff] [blame] | 11 | /// \brief Declares the registers and their encodings for ARM32. |
Andrew Scull | 9612d32 | 2015-07-06 14:53:25 -0700 | [diff] [blame] | 12 | /// |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #ifndef SUBZERO_SRC_ICEREGISTERSARM32_H |
| 16 | #define SUBZERO_SRC_ICEREGISTERSARM32_H |
| 17 | |
| 18 | #include "IceDefs.h" |
| 19 | #include "IceInstARM32.def" |
Jim Stichnoth | c59288b | 2015-11-09 11:38:40 -0800 | [diff] [blame] | 20 | #include "IceOperand.h" // RC_Target |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 21 | #include "IceTypes.h" |
| 22 | |
| 23 | namespace Ice { |
John Porto | 4a56686 | 2016-01-04 09:33:41 -0800 | [diff] [blame] | 24 | namespace ARM32 { |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 25 | namespace RegARM32 { |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 26 | |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 27 | /// An enum of every register. The enum value may not match the encoding used |
| 28 | /// to binary encode register operands in instructions. |
| 29 | enum AllRegisters { |
John Porto | 2187c84 | 2015-12-16 07:48:25 -0800 | [diff] [blame] | 30 | #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
John Porto | dff7dbd | 2016-01-04 09:49:55 -0800 | [diff] [blame] | 31 | isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 32 | val, |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 33 | REGARM32_TABLE |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 34 | #undef X |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 35 | Reg_NUM, |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 36 | #define X(val, init) val init, |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 37 | REGARM32_TABLE_BOUNDS |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 38 | #undef X |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 39 | }; |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 40 | |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 41 | /// An enum of GPR Registers. The enum value does match the encoding used to |
| 42 | /// binary encode register operands in instructions. |
| 43 | enum GPRRegister { |
John Porto | 2187c84 | 2015-12-16 07:48:25 -0800 | [diff] [blame] | 44 | #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
John Porto | dff7dbd | 2016-01-04 09:49:55 -0800 | [diff] [blame] | 45 | isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 46 | Encoded_##val = encode, |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 47 | REGARM32_GPR_TABLE |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 48 | #undef X |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 49 | Encoded_Not_GPR = -1 |
| 50 | }; |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 51 | |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 52 | /// An enum of FP32 S-Registers. The enum value does match the encoding used |
| 53 | /// to binary encode register operands in instructions. |
| 54 | enum SRegister { |
John Porto | 2187c84 | 2015-12-16 07:48:25 -0800 | [diff] [blame] | 55 | #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
John Porto | dff7dbd | 2016-01-04 09:49:55 -0800 | [diff] [blame] | 56 | isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 57 | Encoded_##val = encode, |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 58 | REGARM32_FP32_TABLE |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 59 | #undef X |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 60 | Encoded_Not_SReg = -1 |
| 61 | }; |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 62 | |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 63 | /// An enum of FP64 D-Registers. The enum value does match the encoding used |
| 64 | /// to binary encode register operands in instructions. |
| 65 | enum DRegister { |
John Porto | 2187c84 | 2015-12-16 07:48:25 -0800 | [diff] [blame] | 66 | #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
John Porto | dff7dbd | 2016-01-04 09:49:55 -0800 | [diff] [blame] | 67 | isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 68 | Encoded_##val = encode, |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 69 | REGARM32_FP64_TABLE |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 70 | #undef X |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 71 | Encoded_Not_DReg = -1 |
| 72 | }; |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 73 | |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 74 | /// An enum of 128-bit Q-Registers. The enum value does match the encoding |
| 75 | /// used to binary encode register operands in instructions. |
| 76 | enum QRegister { |
John Porto | 2187c84 | 2015-12-16 07:48:25 -0800 | [diff] [blame] | 77 | #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
John Porto | dff7dbd | 2016-01-04 09:49:55 -0800 | [diff] [blame] | 78 | isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 79 | Encoded_##val = encode, |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 80 | REGARM32_VEC128_TABLE |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 81 | #undef X |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 82 | Encoded_Not_QReg = -1 |
| 83 | }; |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 84 | |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 85 | extern struct RegTableType { |
| 86 | const char *Name; |
| 87 | unsigned Encoding : 10; |
| 88 | unsigned CCArg : 6; |
| 89 | unsigned Scratch : 1; |
| 90 | unsigned Preserved : 1; |
| 91 | unsigned StackPtr : 1; |
| 92 | unsigned FramePtr : 1; |
| 93 | unsigned IsGPR : 1; |
| 94 | unsigned IsInt : 1; |
| 95 | unsigned IsI64Pair : 1; |
| 96 | unsigned IsFP32 : 1; |
| 97 | unsigned IsFP64 : 1; |
| 98 | unsigned IsVec128 : 1; |
John Porto | 149999e | 2016-01-04 13:45:26 -0800 | [diff] [blame] | 99 | #define NUM_ALIASES_BITS 3 |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 100 | SizeT NumAliases : (NUM_ALIASES_BITS + 1); |
| 101 | uint16_t Aliases[1 << NUM_ALIASES_BITS]; |
John Porto | 149999e | 2016-01-04 13:45:26 -0800 | [diff] [blame] | 102 | #undef NUM_ALIASES_BITS |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 103 | } RegTable[Reg_NUM]; |
| 104 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 105 | static inline void assertValidRegNum(RegNumT RegNum) { |
| 106 | (void)RegNum; |
Reed Kotler | 5fa0a5f | 2016-02-15 20:01:24 -0800 | [diff] [blame] | 107 | assert(RegNum.hasValue()); |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | static inline bool isGPRegister(RegNumT RegNum) { |
| 111 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 112 | return RegTable[RegNum].IsGPR; |
| 113 | } |
| 114 | |
| 115 | static constexpr inline SizeT getNumGPRegs() { |
| 116 | return 0 |
John Porto | 149999e | 2016-01-04 13:45:26 -0800 | [diff] [blame] | 117 | #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
| 118 | isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 119 | +(isGPR) |
John Porto | 149999e | 2016-01-04 13:45:26 -0800 | [diff] [blame] | 120 | REGARM32_TABLE |
| 121 | #undef X |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 122 | ; |
| 123 | } |
John Porto | 149999e | 2016-01-04 13:45:26 -0800 | [diff] [blame] | 124 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 125 | static inline GPRRegister getEncodedGPR(RegNumT RegNum) { |
| 126 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 127 | return GPRRegister(RegTable[RegNum].Encoding); |
| 128 | } |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 129 | |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 130 | static constexpr inline SizeT getNumGPRs() { |
| 131 | return 0 |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 132 | #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
| 133 | isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
| 134 | +(isGPR) |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 135 | REGARM32_TABLE |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 136 | #undef X |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 137 | ; |
| 138 | } |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 139 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 140 | static inline bool isGPR(RegNumT RegNum) { |
| 141 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 142 | return RegTable[RegNum].IsGPR; |
| 143 | } |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 144 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 145 | static inline GPRRegister getI64PairFirstGPRNum(RegNumT RegNum) { |
| 146 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 147 | return GPRRegister(RegTable[RegNum].Encoding); |
| 148 | } |
Karl Schimpf | c411dbf | 2016-01-11 09:59:19 -0800 | [diff] [blame] | 149 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 150 | static inline GPRRegister getI64PairSecondGPRNum(RegNumT RegNum) { |
| 151 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 152 | return GPRRegister(RegTable[RegNum].Encoding + 1); |
| 153 | } |
Karl Schimpf | c411dbf | 2016-01-11 09:59:19 -0800 | [diff] [blame] | 154 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 155 | static inline bool isI64RegisterPair(RegNumT RegNum) { |
| 156 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 157 | return RegTable[RegNum].IsI64Pair; |
| 158 | } |
Karl Schimpf | c411dbf | 2016-01-11 09:59:19 -0800 | [diff] [blame] | 159 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 160 | static inline bool isEncodedSReg(RegNumT RegNum) { |
| 161 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 162 | return RegTable[RegNum].IsFP32; |
| 163 | } |
John Porto | ed2c06b | 2015-10-01 15:27:15 -0700 | [diff] [blame] | 164 | |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 165 | static constexpr inline SizeT getNumSRegs() { |
| 166 | return 0 |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 167 | #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
| 168 | isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
| 169 | +(isFP32) |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 170 | REGARM32_TABLE |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 171 | #undef X |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 172 | ; |
| 173 | } |
Karl Schimpf | a3c3214 | 2015-12-18 08:26:16 -0800 | [diff] [blame] | 174 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 175 | static inline SRegister getEncodedSReg(RegNumT RegNum) { |
| 176 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 177 | return SRegister(RegTable[RegNum].Encoding); |
| 178 | } |
Karl Schimpf | c411dbf | 2016-01-11 09:59:19 -0800 | [diff] [blame] | 179 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 180 | static inline bool isEncodedDReg(RegNumT RegNum) { |
| 181 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 182 | return RegTable[RegNum].IsFP64; |
| 183 | } |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 184 | |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 185 | static constexpr inline SizeT getNumDRegs() { |
| 186 | return 0 |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 187 | #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
| 188 | isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
| 189 | +(isFP64) |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 190 | REGARM32_TABLE |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 191 | #undef X |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 192 | ; |
| 193 | } |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 194 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 195 | static inline DRegister getEncodedDReg(RegNumT RegNum) { |
| 196 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 197 | return DRegister(RegTable[RegNum].Encoding); |
| 198 | } |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 199 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 200 | static inline bool isEncodedQReg(RegNumT RegNum) { |
| 201 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 202 | return RegTable[RegNum].IsVec128; |
| 203 | } |
Karl Schimpf | 4acf11a | 2016-01-07 07:31:19 -0800 | [diff] [blame] | 204 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 205 | static inline QRegister getEncodedQReg(RegNumT RegNum) { |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 206 | assert(isEncodedQReg(RegNum)); |
| 207 | return QRegister(RegTable[RegNum].Encoding); |
| 208 | } |
Karl Schimpf | 7cb2db3 | 2015-10-29 14:04:12 -0700 | [diff] [blame] | 209 | |
Jim Stichnoth | 467ffe5 | 2016-03-29 15:01:06 -0700 | [diff] [blame] | 210 | static inline const char *getRegName(RegNumT RegNum) { |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 211 | RegNum.assertIsValid(); |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 212 | return RegTable[RegNum].Name; |
| 213 | } |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 214 | |
Eric Holk | 658bae2 | 2016-02-08 15:22:18 -0800 | [diff] [blame] | 215 | // Extend enum RegClass with ARM32-specific register classes. |
| 216 | enum RegClassARM32 : uint8_t { |
| 217 | RCARM32_QtoS = RC_Target, // Denotes Q registers that are aliased by S |
| 218 | // registers. |
| 219 | RCARM32_NUM |
| 220 | }; |
Jim Stichnoth | c59288b | 2015-11-09 11:38:40 -0800 | [diff] [blame] | 221 | |
Karl Schimpf | 57ec7df | 2016-01-15 08:11:00 -0800 | [diff] [blame] | 222 | } // end of namespace RegARM32 |
John Porto | 4a56686 | 2016-01-04 09:33:41 -0800 | [diff] [blame] | 223 | } // end of namespace ARM32 |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 224 | } // end of namespace Ice |
| 225 | |
| 226 | #endif // SUBZERO_SRC_ICEREGISTERSARM32_H |