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gerrit-public.fairphone.software / platform / external / swiftshader / 5300bfe5c1b6dd711f77284691c920fc6c830873 / . / src / IceInstARM32.def
blob: 1836667f70f102d2ad95c858dc1cf4ff29cc0846 [file] [log] [blame]
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]1//===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
2//
3// The Subzero Code Generator
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines properties of ARM32 instructions in the form of x-macros.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef SUBZERO_SRC_ICEINSTARM32_DEF
15#define SUBZERO_SRC_ICEINSTARM32_DEF
16
17// NOTE: PC and SP are not considered isInt, to avoid register allocating.
Jan Voung0fa6c5a2015-06-01 11:04:04 -0700[diff] [blame]18//
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]19// For the NaCl sandbox we also need to r9 for TLS, so just reserve always.
20// TODO(jvoung): Allow r9 to be isInt when sandboxing is turned off
21// (native mode).
Jan Voung0fa6c5a2015-06-01 11:04:04 -0700[diff] [blame]22//
Jan Voung28068ad2015-07-31 12:58:46 -0700[diff] [blame]23// IP is not considered isInt to reserve it as a scratch register. A scratch
24// register is useful for expanding instructions post-register allocation.
25//
Jan Voung0fa6c5a2015-06-01 11:04:04 -0700[diff] [blame]26// LR is not considered isInt to avoid being allocated as a register.
27// It is technically preserved, but save/restore is handled separately,
28// based on whether or not the function MaybeLeafFunc.
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]29
30// ALIASESn is a family of macros that we use to define register aliasing in
31// ARM32. n indicates how many aliases are being provided to the macro. It
32// assumes the parameters are register names declared in a namespace/class named
33// RegARM32.
34#define ALIASES1(r0) \
35 {RegARM32::r0}
36#define ALIASES2(r0, r1) \
37 {RegARM32::r0, RegARM32::r1}
38#define ALIASES3(r0, r1, r2) \
39 {RegARM32::r0, RegARM32::r1, RegARM32::r2}
40#define ALIASES4(r0, r1, r2, r3) \
41 {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3}
42#define ALIASES7(r0, r1, r2, r3, r4, r5, r6) \
43 {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3, RegARM32::r4, \
44 RegARM32::r5,RegARM32::r6}
45
46
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]47#define REGARM32_GPR_TABLE \
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]48 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]49 isInt, isFP32, isFP64, isVec128, aliases_init */ \
50 X(Reg_r0, 0, "r0", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r0)) \
51 X(Reg_r1, 1, "r1", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r1)) \
52 X(Reg_r2, 2, "r2", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r2)) \
53 X(Reg_r3, 3, "r3", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r3)) \
54 X(Reg_r4, 4, "r4", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r4)) \
55 X(Reg_r5, 5, "r5", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r5)) \
56 X(Reg_r6, 6, "r6", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r6)) \
57 X(Reg_r7, 7, "r7", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r7)) \
58 X(Reg_r8, 8, "r8", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r8)) \
59 X(Reg_r9, 9, "r9", 0, 1, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_r9)) \
60 X(Reg_r10, 10, "r10", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r10)) \
61 X(Reg_fp, 11, "fp", 0, 1, 0, 1, 1, 0, 0, 0, ALIASES1(Reg_fp)) \
62 X(Reg_ip, 12, "ip", 1, 0, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_ip)) \
63 X(Reg_sp, 13, "sp", 0, 0, 1, 0, 0, 0, 0, 0, ALIASES1(Reg_sp)) \
64 X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_lr)) \
65 X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_pc))
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]66//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]67// isInt, isFP32, isFP64, isVec128, aliases_init)
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]68
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]69// S registers 0-15 are scratch, but 16-31 are preserved.
70// Regenerate this with the following python script:
71//
72// def print_sregs():
73// for i in xrange(0, 32):
74// is_scratch = 1 if i < 16 else 0
75// is_preserved = 1 if i >= 16 else 0
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]76// print (' X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' +
77// '{scratch}, {preserved}, 0, 0, 0, 1, 0, 0, ' +
78// 'ALIASES(Reg_s{regnum_s:<2}, Reg_d{regnum:<2}, ' +
79// 'Reg_q{regnum_q:<2})) \\').format(
80// regnum=i, regnum_d=i>>1,
81// regnum_q=i>>2, scratch=is_scratch, preserved=is_preserved)
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]82//
83// print_sregs()
84//
85#define REGARM32_FP32_TABLE \
86 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]87 isInt, isFP32, isFP64, isVec128, aliases_init */ \
88 X(Reg_s0 , 0 , "s0" , 1, 0, 0, 0, 0, 1, 0, 0, \
89 ALIASES3(Reg_s0 , Reg_d0 , Reg_q0)) \
90 X(Reg_s1 , 1 , "s1" , 1, 0, 0, 0, 0, 1, 0, 0, \
91 ALIASES3(Reg_s1 , Reg_d0 , Reg_q0)) \
92 X(Reg_s2 , 2 , "s2" , 1, 0, 0, 0, 0, 1, 0, 0, \
93 ALIASES3(Reg_s2 , Reg_d1 , Reg_q0)) \
94 X(Reg_s3 , 3 , "s3" , 1, 0, 0, 0, 0, 1, 0, 0, \
95 ALIASES3(Reg_s3 , Reg_d1 , Reg_q0)) \
96 X(Reg_s4 , 4 , "s4" , 1, 0, 0, 0, 0, 1, 0, 0, \
97 ALIASES3(Reg_s4 , Reg_d2 , Reg_q1)) \
98 X(Reg_s5 , 5 , "s5" , 1, 0, 0, 0, 0, 1, 0, 0, \
99 ALIASES3(Reg_s5 , Reg_d2 , Reg_q1)) \
100 X(Reg_s6 , 6 , "s6" , 1, 0, 0, 0, 0, 1, 0, 0, \
101 ALIASES3(Reg_s6 , Reg_d3 , Reg_q1)) \
102 X(Reg_s7 , 7 , "s7" , 1, 0, 0, 0, 0, 1, 0, 0, \
103 ALIASES3(Reg_s7 , Reg_d3 , Reg_q1)) \
104 X(Reg_s8 , 8 , "s8" , 1, 0, 0, 0, 0, 1, 0, 0, \
105 ALIASES3(Reg_s8 , Reg_d4 , Reg_q2)) \
106 X(Reg_s9 , 9 , "s9" , 1, 0, 0, 0, 0, 1, 0, 0, \
107 ALIASES3(Reg_s9 , Reg_d4 , Reg_q2)) \
108 X(Reg_s10, 10, "s10", 1, 0, 0, 0, 0, 1, 0, 0, \
109 ALIASES3(Reg_s10, Reg_d5 , Reg_q2)) \
110 X(Reg_s11, 11, "s11", 1, 0, 0, 0, 0, 1, 0, 0, \
111 ALIASES3(Reg_s11, Reg_d5 , Reg_q2)) \
112 X(Reg_s12, 12, "s12", 1, 0, 0, 0, 0, 1, 0, 0, \
113 ALIASES3(Reg_s12, Reg_d6 , Reg_q3)) \
114 X(Reg_s13, 13, "s13", 1, 0, 0, 0, 0, 1, 0, 0, \
115 ALIASES3(Reg_s13, Reg_d6 , Reg_q3)) \
116 X(Reg_s14, 14, "s14", 1, 0, 0, 0, 0, 1, 0, 0, \
117 ALIASES3(Reg_s14, Reg_d7 , Reg_q3)) \
118 X(Reg_s15, 15, "s15", 1, 0, 0, 0, 0, 1, 0, 0, \
119 ALIASES3(Reg_s15, Reg_d7 , Reg_q3)) \
120 X(Reg_s16, 16, "s16", 0, 1, 0, 0, 0, 1, 0, 0, \
121 ALIASES3(Reg_s16, Reg_d8 , Reg_q4)) \
122 X(Reg_s17, 17, "s17", 0, 1, 0, 0, 0, 1, 0, 0, \
123 ALIASES3(Reg_s17, Reg_d8 , Reg_q4)) \
124 X(Reg_s18, 18, "s18", 0, 1, 0, 0, 0, 1, 0, 0, \
125 ALIASES3(Reg_s18, Reg_d9 , Reg_q4)) \
126 X(Reg_s19, 19, "s19", 0, 1, 0, 0, 0, 1, 0, 0, \
127 ALIASES3(Reg_s19, Reg_d9 , Reg_q4)) \
128 X(Reg_s20, 20, "s20", 0, 1, 0, 0, 0, 1, 0, 0, \
129 ALIASES3(Reg_s20, Reg_d10, Reg_q5)) \
130 X(Reg_s21, 21, "s21", 0, 1, 0, 0, 0, 1, 0, 0, \
131 ALIASES3(Reg_s21, Reg_d10, Reg_q5)) \
132 X(Reg_s22, 22, "s22", 0, 1, 0, 0, 0, 1, 0, 0, \
133 ALIASES3(Reg_s22, Reg_d11, Reg_q5)) \
134 X(Reg_s23, 23, "s23", 0, 1, 0, 0, 0, 1, 0, 0, \
135 ALIASES3(Reg_s23, Reg_d11, Reg_q5)) \
136 X(Reg_s24, 24, "s24", 0, 1, 0, 0, 0, 1, 0, 0, \
137 ALIASES3(Reg_s24, Reg_d12, Reg_q6)) \
138 X(Reg_s25, 25, "s25", 0, 1, 0, 0, 0, 1, 0, 0, \
139 ALIASES3(Reg_s25, Reg_d12, Reg_q6)) \
140 X(Reg_s26, 26, "s26", 0, 1, 0, 0, 0, 1, 0, 0, \
141 ALIASES3(Reg_s26, Reg_d13, Reg_q6)) \
142 X(Reg_s27, 27, "s27", 0, 1, 0, 0, 0, 1, 0, 0, \
143 ALIASES3(Reg_s27, Reg_d13, Reg_q6)) \
144 X(Reg_s28, 28, "s28", 0, 1, 0, 0, 0, 1, 0, 0, \
145 ALIASES3(Reg_s28, Reg_d14, Reg_q7)) \
146 X(Reg_s29, 29, "s29", 0, 1, 0, 0, 0, 1, 0, 0, \
147 ALIASES3(Reg_s29, Reg_d14, Reg_q7)) \
148 X(Reg_s30, 30, "s30", 0, 1, 0, 0, 0, 1, 0, 0, \
149 ALIASES3(Reg_s30, Reg_d15, Reg_q7)) \
150 X(Reg_s31, 31, "s31", 0, 1, 0, 0, 0, 1, 0, 0, \
151 ALIASES3(Reg_s31, Reg_d15, Reg_q7))
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]152//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]153// isInt, isFP32,isFP64, isVec128, aliases_init)
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]154
155// D registers 0-7 are scratch, 8-15 are preserved, and 16-31
156// are also scratch (if supported by the D32 feature vs D16).
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]157// D registers are defined in reverse order so that, during register allocation,
158// Subzero will prefer higher D registers. In processors supporting the D32
159// feature this will effectively cause double allocation to bias towards
160// allocating "high" D registers, which do not alias any S registers.
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]161//
162// Regenerate this with the following python script:
163// def print_dregs():
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]164// for i in xrange(31, 15, -1):
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]165// is_scratch = 1 if (i < 8 or i >= 16) else 0
166// is_preserved = 1 if (8 <= i and i < 16) else 0
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]167// print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
168// '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, ' +
169// 'ALIASES(Reg_d{regnum:<2}, Reg_q{regnum_q:<2}) \\').format(
170// regnum=i, regnum_q=i>>1, scratch=is_scratch,
171// preserved=is_preserved)
172// for i in xrange(15, -1, -1):
173// is_scratch = 1 if (i < 8 or i >= 16) else 0
174// is_preserved = 1 if (8 <= i and i < 16) else 0
175// print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
176// '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, ' +
177// 'ALIASES(Reg_s{regnum_s0:<2}, Reg_s{regnum_s1:<2}, ' +
178// 'Reg_d{regnum:<2}, Reg_q{regnum_q:<2})) \\').format(
179// regnum_s0 = (i<<1), regnum_s1 = (i<<1) + 1, regnum=i,
180// regnum_q=i>>1, scratch=is_scratch, preserved=is_preserved)
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]181//
182// print_dregs()
183//
184#define REGARM32_FP64_TABLE \
185 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]186 isInt, isFP32, isFP64, isVec128, aliases_init */ \
187 X(Reg_d31, 31, "d31", 1, 0, 0, 0, 0, 0, 1, 0, \
188 ALIASES2(Reg_d31, Reg_q15)) \
189 X(Reg_d30, 30, "d30", 1, 0, 0, 0, 0, 0, 1, 0, \
190 ALIASES2(Reg_d30, Reg_q15)) \
191 X(Reg_d29, 29, "d29", 1, 0, 0, 0, 0, 0, 1, 0, \
192 ALIASES2(Reg_d29, Reg_q14)) \
193 X(Reg_d28, 28, "d28", 1, 0, 0, 0, 0, 0, 1, 0, \
194 ALIASES2(Reg_d28, Reg_q14)) \
195 X(Reg_d27, 27, "d27", 1, 0, 0, 0, 0, 0, 1, 0, \
196 ALIASES2(Reg_d27, Reg_q13)) \
197 X(Reg_d26, 26, "d26", 1, 0, 0, 0, 0, 0, 1, 0, \
198 ALIASES2(Reg_d26, Reg_q13)) \
199 X(Reg_d25, 25, "d25", 1, 0, 0, 0, 0, 0, 1, 0, \
200 ALIASES2(Reg_d25, Reg_q12)) \
201 X(Reg_d24, 24, "d24", 1, 0, 0, 0, 0, 0, 1, 0, \
202 ALIASES2(Reg_d24, Reg_q12)) \
203 X(Reg_d23, 23, "d23", 1, 0, 0, 0, 0, 0, 1, 0, \
204 ALIASES2(Reg_d23, Reg_q11)) \
205 X(Reg_d22, 22, "d22", 1, 0, 0, 0, 0, 0, 1, 0, \
206 ALIASES2(Reg_d22, Reg_q11)) \
207 X(Reg_d21, 21, "d21", 1, 0, 0, 0, 0, 0, 1, 0, \
208 ALIASES2(Reg_d21, Reg_q10)) \
209 X(Reg_d20, 20, "d20", 1, 0, 0, 0, 0, 0, 1, 0, \
210 ALIASES2(Reg_d20, Reg_q10)) \
211 X(Reg_d19, 19, "d19", 1, 0, 0, 0, 0, 0, 1, 0, \
212 ALIASES2(Reg_d19, Reg_q9)) \
213 X(Reg_d18, 18, "d18", 1, 0, 0, 0, 0, 0, 1, 0, \
214 ALIASES2(Reg_d18, Reg_q9)) \
215 X(Reg_d17, 17, "d17", 1, 0, 0, 0, 0, 0, 1, 0, \
216 ALIASES2(Reg_d17, Reg_q8)) \
217 X(Reg_d16, 16, "d16", 1, 0, 0, 0, 0, 0, 1, 0, \
218 ALIASES2(Reg_d16, Reg_q8)) \
219 X(Reg_d15, 15, "d15", 0, 1, 0, 0, 0, 0, 1, 0, \
220 ALIASES4(Reg_s30, Reg_s31, Reg_d15, Reg_q7)) \
221 X(Reg_d14, 14, "d14", 0, 1, 0, 0, 0, 0, 1, 0, \
222 ALIASES4(Reg_s28, Reg_s29, Reg_d14, Reg_q7)) \
223 X(Reg_d13, 13, "d13", 0, 1, 0, 0, 0, 0, 1, 0, \
224 ALIASES4(Reg_s26, Reg_s27, Reg_d13, Reg_q6)) \
225 X(Reg_d12, 12, "d12", 0, 1, 0, 0, 0, 0, 1, 0, \
226 ALIASES4(Reg_s24, Reg_s25, Reg_d12, Reg_q6)) \
227 X(Reg_d11, 11, "d11", 0, 1, 0, 0, 0, 0, 1, 0, \
228 ALIASES4(Reg_s22, Reg_s23, Reg_d11, Reg_q5)) \
229 X(Reg_d10, 10, "d10", 0, 1, 0, 0, 0, 0, 1, 0, \
230 ALIASES4(Reg_s20, Reg_s21, Reg_d10, Reg_q5)) \
231 X(Reg_d9 , 9 , "d9", 0, 1, 0, 0, 0, 0, 1, 0, \
232 ALIASES4(Reg_s18, Reg_s19, Reg_d9 , Reg_q4)) \
233 X(Reg_d8 , 8 , "d8", 0, 1, 0, 0, 0, 0, 1, 0, \
234 ALIASES4(Reg_s16, Reg_s17, Reg_d8 , Reg_q4)) \
235 X(Reg_d7 , 7 , "d7", 1, 0, 0, 0, 0, 0, 1, 0, \
236 ALIASES4(Reg_s14, Reg_s15, Reg_d7 , Reg_q3)) \
237 X(Reg_d6 , 6 , "d6", 1, 0, 0, 0, 0, 0, 1, 0, \
238 ALIASES4(Reg_s12, Reg_s13, Reg_d6 , Reg_q3)) \
239 X(Reg_d5 , 5 , "d5", 1, 0, 0, 0, 0, 0, 1, 0, \
240 ALIASES4(Reg_s10, Reg_s11, Reg_d5 , Reg_q2)) \
241 X(Reg_d4 , 4 , "d4", 1, 0, 0, 0, 0, 0, 1, 0, \
242 ALIASES4(Reg_s8 , Reg_s9 , Reg_d4 , Reg_q2)) \
243 X(Reg_d3 , 3 , "d3", 1, 0, 0, 0, 0, 0, 1, 0, \
244 ALIASES4(Reg_s6 , Reg_s7 , Reg_d3 , Reg_q1)) \
245 X(Reg_d2 , 2 , "d2", 1, 0, 0, 0, 0, 0, 1, 0, \
246 ALIASES4(Reg_s4 , Reg_s5 , Reg_d2 , Reg_q1)) \
247 X(Reg_d1 , 1 , "d1", 1, 0, 0, 0, 0, 0, 1, 0, \
248 ALIASES4(Reg_s2 , Reg_s3 , Reg_d1 , Reg_q0)) \
249 X(Reg_d0 , 0 , "d0", 1, 0, 0, 0, 0, 0, 1, 0, \
250 ALIASES4(Reg_s0 , Reg_s1 , Reg_d0 , Reg_q0))
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]251//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]252// isInt, isFP32, isFP64, isVec128, aliases_init)
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]253
254// Q registers 0-3 are scratch, 4-7 are preserved, and 8-15
255// are also scratch (if supported by the D32 feature).
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]256// Q registers are defined in reverse order for the same reason as D registers.
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]257//
258// Regenerate this with the following python script:
259// def print_qregs():
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]260// for i in xrange(15, 7, -1):
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]261// is_scratch = 1 if (i < 4 or i >= 8) else 0
262// is_preserved = 1 if (4 <= i and i < 8) else 0
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]263// print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
264// '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, ALIASES(' +
265// 'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' +
266// 'Reg_q{regnum:<2})) \\').format(
267// regnum_d0=(i<<1), regnum_d1=(i<<1)+1, regnum=i,
268// scratch=is_scratch, preserved=is_preserved)
269// for i in xrange(7, -1, -1):
270// is_scratch = 1 if (i < 4 or i >= 8) else 0
271// is_preserved = 1 if (4 <= i and i < 8) else 0
272// print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
273// '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, ALIASES(' +
274// 'Reg_s{regnum_s0:<2}, Reg_s{regnum_s1:<2}, ' +
275// 'Reg_s{regnum_s2:<2}, Reg_s{regnum_s3:<2}, ' +
276// 'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' +
277// 'Reg_q{regnum:<2})) \\').format(
278// regnum_s0=(i<<2), regnum_s1=(i<<2)+1, regnum_s2=(i<<2)+2,
279// regnum_s3=(i<<2)+3, regnum_d0=(i<<1), regnum_d1=(i<<1)+1,
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]280// regnum=i, scratch=is_scratch, preserved=is_preserved)
281//
282// print_qregs()
283//
284#define REGARM32_VEC128_TABLE \
285 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]286 isInt, isFP32, isFP64, isVec128, alias_init */ \
287 X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 1, \
288 ALIASES3(Reg_d30, Reg_d31, Reg_q15)) \
289 X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 1, \
290 ALIASES3(Reg_d28, Reg_d29, Reg_q14)) \
291 X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 1, \
292 ALIASES3(Reg_d26, Reg_d27, Reg_q13)) \
293 X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 1, \
294 ALIASES3(Reg_d24, Reg_d25, Reg_q12)) \
295 X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 1, \
296 ALIASES3(Reg_d22, Reg_d23, Reg_q11)) \
297 X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 1, \
298 ALIASES3(Reg_d20, Reg_d21, Reg_q10)) \
299 X(Reg_q9 , 9 , "q9", 1, 0, 0, 0, 0, 0, 0, 1, \
300 ALIASES3(Reg_d18, Reg_d19, Reg_q9)) \
301 X(Reg_q8 , 8 , "q8", 1, 0, 0, 0, 0, 0, 0, 1, \
302 ALIASES3(Reg_d16, Reg_d17, Reg_q8)) \
303 X(Reg_q7 , 7 , "q7", 0, 1, 0, 0, 0, 0, 0, 1, \
304 ALIASES7(Reg_s28, Reg_s29, Reg_s30, Reg_s31, Reg_d14, Reg_d15, Reg_q7)) \
305 X(Reg_q6 , 6 , "q6", 0, 1, 0, 0, 0, 0, 0, 1, \
306 ALIASES7(Reg_s24, Reg_s25, Reg_s26, Reg_s27, Reg_d12, Reg_d13, Reg_q6)) \
307 X(Reg_q5 , 5 , "q5", 0, 1, 0, 0, 0, 0, 0, 1, \
308 ALIASES7(Reg_s20, Reg_s21, Reg_s22, Reg_s23, Reg_d10, Reg_d11, Reg_q5)) \
309 X(Reg_q4 , 4 , "q4", 0, 1, 0, 0, 0, 0, 0, 1, \
310 ALIASES7(Reg_s16, Reg_s17, Reg_s18, Reg_s19, Reg_d8 , Reg_d9 , Reg_q4)) \
311 X(Reg_q3 , 3 , "q3", 1, 0, 0, 0, 0, 0, 0, 1, \
312 ALIASES7(Reg_s12, Reg_s13, Reg_s14, Reg_s15, Reg_d6 , Reg_d7 , Reg_q3)) \
313 X(Reg_q2 , 2 , "q2", 1, 0, 0, 0, 0, 0, 0, 1, \
314 ALIASES7(Reg_s8 , Reg_s9 , Reg_s10, Reg_s11, Reg_d4 , Reg_d5 , Reg_q2)) \
315 X(Reg_q1 , 1 , "q1", 1, 0, 0, 0, 0, 0, 0, 1, \
316 ALIASES7(Reg_s4 , Reg_s5 , Reg_s6 , Reg_s7 , Reg_d2 , Reg_d3 , Reg_q1)) \
317 X(Reg_q0 , 0 , "q0", 1, 0, 0, 0, 0, 0, 0, 1, \
318 ALIASES7(Reg_s0 , Reg_s1 , Reg_s2 , Reg_s3 , Reg_d0 , Reg_d1 , Reg_q0))
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]319//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]320// isInt, isFP32, isFP64, isVec128, alias_init)
321#undef ALIASES
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]322
323// We also provide a combined table, so that there is a namespace where
324// all of the registers are considered and have distinct numberings.
325// This is in contrast to the above, where the "encode" is based on how
326// the register numbers will be encoded in binaries and values can overlap.
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]327#define REGARM32_TABLE \
328 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]329 isFP32, isFP64, isVec128, alias_init */ \
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]330 REGARM32_GPR_TABLE \
331 REGARM32_FP32_TABLE \
332 REGARM32_FP64_TABLE \
333 REGARM32_VEC128_TABLE
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]334//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]335// isInt, isFP32, isFP64, isVec128, alias_init)
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]336
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]337#define REGARM32_TABLE_BOUNDS \
338 /* val, init */ \
339 X(Reg_GPR_First, = Reg_r0) \
340 X(Reg_GPR_Last, = Reg_pc) \
341 X(Reg_SREG_First, = Reg_s0) \
342 X(Reg_SREG_Last, = Reg_s31) \
343 X(Reg_DREG_First, = Reg_d0) \
344 X(Reg_DREG_Last, = Reg_d31) \
345 X(Reg_QREG_First, = Reg_q0) \
346 X(Reg_QREG_Last, = Reg_q15)
347// define X(val, init)
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]348
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]349// Load/Store instruction width suffixes and FP/Vector element size suffixes
350// the # of offset bits allowed as part of an addressing mode (for sign or
351// zero extending load/stores).
352#define ICETYPEARM32_TABLE \
353 /* tag, element type, int_width, vec_width, addr bits sext, zext */ \
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]354 X(IceType_void, IceType_void, "" , "" , 0 , 0) \
355 X(IceType_i1, IceType_void, "b", "" , 8 , 12) \
356 X(IceType_i8, IceType_void, "b", "" , 8 , 12) \
357 X(IceType_i16, IceType_void, "h", "" , 8 , 8) \
358 X(IceType_i32, IceType_void, "" , "" , 12, 12) \
359 X(IceType_i64, IceType_void, "d", "" , 8 , 8) \
360 X(IceType_f32, IceType_void, "" , ".f32", 10, 10) \
361 X(IceType_f64, IceType_void, "" , ".f64", 10, 10) \
362 X(IceType_v4i1, IceType_i32 , "" , ".i32", 0 , 0) \
363 X(IceType_v8i1, IceType_i16 , "" , ".i16", 0 , 0) \
364 X(IceType_v16i1, IceType_i8 , "" , ".i8" , 0 , 0) \
365 X(IceType_v16i8, IceType_i8 , "" , ".i8" , 0 , 0) \
366 X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0) \
367 X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0) \
368 X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0)
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]369//#define X(tag, elementty, int_width, vec_width, sbits, ubits)
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]370
Jan Voungb3401d22015-05-18 09:38:21 -0700[diff] [blame]371// Shifter types for Data-processing operands as defined in section A5.1.2.
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]372#define ICEINSTARM32SHIFT_TABLE \
373 /* enum value, emit */ \
374 X(LSL, "lsl") \
375 X(LSR, "lsr") \
376 X(ASR, "asr") \
377 X(ROR, "ror") \
378 X(RRX, "rrx")
Jan Voungb3401d22015-05-18 09:38:21 -0700[diff] [blame]379//#define X(tag, emit)
380
Jan Voung3bfd99a2015-05-22 16:35:25 -0700[diff] [blame]381// Attributes for the condition code 4-bit encoding (that is independent
382// of the APSR's NZCV fields). For example, EQ is 0, but corresponds to
383// Z = 1, and NE is 1, but corresponds to Z = 0.
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]384#define ICEINSTARM32COND_TABLE \
385 /* enum value, encoding, opposite, emit */ \
John Porto5300bfe2015-09-08 09:03:22 -0700[diff] [blame^]386 X(EQ, 0 , NE, "eq") /* equal */ \
387 X(NE, 1 , EQ, "ne") /* not equal */ \
388 X(CS, 2 , CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */ \
389 X(CC, 3 , CS, "cc") /* carry clear/unsigned (AKA lo: lower) */ \
390 X(MI, 4 , PL, "mi") /* minus/negative */ \
391 X(PL, 5 , MI, "pl") /* plus/positive or zero */ \
392 X(VS, 6 , VC, "vs") /* overflow (float unordered) */ \
393 X(VC, 7 , VS, "vc") /* no overflow (float not unordered) */ \
394 X(HI, 8 , LS, "hi") /* unsigned higher */ \
395 X(LS, 9 , HI, "ls") /* unsigned lower or same */ \
Jan Voung86ebec12015-08-09 07:58:35 -0700[diff] [blame]396 X(GE, 10, LT, "ge") /* signed greater than or equal */ \
397 X(LT, 11, GE, "lt") /* signed less than */ \
398 X(GT, 12, LE, "gt") /* signed greater than */ \
399 X(LE, 13, GT, "le") /* signed less than or equal */ \
400 X(AL, 14, kNone, "") /* always (unconditional) */ \
401 X(kNone, 15, kNone, "??") /* special condition / none */
Jan Voung3bfd99a2015-05-22 16:35:25 -0700[diff] [blame]402//#define(tag, encode, opp, emit)
403
Jan Voungb36ad9b2015-04-21 17:01:49 -0700[diff] [blame]404#endif // SUBZERO_SRC_ICEINSTARM32_DEF