John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 1 | //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=// |
| 2 | // |
| 3 | // The Subzero Code Generator |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// |
| 10 | /// \file |
Jim Stichnoth | 92a6e5b | 2015-12-02 16:52:44 -0800 | [diff] [blame] | 11 | /// \brief Declares the X8664 Target Lowering Traits. |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 12 | /// |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #ifndef SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H |
| 16 | #define SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H |
| 17 | |
| 18 | #include "IceAssembler.h" |
| 19 | #include "IceConditionCodesX8664.h" |
| 20 | #include "IceDefs.h" |
| 21 | #include "IceInst.h" |
| 22 | #include "IceInstX8664.def" |
| 23 | #include "IceOperand.h" |
| 24 | #include "IceRegistersX8664.h" |
| 25 | #include "IceTargetLowering.h" |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 26 | #include "IceTargetLoweringX8664.def" |
Jim Stichnoth | c59288b | 2015-11-09 11:38:40 -0800 | [diff] [blame] | 27 | #include "IceTargetLoweringX86RegClass.h" |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 28 | |
John Porto | bb0a5fe | 2015-09-04 11:23:41 -0700 | [diff] [blame] | 29 | #include <array> |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 30 | #include <initializer_list> |
John Porto | bb0a5fe | 2015-09-04 11:23:41 -0700 | [diff] [blame] | 31 | |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 32 | namespace Ice { |
| 33 | |
John Porto | 4a56686 | 2016-01-04 09:33:41 -0800 | [diff] [blame] | 34 | namespace X8664 { |
| 35 | using namespace ::Ice::X86; |
| 36 | |
| 37 | template <class TraitsType> class AssemblerX86Base; |
| 38 | template <class TraitsType> struct Insts; |
| 39 | template <class TraitsType> class TargetX86Base; |
| 40 | |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 41 | class TargetX8664; |
| 42 | |
John Porto | 4a56686 | 2016-01-04 09:33:41 -0800 | [diff] [blame] | 43 | struct TargetX8664Traits { |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 44 | //---------------------------------------------------------------------------- |
| 45 | // ______ ______ __ __ |
| 46 | // /\ __ \/\ ___\/\ "-./ \ |
| 47 | // \ \ __ \ \___ \ \ \-./\ \ |
| 48 | // \ \_\ \_\/\_____\ \_\ \ \_\ |
| 49 | // \/_/\/_/\/_____/\/_/ \/_/ |
| 50 | // |
| 51 | //---------------------------------------------------------------------------- |
John Porto | 4a56686 | 2016-01-04 09:33:41 -0800 | [diff] [blame] | 52 | static constexpr ::Ice::Assembler::AssemblerKind AsmKind = |
Nicolas Capens | 464df5b | 2016-09-17 00:19:38 -0400 | [diff] [blame] | 53 | ::Ice::Assembler::Asm_X8664; |
John Porto | 4a56686 | 2016-01-04 09:33:41 -0800 | [diff] [blame] | 54 | |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 55 | static constexpr bool Is64Bit = true; |
| 56 | static constexpr bool HasPopa = false; |
| 57 | static constexpr bool HasPusha = false; |
| 58 | static constexpr bool UsesX87 = false; |
| 59 | static constexpr ::Ice::RegX8664::GPRRegister Last8BitGPR = |
| 60 | ::Ice::RegX8664::GPRRegister::Encoded_Reg_r15d; |
| 61 | |
| 62 | enum ScaleFactor { TIMES_1 = 0, TIMES_2 = 1, TIMES_4 = 2, TIMES_8 = 3 }; |
| 63 | |
| 64 | using GPRRegister = ::Ice::RegX8664::GPRRegister; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 65 | using ByteRegister = ::Ice::RegX8664::ByteRegister; |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 66 | using XmmRegister = ::Ice::RegX8664::XmmRegister; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 67 | |
| 68 | using Cond = ::Ice::CondX8664; |
| 69 | |
| 70 | using RegisterSet = ::Ice::RegX8664; |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 71 | static constexpr RegisterSet::AllRegisters StackPtr = RegX8664::Reg_rsp; |
| 72 | static constexpr RegisterSet::AllRegisters FramePtr = RegX8664::Reg_rbp; |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 73 | static constexpr GPRRegister Encoded_Reg_Accumulator = |
| 74 | RegX8664::Encoded_Reg_eax; |
| 75 | static constexpr GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx; |
Jim Stichnoth | 8ff4b28 | 2016-01-04 15:39:06 -0800 | [diff] [blame] | 76 | static constexpr FixupKind FK_PcRel = llvm::ELF::R_X86_64_PC32; |
John Porto | 27fddcc | 2016-02-02 15:06:09 -0800 | [diff] [blame] | 77 | static constexpr FixupKind FK_Abs = llvm::ELF::R_X86_64_32S; |
Jim Stichnoth | 8ff4b28 | 2016-01-04 15:39:06 -0800 | [diff] [blame] | 78 | static constexpr FixupKind FK_Gotoff = llvm::ELF::R_X86_64_GOTOFF64; |
| 79 | static constexpr FixupKind FK_GotPC = llvm::ELF::R_X86_64_GOTPC32; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 80 | |
| 81 | class Operand { |
| 82 | public: |
| 83 | enum RexBits { |
| 84 | RexNone = 0x00, |
| 85 | RexBase = 0x40, |
| 86 | RexW = RexBase | (1 << 3), |
| 87 | RexR = RexBase | (1 << 2), |
| 88 | RexX = RexBase | (1 << 1), |
| 89 | RexB = RexBase | (1 << 0), |
| 90 | }; |
| 91 | |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 92 | protected: |
| 93 | // Needed by subclass Address. |
| 94 | Operand() = default; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 95 | |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 96 | public: |
| 97 | Operand(const Operand &) = default; |
| 98 | Operand(Operand &&) = default; |
| 99 | Operand &operator=(const Operand &) = default; |
| 100 | Operand &operator=(Operand &&) = default; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 101 | |
| 102 | uint8_t mod() const { return (encoding_at(0) >> 6) & 3; } |
| 103 | |
| 104 | uint8_t rexX() const { return (rex_ & RexX) != RexX ? RexNone : RexX; } |
| 105 | uint8_t rexB() const { return (rex_ & RexB) != RexB ? RexNone : RexB; } |
| 106 | |
| 107 | GPRRegister rm() const { |
| 108 | return static_cast<GPRRegister>((rexB() != 0 ? 0x08 : 0) | |
| 109 | (encoding_at(0) & 7)); |
| 110 | } |
| 111 | |
| 112 | ScaleFactor scale() const { |
| 113 | return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3); |
| 114 | } |
| 115 | |
| 116 | GPRRegister index() const { |
| 117 | return static_cast<GPRRegister>((rexX() != 0 ? 0x08 : 0) | |
| 118 | ((encoding_at(1) >> 3) & 7)); |
| 119 | } |
| 120 | |
| 121 | GPRRegister base() const { |
| 122 | return static_cast<GPRRegister>((rexB() != 0 ? 0x08 : 0) | |
| 123 | (encoding_at(1) & 7)); |
| 124 | } |
| 125 | |
| 126 | int8_t disp8() const { |
| 127 | assert(length_ >= 2); |
| 128 | return static_cast<int8_t>(encoding_[length_ - 1]); |
| 129 | } |
| 130 | |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 131 | AssemblerFixup *fixup() const { return fixup_; } |
| 132 | |
| 133 | protected: |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 134 | void SetModRM(int mod, GPRRegister rm) { |
| 135 | assert((mod & ~3) == 0); |
| 136 | encoding_[0] = (mod << 6) | (rm & 0x07); |
| 137 | rex_ = (rm & 0x08) ? RexB : RexNone; |
| 138 | length_ = 1; |
| 139 | } |
| 140 | |
| 141 | void SetSIB(ScaleFactor scale, GPRRegister index, GPRRegister base) { |
| 142 | assert(length_ == 1); |
| 143 | assert((scale & ~3) == 0); |
| 144 | encoding_[1] = (scale << 6) | ((index & 0x07) << 3) | (base & 0x07); |
| 145 | rex_ = |
| 146 | ((base & 0x08) ? RexB : RexNone) | ((index & 0x08) ? RexX : RexNone); |
| 147 | length_ = 2; |
| 148 | } |
| 149 | |
| 150 | void SetDisp8(int8_t disp) { |
| 151 | assert(length_ == 1 || length_ == 2); |
| 152 | encoding_[length_++] = static_cast<uint8_t>(disp); |
| 153 | } |
| 154 | |
| 155 | void SetDisp32(int32_t disp) { |
| 156 | assert(length_ == 1 || length_ == 2); |
| 157 | intptr_t disp_size = sizeof(disp); |
| 158 | memmove(&encoding_[length_], &disp, disp_size); |
| 159 | length_ += disp_size; |
| 160 | } |
| 161 | |
| 162 | void SetFixup(AssemblerFixup *fixup) { fixup_ = fixup; } |
| 163 | |
| 164 | private: |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 165 | AssemblerFixup *fixup_ = nullptr; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 166 | uint8_t rex_ = 0; |
| 167 | uint8_t encoding_[6]; |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 168 | uint8_t length_ = 0; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 169 | |
| 170 | explicit Operand(GPRRegister reg) : fixup_(nullptr) { SetModRM(3, reg); } |
| 171 | |
| 172 | /// Get the operand encoding byte at the given index. |
| 173 | uint8_t encoding_at(intptr_t index) const { |
| 174 | assert(index >= 0 && index < length_); |
| 175 | return encoding_[index]; |
| 176 | } |
| 177 | |
| 178 | /// Returns whether or not this operand is really the given register in |
| 179 | /// disguise. Used from the assembler to generate better encodings. |
| 180 | bool IsRegister(GPRRegister reg) const { |
| 181 | return ((encoding_[0] & 0xF8) == |
| 182 | 0xC0) // Addressing mode is register only. |
| 183 | && |
| 184 | (rm() == reg); // Register codes match. |
| 185 | } |
| 186 | |
John Porto | 4a56686 | 2016-01-04 09:33:41 -0800 | [diff] [blame] | 187 | friend class AssemblerX86Base<TargetX8664Traits>; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 188 | }; |
| 189 | |
| 190 | class Address : public Operand { |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 191 | Address() = default; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 192 | |
| 193 | public: |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 194 | Address(const Address &) = default; |
| 195 | Address(Address &&) = default; |
| 196 | Address &operator=(const Address &) = default; |
| 197 | Address &operator=(Address &&) = default; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 198 | |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 199 | Address(GPRRegister Base, int32_t Disp, AssemblerFixup *Fixup) { |
| 200 | if (Fixup == nullptr && Disp == 0 && |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 201 | (Base & 7) != RegX8664::Encoded_Reg_rbp) { |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 202 | SetModRM(0, Base); |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 203 | if ((Base & 7) == RegX8664::Encoded_Reg_rsp) |
| 204 | SetSIB(TIMES_1, RegX8664::Encoded_Reg_rsp, Base); |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 205 | } else if (Fixup == nullptr && Utils::IsInt(8, Disp)) { |
| 206 | SetModRM(1, Base); |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 207 | if ((Base & 7) == RegX8664::Encoded_Reg_rsp) |
| 208 | SetSIB(TIMES_1, RegX8664::Encoded_Reg_rsp, Base); |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 209 | SetDisp8(Disp); |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 210 | } else { |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 211 | SetModRM(2, Base); |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 212 | if ((Base & 7) == RegX8664::Encoded_Reg_rsp) |
| 213 | SetSIB(TIMES_1, RegX8664::Encoded_Reg_rsp, Base); |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 214 | SetDisp32(Disp); |
| 215 | if (Fixup) |
| 216 | SetFixup(Fixup); |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 217 | } |
| 218 | } |
| 219 | |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 220 | Address(GPRRegister Index, ScaleFactor Scale, int32_t Disp, |
| 221 | AssemblerFixup *Fixup) { |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 222 | assert(Index != RegX8664::Encoded_Reg_rsp); // Illegal addressing mode. |
| 223 | SetModRM(0, RegX8664::Encoded_Reg_rsp); |
| 224 | SetSIB(Scale, Index, RegX8664::Encoded_Reg_rbp); |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 225 | SetDisp32(Disp); |
| 226 | if (Fixup) |
| 227 | SetFixup(Fixup); |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 228 | } |
| 229 | |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 230 | Address(GPRRegister Base, GPRRegister Index, ScaleFactor Scale, |
| 231 | int32_t Disp, AssemblerFixup *Fixup) { |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 232 | assert(Index != RegX8664::Encoded_Reg_rsp); // Illegal addressing mode. |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 233 | if (Fixup == nullptr && Disp == 0 && |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 234 | (Base & 7) != RegX8664::Encoded_Reg_rbp) { |
| 235 | SetModRM(0, RegX8664::Encoded_Reg_rsp); |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 236 | SetSIB(Scale, Index, Base); |
| 237 | } else if (Fixup == nullptr && Utils::IsInt(8, Disp)) { |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 238 | SetModRM(1, RegX8664::Encoded_Reg_rsp); |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 239 | SetSIB(Scale, Index, Base); |
| 240 | SetDisp8(Disp); |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 241 | } else { |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 242 | SetModRM(2, RegX8664::Encoded_Reg_rsp); |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 243 | SetSIB(Scale, Index, Base); |
| 244 | SetDisp32(Disp); |
| 245 | if (Fixup) |
| 246 | SetFixup(Fixup); |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 247 | } |
| 248 | } |
| 249 | |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 250 | /// Generate a RIP-relative address expression on x86-64. |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 251 | static Address RipRelative(RelocOffsetT Offset, AssemblerFixup *Fixup) { |
| 252 | assert(Fixup != nullptr); |
| 253 | assert(Fixup->kind() == FK_PcRel); |
| 254 | Address NewAddress; |
| 255 | NewAddress.SetModRM(0x0, RegX8664::Encoded_Reg_rbp); |
John Porto | 3c275ce | 2015-12-22 08:14:00 -0800 | [diff] [blame] | 256 | |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 257 | // Use the Offset in the displacement for now. If we decide to process |
| 258 | // fixups later, we'll need to patch up the emitted displacement. |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 259 | NewAddress.SetDisp32(Offset); |
David Sehr | aa0b1a1 | 2015-10-27 16:55:40 -0700 | [diff] [blame] | 260 | if (Fixup) |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 261 | NewAddress.SetFixup(Fixup); |
| 262 | |
| 263 | return NewAddress; |
| 264 | } |
| 265 | |
| 266 | /// Generate an absolute address. |
| 267 | static Address Absolute(RelocOffsetT Addr) { |
| 268 | Address NewAddress; |
| 269 | NewAddress.SetModRM(0x0, RegX8664::Encoded_Reg_rsp); |
| 270 | static constexpr ScaleFactor NoScale = TIMES_1; |
| 271 | NewAddress.SetSIB(NoScale, RegX8664::Encoded_Reg_rsp, |
| 272 | RegX8664::Encoded_Reg_rbp); |
| 273 | NewAddress.SetDisp32(Addr); |
| 274 | return NewAddress; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 275 | } |
| 276 | |
| 277 | static Address ofConstPool(Assembler *Asm, const Constant *Imm) { |
| 278 | // TODO(jpp): ??? |
Jim Stichnoth | 8ff4b28 | 2016-01-04 15:39:06 -0800 | [diff] [blame] | 279 | AssemblerFixup *Fixup = Asm->createFixup(FK_Abs, Imm); |
John Porto | 1d23542 | 2015-08-12 12:37:53 -0700 | [diff] [blame] | 280 | const RelocOffsetT Offset = 4; |
John Porto | d1bd1d3 | 2016-01-26 11:44:01 -0800 | [diff] [blame] | 281 | return Address::RipRelative(Offset, Fixup); |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 282 | } |
| 283 | }; |
| 284 | |
| 285 | //---------------------------------------------------------------------------- |
| 286 | // __ ______ __ __ ______ ______ __ __ __ ______ |
| 287 | // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ |
| 288 | // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ |
| 289 | // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ |
| 290 | // \/_____/\/_____/\/_/ \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/ |
| 291 | // |
| 292 | //---------------------------------------------------------------------------- |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 293 | enum InstructionSet { |
| 294 | Begin, |
| 295 | // SSE2 is the PNaCl baseline instruction set. |
| 296 | SSE2 = Begin, |
| 297 | SSE4_1, |
| 298 | End |
| 299 | }; |
| 300 | |
| 301 | static const char *TargetName; |
John Porto | 1d23542 | 2015-08-12 12:37:53 -0700 | [diff] [blame] | 302 | static constexpr Type WordType = IceType_i64; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 303 | |
Jim Stichnoth | 467ffe5 | 2016-03-29 15:01:06 -0700 | [diff] [blame] | 304 | static const char *getRegName(RegNumT RegNum) { |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 305 | static const char *const RegNames[RegisterSet::Reg_NUM] = { |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 306 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 307 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 308 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 309 | name, |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 310 | REGX8664_TABLE |
| 311 | #undef X |
| 312 | }; |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 313 | RegNum.assertIsValid(); |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 314 | return RegNames[RegNum]; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 315 | } |
| 316 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 317 | static GPRRegister getEncodedGPR(RegNumT RegNum) { |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 318 | static const GPRRegister GPRRegs[RegisterSet::Reg_NUM] = { |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 319 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 320 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 321 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 322 | GPRRegister(isGPR ? encode : GPRRegister::Encoded_Not_GPR), |
| 323 | REGX8664_TABLE |
| 324 | #undef X |
| 325 | }; |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 326 | RegNum.assertIsValid(); |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 327 | assert(GPRRegs[RegNum] != GPRRegister::Encoded_Not_GPR); |
| 328 | return GPRRegs[RegNum]; |
| 329 | } |
| 330 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 331 | static ByteRegister getEncodedByteReg(RegNumT RegNum) { |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 332 | static const ByteRegister ByteRegs[RegisterSet::Reg_NUM] = { |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 333 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 334 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 335 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 336 | ByteRegister(is8 ? encode : ByteRegister::Encoded_Not_ByteReg), |
| 337 | REGX8664_TABLE |
| 338 | #undef X |
| 339 | }; |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 340 | RegNum.assertIsValid(); |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 341 | assert(ByteRegs[RegNum] != ByteRegister::Encoded_Not_ByteReg); |
| 342 | return ByteRegs[RegNum]; |
| 343 | } |
| 344 | |
Stephen White | 17078c7 | 2019-02-27 14:39:14 -0500 | [diff] [blame] | 345 | static bool isXmm(RegNumT RegNum) { |
| 346 | static const bool IsXmm [RegisterSet::Reg_NUM] = { |
| 347 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
| 348 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 349 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
| 350 | isXmm, |
| 351 | REGX8664_TABLE |
| 352 | #undef X |
| 353 | }; |
| 354 | return IsXmm[RegNum]; |
| 355 | } |
| 356 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 357 | static XmmRegister getEncodedXmm(RegNumT RegNum) { |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 358 | static const XmmRegister XmmRegs[RegisterSet::Reg_NUM] = { |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 359 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 360 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 361 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 362 | XmmRegister(isXmm ? encode : XmmRegister::Encoded_Not_Xmm), |
| 363 | REGX8664_TABLE |
| 364 | #undef X |
| 365 | }; |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 366 | RegNum.assertIsValid(); |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 367 | assert(XmmRegs[RegNum] != XmmRegister::Encoded_Not_Xmm); |
| 368 | return XmmRegs[RegNum]; |
| 369 | } |
| 370 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 371 | static uint32_t getEncoding(RegNumT RegNum) { |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 372 | static const uint32_t Encoding[RegisterSet::Reg_NUM] = { |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 373 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 374 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 375 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 376 | encode, |
| 377 | REGX8664_TABLE |
| 378 | #undef X |
| 379 | }; |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 380 | RegNum.assertIsValid(); |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 381 | return Encoding[RegNum]; |
| 382 | } |
| 383 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 384 | static inline RegNumT getBaseReg(RegNumT RegNum) { |
| 385 | static const RegNumT BaseRegs[RegisterSet::Reg_NUM] = { |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 386 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 387 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 388 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 389 | RegisterSet::base, |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 390 | REGX8664_TABLE |
| 391 | #undef X |
| 392 | }; |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 393 | RegNum.assertIsValid(); |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 394 | return BaseRegs[RegNum]; |
| 395 | } |
| 396 | |
John Porto | 008f4ce | 2015-12-24 13:22:18 -0800 | [diff] [blame] | 397 | private: |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 398 | static RegNumT getFirstGprForType(Type Ty) { |
John Porto | 008f4ce | 2015-12-24 13:22:18 -0800 | [diff] [blame] | 399 | switch (Ty) { |
| 400 | default: |
| 401 | llvm_unreachable("Invalid type for GPR."); |
| 402 | case IceType_i1: |
| 403 | case IceType_i8: |
| 404 | return RegisterSet::Reg_al; |
| 405 | case IceType_i16: |
| 406 | return RegisterSet::Reg_ax; |
| 407 | case IceType_i32: |
| 408 | return RegisterSet::Reg_eax; |
| 409 | case IceType_i64: |
| 410 | return RegisterSet::Reg_rax; |
| 411 | } |
| 412 | } |
| 413 | |
| 414 | public: |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 415 | static RegNumT getGprForType(Type Ty, RegNumT RegNum) { |
Reed Kotler | 5fa0a5f | 2016-02-15 20:01:24 -0800 | [diff] [blame] | 416 | assert(RegNum.hasValue()); |
John Porto | 008f4ce | 2015-12-24 13:22:18 -0800 | [diff] [blame] | 417 | |
| 418 | if (!isScalarIntegerType(Ty)) { |
| 419 | return RegNum; |
| 420 | } |
| 421 | |
| 422 | assert(Ty == IceType_i1 || Ty == IceType_i8 || Ty == IceType_i16 || |
| 423 | Ty == IceType_i32 || Ty == IceType_i64); |
| 424 | |
| 425 | if (RegNum == RegisterSet::Reg_ah) { |
| 426 | assert(Ty == IceType_i8); |
| 427 | return RegNum; |
| 428 | } |
| 429 | |
| 430 | assert(RegNum != RegisterSet::Reg_bh); |
| 431 | assert(RegNum != RegisterSet::Reg_ch); |
| 432 | assert(RegNum != RegisterSet::Reg_dh); |
| 433 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 434 | const RegNumT FirstGprForType = getFirstGprForType(Ty); |
John Porto | 008f4ce | 2015-12-24 13:22:18 -0800 | [diff] [blame] | 435 | |
| 436 | switch (RegNum) { |
| 437 | default: |
| 438 | llvm::report_fatal_error("Unknown register."); |
| 439 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 440 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 441 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
John Porto | 008f4ce | 2015-12-24 13:22:18 -0800 | [diff] [blame] | 442 | case RegisterSet::val: { \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 443 | if (!isGPR) \ |
| 444 | return RegisterSet::val; \ |
John Porto | 008f4ce | 2015-12-24 13:22:18 -0800 | [diff] [blame] | 445 | assert((is64) || (is32) || (is16) || (is8) || \ |
Jim Stichnoth | ee1aae8 | 2016-02-02 09:29:21 -0800 | [diff] [blame] | 446 | getBaseReg(RegisterSet::val) == RegisterSet::Reg_rsp); \ |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 447 | constexpr RegisterSet::AllRegisters FirstGprWithRegNumSize = \ |
Jim Stichnoth | ee1aae8 | 2016-02-02 09:29:21 -0800 | [diff] [blame] | 448 | ((is64) || RegisterSet::val == RegisterSet::Reg_rsp) \ |
John Porto | 008f4ce | 2015-12-24 13:22:18 -0800 | [diff] [blame] | 449 | ? RegisterSet::Reg_rax \ |
Jim Stichnoth | ee1aae8 | 2016-02-02 09:29:21 -0800 | [diff] [blame] | 450 | : (((is32) || RegisterSet::val == RegisterSet::Reg_esp) \ |
John Porto | 008f4ce | 2015-12-24 13:22:18 -0800 | [diff] [blame] | 451 | ? RegisterSet::Reg_eax \ |
Jim Stichnoth | ee1aae8 | 2016-02-02 09:29:21 -0800 | [diff] [blame] | 452 | : (((is16) || RegisterSet::val == RegisterSet::Reg_sp) \ |
John Porto | 008f4ce | 2015-12-24 13:22:18 -0800 | [diff] [blame] | 453 | ? RegisterSet::Reg_ax \ |
| 454 | : RegisterSet::Reg_al)); \ |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 455 | const auto NewRegNum = \ |
| 456 | RegNumT::fixme(RegNum - FirstGprWithRegNumSize + FirstGprForType); \ |
John Porto | 008f4ce | 2015-12-24 13:22:18 -0800 | [diff] [blame] | 457 | assert(getBaseReg(RegNum) == getBaseReg(NewRegNum) && \ |
| 458 | "Error involving " #val); \ |
| 459 | return NewRegNum; \ |
| 460 | } |
| 461 | REGX8664_TABLE |
| 462 | #undef X |
| 463 | } |
| 464 | } |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 465 | |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 466 | private: |
| 467 | /// SizeOf is used to obtain the size of an initializer list as a constexpr |
| 468 | /// expression. This is only needed until our C++ library is updated to |
| 469 | /// C++ 14 -- which defines constexpr members to std::initializer_list. |
| 470 | class SizeOf { |
| 471 | SizeOf(const SizeOf &) = delete; |
| 472 | SizeOf &operator=(const SizeOf &) = delete; |
| 473 | |
| 474 | public: |
| 475 | constexpr SizeOf() : Size(0) {} |
| 476 | template <typename... T> |
| 477 | explicit constexpr SizeOf(T...) |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 478 | : Size(length<T...>::value) {} |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 479 | constexpr SizeT size() const { return Size; } |
| 480 | |
| 481 | private: |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 482 | template <typename T, typename... U> struct length { |
| 483 | static constexpr std::size_t value = 1 + length<U...>::value; |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 484 | }; |
| 485 | |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 486 | template <typename T> struct length<T> { |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 487 | static constexpr std::size_t value = 1; |
| 488 | }; |
| 489 | |
| 490 | const std::size_t Size; |
| 491 | }; |
| 492 | |
| 493 | public: |
John Porto | bb0a5fe | 2015-09-04 11:23:41 -0700 | [diff] [blame] | 494 | static void initRegisterSet( |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 495 | const ::Ice::ClFlags &Flags, |
John Porto | e82b560 | 2016-02-24 15:58:55 -0800 | [diff] [blame] | 496 | std::array<SmallBitVector, RCX86_NUM> *TypeToRegisterSet, |
| 497 | std::array<SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases) { |
| 498 | SmallBitVector IntegerRegistersI64(RegisterSet::Reg_NUM); |
| 499 | SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM); |
| 500 | SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM); |
| 501 | SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM); |
| 502 | SmallBitVector FloatRegisters(RegisterSet::Reg_NUM); |
| 503 | SmallBitVector VectorRegisters(RegisterSet::Reg_NUM); |
| 504 | SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM); |
| 505 | SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM); |
| 506 | SmallBitVector Trunc16To8Registers(RegisterSet::Reg_NUM); |
| 507 | SmallBitVector Trunc8RcvrRegisters(RegisterSet::Reg_NUM); |
| 508 | SmallBitVector AhRcvrRegisters(RegisterSet::Reg_NUM); |
| 509 | SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM); |
John Porto | bb0a5fe | 2015-09-04 11:23:41 -0700 | [diff] [blame] | 510 | |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 511 | static constexpr struct { |
| 512 | uint16_t Val; |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 513 | unsigned IsReservedWhenSandboxing : 1; |
Jim Stichnoth | caeaa27 | 2016-01-10 12:53:44 -0800 | [diff] [blame] | 514 | unsigned Is64 : 1; |
| 515 | unsigned Is32 : 1; |
| 516 | unsigned Is16 : 1; |
| 517 | unsigned Is8 : 1; |
| 518 | unsigned IsXmm : 1; |
| 519 | unsigned Is64To8 : 1; |
| 520 | unsigned Is32To8 : 1; |
| 521 | unsigned Is16To8 : 1; |
| 522 | unsigned IsTrunc8Rcvr : 1; |
| 523 | unsigned IsAhRcvr : 1; |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 524 | #define NUM_ALIASES_BITS 2 |
| 525 | SizeT NumAliases : (NUM_ALIASES_BITS + 1); |
| 526 | uint16_t Aliases[1 << NUM_ALIASES_BITS]; |
| 527 | #undef NUM_ALIASES_BITS |
| 528 | } X8664RegTable[RegisterSet::Reg_NUM] = { |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 529 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 530 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 531 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 532 | { \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 533 | RegisterSet::val, sboxres, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
Jim Stichnoth | 29d15fd | 2016-01-19 10:25:37 -0800 | [diff] [blame] | 534 | is16To8, isTrunc8Rcvr, isAhRcvr, (SizeOf aliases).size(), aliases, \ |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 535 | } \ |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 536 | , |
| 537 | REGX8664_TABLE |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 538 | #undef X |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 539 | }; |
| 540 | |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 541 | const bool NeedSandboxing = Flags.getUseSandboxing(); |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 542 | for (SizeT ii = 0; ii < llvm::array_lengthof(X8664RegTable); ++ii) { |
| 543 | const auto &Entry = X8664RegTable[ii]; |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 544 | // Even though the register is disabled for register allocation, it might |
| 545 | // still be used by the Target Lowering (e.g., base pointer), so the |
| 546 | // register alias table still needs to be defined. |
| 547 | (*RegisterAliases)[Entry.Val].resize(RegisterSet::Reg_NUM); |
| 548 | for (int J = 0; J < Entry.NumAliases; ++J) { |
| 549 | SizeT Alias = Entry.Aliases[J]; |
| 550 | assert(!(*RegisterAliases)[Entry.Val][Alias] && "Duplicate alias"); |
| 551 | (*RegisterAliases)[Entry.Val].set(Alias); |
| 552 | } |
| 553 | |
| 554 | (*RegisterAliases)[Entry.Val].set(Entry.Val); |
| 555 | const bool DisabledRegister = |
| 556 | NeedSandboxing && Entry.IsReservedWhenSandboxing; |
| 557 | if (DisabledRegister) { |
| 558 | continue; |
| 559 | } |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 560 | (IntegerRegistersI64)[Entry.Val] = Entry.Is64; |
| 561 | (IntegerRegistersI32)[Entry.Val] = Entry.Is32; |
| 562 | (IntegerRegistersI16)[Entry.Val] = Entry.Is16; |
| 563 | (IntegerRegistersI8)[Entry.Val] = Entry.Is8; |
| 564 | (FloatRegisters)[Entry.Val] = Entry.IsXmm; |
| 565 | (VectorRegisters)[Entry.Val] = Entry.IsXmm; |
| 566 | (Trunc64To8Registers)[Entry.Val] = Entry.Is64To8; |
| 567 | (Trunc32To8Registers)[Entry.Val] = Entry.Is32To8; |
| 568 | (Trunc16To8Registers)[Entry.Val] = Entry.Is16To8; |
| 569 | (Trunc8RcvrRegisters)[Entry.Val] = Entry.IsTrunc8Rcvr; |
| 570 | (AhRcvrRegisters)[Entry.Val] = Entry.IsAhRcvr; |
John Porto | 4a308ce | 2015-12-30 09:55:04 -0800 | [diff] [blame] | 571 | } |
John Porto | bb0a5fe | 2015-09-04 11:23:41 -0700 | [diff] [blame] | 572 | |
Jim Stichnoth | c59288b | 2015-11-09 11:38:40 -0800 | [diff] [blame] | 573 | (*TypeToRegisterSet)[RC_void] = InvalidRegisters; |
| 574 | (*TypeToRegisterSet)[RC_i1] = IntegerRegistersI8; |
| 575 | (*TypeToRegisterSet)[RC_i8] = IntegerRegistersI8; |
| 576 | (*TypeToRegisterSet)[RC_i16] = IntegerRegistersI16; |
| 577 | (*TypeToRegisterSet)[RC_i32] = IntegerRegistersI32; |
| 578 | (*TypeToRegisterSet)[RC_i64] = IntegerRegistersI64; |
| 579 | (*TypeToRegisterSet)[RC_f32] = FloatRegisters; |
| 580 | (*TypeToRegisterSet)[RC_f64] = FloatRegisters; |
| 581 | (*TypeToRegisterSet)[RC_v4i1] = VectorRegisters; |
| 582 | (*TypeToRegisterSet)[RC_v8i1] = VectorRegisters; |
| 583 | (*TypeToRegisterSet)[RC_v16i1] = VectorRegisters; |
| 584 | (*TypeToRegisterSet)[RC_v16i8] = VectorRegisters; |
| 585 | (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters; |
| 586 | (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; |
| 587 | (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; |
| 588 | (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; |
| 589 | (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers; |
| 590 | (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers; |
| 591 | (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters; |
| 592 | (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 593 | } |
| 594 | |
John Porto | e82b560 | 2016-02-24 15:58:55 -0800 | [diff] [blame] | 595 | static SmallBitVector getRegisterSet(const ::Ice::ClFlags &Flags, |
| 596 | TargetLowering::RegSetMask Include, |
| 597 | TargetLowering::RegSetMask Exclude) { |
| 598 | SmallBitVector Registers(RegisterSet::Reg_NUM); |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 599 | |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 600 | const bool NeedSandboxing = Flags.getUseSandboxing(); |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 601 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 602 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 603 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
| 604 | if (!NeedSandboxing || !(sboxres)) { \ |
| 605 | if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave)) \ |
| 606 | Registers[RegisterSet::val] = true; \ |
| 607 | if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave)) \ |
| 608 | Registers[RegisterSet::val] = true; \ |
| 609 | if (stackptr && (Include & ::Ice::TargetLowering::RegSet_StackPointer)) \ |
| 610 | Registers[RegisterSet::val] = true; \ |
| 611 | if (frameptr && (Include & ::Ice::TargetLowering::RegSet_FramePointer)) \ |
| 612 | Registers[RegisterSet::val] = true; \ |
| 613 | if (scratch && (Exclude & ::Ice::TargetLowering::RegSet_CallerSave)) \ |
| 614 | Registers[RegisterSet::val] = false; \ |
| 615 | if (preserved && (Exclude & ::Ice::TargetLowering::RegSet_CalleeSave)) \ |
| 616 | Registers[RegisterSet::val] = false; \ |
| 617 | if (stackptr && (Exclude & ::Ice::TargetLowering::RegSet_StackPointer)) \ |
| 618 | Registers[RegisterSet::val] = false; \ |
| 619 | if (frameptr && (Exclude & ::Ice::TargetLowering::RegSet_FramePointer)) \ |
| 620 | Registers[RegisterSet::val] = false; \ |
| 621 | } |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 622 | |
| 623 | REGX8664_TABLE |
| 624 | |
| 625 | #undef X |
| 626 | |
| 627 | return Registers; |
| 628 | } |
| 629 | |
Karl Schimpf | d469994 | 2016-04-02 09:55:31 -0700 | [diff] [blame] | 630 | static void makeRandomRegisterPermutation( |
| 631 | Cfg *Func, llvm::SmallVectorImpl<RegNumT> &Permutation, |
| 632 | const SmallBitVector &ExcludeRegisters, uint64_t Salt) { |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 633 | // TODO(stichnot): Declaring Permutation this way loses type/size |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 634 | // information. Fix this in conjunction with the caller-side TODO. |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 635 | assert(Permutation.size() >= RegisterSet::Reg_NUM); |
| 636 | // Expected upper bound on the number of registers in a single equivalence |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 637 | // class. For x86-64, this would comprise the 16 XMM registers. This is |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 638 | // for performance, not correctness. |
| 639 | static const unsigned MaxEquivalenceClassSize = 8; |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 640 | using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>; |
Andrew Scull | 8072bae | 2015-09-14 16:01:26 -0700 | [diff] [blame] | 641 | using EquivalenceClassMap = std::map<uint32_t, RegisterList>; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 642 | EquivalenceClassMap EquivalenceClasses; |
| 643 | SizeT NumShuffled = 0, NumPreserved = 0; |
| 644 | |
| 645 | // Build up the equivalence classes of registers by looking at the register |
| 646 | // properties as well as whether the registers should be explicitly excluded |
| 647 | // from shuffling. |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 648 | #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 649 | sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
| 650 | is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 651 | if (ExcludeRegisters[RegisterSet::val]) { \ |
| 652 | /* val stays the same in the resulting permutation. */ \ |
| 653 | Permutation[RegisterSet::val] = RegisterSet::val; \ |
| 654 | ++NumPreserved; \ |
| 655 | } else { \ |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 656 | uint32_t AttrKey = 0; \ |
| 657 | uint32_t Index = 0; \ |
| 658 | /* Combine relevant attributes into an equivalence class key. */ \ |
| 659 | Index |= (scratch << (AttrKey++)); \ |
| 660 | Index |= (preserved << (AttrKey++)); \ |
| 661 | Index |= (is8 << (AttrKey++)); \ |
| 662 | Index |= (is16 << (AttrKey++)); \ |
| 663 | Index |= (is32 << (AttrKey++)); \ |
| 664 | Index |= (is64 << (AttrKey++)); \ |
| 665 | Index |= (isXmm << (AttrKey++)); \ |
Jim Stichnoth | c59288b | 2015-11-09 11:38:40 -0800 | [diff] [blame] | 666 | Index |= (is16To8 << (AttrKey++)); \ |
| 667 | Index |= (is32To8 << (AttrKey++)); \ |
| 668 | Index |= (is64To8 << (AttrKey++)); \ |
| 669 | Index |= (isTrunc8Rcvr << (AttrKey++)); \ |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 670 | /* val is assigned to an equivalence class based on its properties. */ \ |
| 671 | EquivalenceClasses[Index].push_back(RegisterSet::val); \ |
| 672 | } |
| 673 | REGX8664_TABLE |
| 674 | #undef X |
| 675 | |
Qining Lu | aee5fa8 | 2015-08-20 14:59:03 -0700 | [diff] [blame] | 676 | // Create a random number generator for regalloc randomization. |
Karl Schimpf | d469994 | 2016-04-02 09:55:31 -0700 | [diff] [blame] | 677 | RandomNumberGenerator RNG(getFlags().getRandomSeed(), |
Qining Lu | aee5fa8 | 2015-08-20 14:59:03 -0700 | [diff] [blame] | 678 | RPE_RegAllocRandomization, Salt); |
| 679 | RandomNumberGeneratorWrapper RNGW(RNG); |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 680 | |
| 681 | // Shuffle the resulting equivalence classes. |
| 682 | for (auto I : EquivalenceClasses) { |
| 683 | const RegisterList &List = I.second; |
| 684 | RegisterList Shuffled(List); |
Qining Lu | aee5fa8 | 2015-08-20 14:59:03 -0700 | [diff] [blame] | 685 | RandomShuffle(Shuffled.begin(), Shuffled.end(), RNGW); |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 686 | for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) { |
| 687 | Permutation[List[SI]] = Shuffled[SI]; |
| 688 | ++NumShuffled; |
| 689 | } |
| 690 | } |
| 691 | |
| 692 | assert(NumShuffled + NumPreserved == RegisterSet::Reg_NUM); |
| 693 | |
| 694 | if (Func->isVerbose(IceV_Random)) { |
| 695 | OstreamLocker L(Func->getContext()); |
| 696 | Ostream &Str = Func->getContext()->getStrDump(); |
| 697 | Str << "Register equivalence classes:\n"; |
| 698 | for (auto I : EquivalenceClasses) { |
| 699 | Str << "{"; |
| 700 | const RegisterList &List = I.second; |
| 701 | bool First = true; |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 702 | for (RegNumT Register : List) { |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 703 | if (!First) |
| 704 | Str << " "; |
| 705 | First = false; |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 706 | Str << getRegName(Register); |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 707 | } |
| 708 | Str << "}\n"; |
| 709 | } |
| 710 | } |
| 711 | } |
| 712 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 713 | static RegNumT getRaxOrDie() { return RegisterSet::Reg_rax; } |
John Porto | 3c275ce | 2015-12-22 08:14:00 -0800 | [diff] [blame] | 714 | |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 715 | static RegNumT getRdxOrDie() { return RegisterSet::Reg_rdx; } |
John Porto | 3c275ce | 2015-12-22 08:14:00 -0800 | [diff] [blame] | 716 | |
Nicolas Capens | 4e679e5 | 2017-01-12 17:01:06 -0500 | [diff] [blame] | 717 | #if defined(SUBZERO_USE_MICROSOFT_ABI) |
Nicolas Capens | 464df5b | 2016-09-17 00:19:38 -0400 | [diff] [blame] | 718 | // Microsoft x86-64 calling convention: |
| 719 | // |
| 720 | // * The first four arguments of vector/fp type, regardless of their |
| 721 | // position relative to the other arguments in the argument list, are placed |
| 722 | // in registers %xmm0 - %xmm3. |
| 723 | // |
| 724 | // * The first four arguments of integer types, regardless of their position |
| 725 | // relative to the other arguments in the argument list, are placed in |
| 726 | // registers %rcx, %rdx, %r8, and %r9. |
| 727 | |
| 728 | /// The maximum number of arguments to pass in XMM registers |
| 729 | static constexpr uint32_t X86_MAX_XMM_ARGS = 4; |
| 730 | /// The maximum number of arguments to pass in GPR registers |
| 731 | static constexpr uint32_t X86_MAX_GPR_ARGS = 4; |
| 732 | static RegNumT getRegisterForGprArgNum(Type Ty, uint32_t ArgNum) { |
| 733 | if (ArgNum >= X86_MAX_GPR_ARGS) { |
| 734 | return RegNumT(); |
| 735 | } |
| 736 | static const RegisterSet::AllRegisters GprForArgNum[] = { |
| 737 | RegisterSet::Reg_rcx, RegisterSet::Reg_rdx, RegisterSet::Reg_r8, |
| 738 | RegisterSet::Reg_r9, |
| 739 | }; |
| 740 | static_assert(llvm::array_lengthof(GprForArgNum) == X86_MAX_GPR_ARGS, |
| 741 | "Mismatch between MAX_GPR_ARGS and GprForArgNum."); |
| 742 | assert(Ty == IceType_i64 || Ty == IceType_i32); |
| 743 | return getGprForType(Ty, GprForArgNum[ArgNum]); |
| 744 | } |
Nicolas Capens | 4b1bdae | 2017-01-06 18:19:17 -0500 | [diff] [blame] | 745 | #else |
Nicolas Capens | 464df5b | 2016-09-17 00:19:38 -0400 | [diff] [blame] | 746 | // System V x86-64 calling convention: |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 747 | // |
| 748 | // * The first eight arguments of vector/fp type, regardless of their |
| 749 | // position relative to the other arguments in the argument list, are placed |
| 750 | // in registers %xmm0 - %xmm7. |
| 751 | // |
| 752 | // * The first six arguments of integer types, regardless of their position |
| 753 | // relative to the other arguments in the argument list, are placed in |
| 754 | // registers %rdi, %rsi, %rdx, %rcx, %r8, and %r9. |
| 755 | // |
| 756 | // This intends to match the section "Function Calling Sequence" of the |
| 757 | // document "System V Application Binary Interface." |
| 758 | |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 759 | /// The maximum number of arguments to pass in XMM registers |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 760 | static constexpr uint32_t X86_MAX_XMM_ARGS = 8; |
John Porto | e0d9afa | 2015-08-05 10:13:44 -0700 | [diff] [blame] | 761 | /// The maximum number of arguments to pass in GPR registers |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 762 | static constexpr uint32_t X86_MAX_GPR_ARGS = 6; |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 763 | /// Get the register for a given argument slot in the GPRs. |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 764 | static RegNumT getRegisterForGprArgNum(Type Ty, uint32_t ArgNum) { |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 765 | if (ArgNum >= X86_MAX_GPR_ARGS) { |
Reed Kotler | 5fa0a5f | 2016-02-15 20:01:24 -0800 | [diff] [blame] | 766 | return RegNumT(); |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 767 | } |
| 768 | static const RegisterSet::AllRegisters GprForArgNum[] = { |
| 769 | RegisterSet::Reg_rdi, RegisterSet::Reg_rsi, RegisterSet::Reg_rdx, |
| 770 | RegisterSet::Reg_rcx, RegisterSet::Reg_r8, RegisterSet::Reg_r9, |
| 771 | }; |
| 772 | static_assert(llvm::array_lengthof(GprForArgNum) == X86_MAX_GPR_ARGS, |
| 773 | "Mismatch between MAX_GPR_ARGS and GprForArgNum."); |
| 774 | assert(Ty == IceType_i64 || Ty == IceType_i32); |
Jim Stichnoth | 8aa3966 | 2016-02-10 11:20:30 -0800 | [diff] [blame] | 775 | return getGprForType(Ty, GprForArgNum[ArgNum]); |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 776 | } |
Nicolas Capens | 73ae4fd | 2016-10-28 11:24:50 -0400 | [diff] [blame] | 777 | #endif |
Nicolas Capens | 464df5b | 2016-09-17 00:19:38 -0400 | [diff] [blame] | 778 | |
| 779 | /// Whether scalar floating point arguments are passed in XMM registers |
| 780 | static constexpr bool X86_PASS_SCALAR_FP_IN_XMM = true; |
| 781 | /// Get the register for a given argument slot in the XMM registers. |
| 782 | static RegNumT getRegisterForXmmArgNum(uint32_t ArgNum) { |
| 783 | // TODO(sehr): Change to use the CCArg technique used in ARM32. |
| 784 | static_assert(RegisterSet::Reg_xmm0 + 1 == RegisterSet::Reg_xmm1, |
| 785 | "Inconsistency between XMM register numbers and ordinals"); |
| 786 | if (ArgNum >= X86_MAX_XMM_ARGS) { |
| 787 | return RegNumT(); |
| 788 | } |
| 789 | return RegNumT::fixme(RegisterSet::Reg_xmm0 + ArgNum); |
| 790 | } |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 791 | |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 792 | /// The number of bits in a byte |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 793 | static constexpr uint32_t X86_CHAR_BIT = 8; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 794 | /// Stack alignment. This is defined in IceTargetLoweringX8664.cpp because it |
| 795 | /// is used as an argument to std::max(), and the default std::less<T> has an |
| 796 | /// operator(T const&, T const&) which requires this member to have an |
| 797 | /// address. |
| 798 | static const uint32_t X86_STACK_ALIGNMENT_BYTES; |
| 799 | /// Size of the return address on the stack |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 800 | static constexpr uint32_t X86_RET_IP_SIZE_BYTES = 8; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 801 | /// The number of different NOP instructions |
David Sehr | 0c68bef | 2016-01-20 10:00:23 -0800 | [diff] [blame] | 802 | static constexpr uint32_t X86_NUM_NOP_VARIANTS = 5; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 803 | |
Andrew Scull | cfa628b | 2015-08-20 14:23:05 -0700 | [diff] [blame] | 804 | /// \name Limits for unrolling memory intrinsics. |
| 805 | /// @{ |
| 806 | static constexpr uint32_t MEMCPY_UNROLL_LIMIT = 8; |
| 807 | static constexpr uint32_t MEMMOVE_UNROLL_LIMIT = 8; |
Jim Stichnoth | 35e1600 | 2016-08-05 14:11:49 -0700 | [diff] [blame] | 808 | static constexpr uint32_t MEMSET_UNROLL_LIMIT = 8; |
Andrew Scull | cfa628b | 2015-08-20 14:23:05 -0700 | [diff] [blame] | 809 | /// @} |
| 810 | |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 811 | /// Value is in bytes. Return Value adjusted to the next highest multiple of |
| 812 | /// the stack alignment. |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 813 | static uint32_t applyStackAlignment(uint32_t Value) { |
| 814 | return Utils::applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES); |
| 815 | } |
| 816 | |
| 817 | /// Return the type which the elements of the vector have in the X86 |
| 818 | /// representation of the vector. |
| 819 | static Type getInVectorElementType(Type Ty) { |
| 820 | assert(isVectorType(Ty)); |
Jim Stichnoth | 2d6c826 | 2016-02-07 09:50:27 -0800 | [diff] [blame] | 821 | assert(Ty < TableTypeX8664AttributesSize); |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 822 | return TableTypeX8664Attributes[Ty].InVectorElementType; |
| 823 | } |
| 824 | |
| 825 | // Note: The following data structures are defined in |
| 826 | // IceTargetLoweringX8664.cpp. |
| 827 | |
| 828 | /// The following table summarizes the logic for lowering the fcmp |
| 829 | /// instruction. There is one table entry for each of the 16 conditions. |
| 830 | /// |
| 831 | /// The first four columns describe the case when the operands are floating |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 832 | /// point scalar values. A comment in lowerFcmp() describes the lowering |
| 833 | /// template. In the most general case, there is a compare followed by two |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 834 | /// conditional branches, because some fcmp conditions don't map to a single |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 835 | /// x86 conditional branch. However, in many cases it is possible to swap the |
| 836 | /// operands in the comparison and have a single conditional branch. Since |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 837 | /// it's quite tedious to validate the table by hand, good execution tests are |
| 838 | /// helpful. |
| 839 | /// |
| 840 | /// The last two columns describe the case when the operands are vectors of |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 841 | /// floating point values. For most fcmp conditions, there is a clear mapping |
| 842 | /// to a single x86 cmpps instruction variant. Some fcmp conditions require |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 843 | /// special code to handle and these are marked in the table with a |
| 844 | /// Cmpps_Invalid predicate. |
| 845 | /// {@ |
| 846 | static const struct TableFcmpType { |
| 847 | uint32_t Default; |
| 848 | bool SwapScalarOperands; |
| 849 | Cond::BrCond C1, C2; |
| 850 | bool SwapVectorOperands; |
| 851 | Cond::CmppsCond Predicate; |
| 852 | } TableFcmp[]; |
| 853 | static const size_t TableFcmpSize; |
| 854 | /// @} |
| 855 | |
| 856 | /// The following table summarizes the logic for lowering the icmp instruction |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 857 | /// for i32 and narrower types. Each icmp condition has a clear mapping to an |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 858 | /// x86 conditional branch instruction. |
| 859 | /// {@ |
| 860 | static const struct TableIcmp32Type { Cond::BrCond Mapping; } TableIcmp32[]; |
| 861 | static const size_t TableIcmp32Size; |
| 862 | /// @} |
| 863 | |
| 864 | /// The following table summarizes the logic for lowering the icmp instruction |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 865 | /// for the i64 type. For Eq and Ne, two separate 32-bit comparisons and |
| 866 | /// conditional branches are needed. For the other conditions, three separate |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 867 | /// conditional branches are needed. |
| 868 | /// {@ |
| 869 | static const struct TableIcmp64Type { |
| 870 | Cond::BrCond C1, C2, C3; |
| 871 | } TableIcmp64[]; |
| 872 | static const size_t TableIcmp64Size; |
| 873 | /// @} |
| 874 | |
| 875 | static Cond::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) { |
Jim Stichnoth | 2d6c826 | 2016-02-07 09:50:27 -0800 | [diff] [blame] | 876 | assert(Cond < TableIcmp32Size); |
| 877 | return TableIcmp32[Cond].Mapping; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 878 | } |
| 879 | |
| 880 | static const struct TableTypeX8664AttributesType { |
| 881 | Type InVectorElementType; |
| 882 | } TableTypeX8664Attributes[]; |
| 883 | static const size_t TableTypeX8664AttributesSize; |
| 884 | |
| 885 | //---------------------------------------------------------------------------- |
| 886 | // __ __ __ ______ ______ |
| 887 | // /\ \/\ "-.\ \/\ ___\/\__ _\ |
| 888 | // \ \ \ \ \-. \ \___ \/_/\ \/ |
| 889 | // \ \_\ \_\\"\_\/\_____\ \ \_\ |
| 890 | // \/_/\/_/ \/_/\/_____/ \/_/ |
| 891 | // |
| 892 | //---------------------------------------------------------------------------- |
John Porto | 4a56686 | 2016-01-04 09:33:41 -0800 | [diff] [blame] | 893 | using Traits = TargetX8664Traits; |
| 894 | using Insts = ::Ice::X8664::Insts<Traits>; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 895 | |
John Porto | 4a56686 | 2016-01-04 09:33:41 -0800 | [diff] [blame] | 896 | using TargetLowering = ::Ice::X8664::TargetX86Base<Traits>; |
| 897 | using ConcreteTarget = ::Ice::X8664::TargetX8664; |
| 898 | using Assembler = ::Ice::X8664::AssemblerX86Base<Traits>; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 899 | |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 900 | /// X86Operand extends the Operand hierarchy. Its subclasses are X86OperandMem |
| 901 | /// and VariableSplit. |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 902 | class X86Operand : public ::Ice::Operand { |
| 903 | X86Operand() = delete; |
| 904 | X86Operand(const X86Operand &) = delete; |
| 905 | X86Operand &operator=(const X86Operand &) = delete; |
| 906 | |
| 907 | public: |
| 908 | enum OperandKindX8664 { k__Start = ::Ice::Operand::kTarget, kMem, kSplit }; |
| 909 | using ::Ice::Operand::dump; |
| 910 | |
| 911 | void dump(const Cfg *, Ostream &Str) const override; |
| 912 | |
| 913 | protected: |
| 914 | X86Operand(OperandKindX8664 Kind, Type Ty) |
| 915 | : Operand(static_cast<::Ice::Operand::OperandKind>(Kind), Ty) {} |
| 916 | }; |
| 917 | |
| 918 | /// X86OperandMem represents the m64 addressing mode, with optional base and |
| 919 | /// index registers, a constant offset, and a fixed shift value for the index |
| 920 | /// register. |
| 921 | class X86OperandMem : public X86Operand { |
| 922 | X86OperandMem() = delete; |
| 923 | X86OperandMem(const X86OperandMem &) = delete; |
| 924 | X86OperandMem &operator=(const X86OperandMem &) = delete; |
| 925 | |
| 926 | public: |
| 927 | enum SegmentRegisters { DefaultSegment = -1, SegReg_NUM }; |
| 928 | static X86OperandMem * |
| 929 | create(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, |
| 930 | Variable *Index = nullptr, uint16_t Shift = 0, |
Jim Stichnoth | 8ff4b28 | 2016-01-04 15:39:06 -0800 | [diff] [blame] | 931 | SegmentRegisters SegmentRegister = DefaultSegment, |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 932 | bool IsRebased = false) { |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 933 | assert(SegmentRegister == DefaultSegment); |
| 934 | (void)SegmentRegister; |
| 935 | return new (Func->allocate<X86OperandMem>()) |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 936 | X86OperandMem(Func, Ty, Base, Offset, Index, Shift, IsRebased); |
| 937 | } |
| 938 | static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base, |
| 939 | Constant *Offset, bool IsRebased) { |
| 940 | constexpr Variable *NoIndex = nullptr; |
| 941 | constexpr uint16_t NoShift = 0; |
| 942 | return new (Func->allocate<X86OperandMem>()) |
| 943 | X86OperandMem(Func, Ty, Base, Offset, NoIndex, NoShift, IsRebased); |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 944 | } |
| 945 | Variable *getBase() const { return Base; } |
| 946 | Constant *getOffset() const { return Offset; } |
| 947 | Variable *getIndex() const { return Index; } |
| 948 | uint16_t getShift() const { return Shift; } |
| 949 | SegmentRegisters getSegmentRegister() const { return DefaultSegment; } |
| 950 | void emitSegmentOverride(Assembler *) const {} |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 951 | bool getIsRebased() const { return IsRebased; } |
| 952 | Address toAsmAddress(Assembler *Asm, const Ice::TargetLowering *Target, |
| 953 | bool IsLeaAddr = false) const; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 954 | |
| 955 | void emit(const Cfg *Func) const override; |
| 956 | using X86Operand::dump; |
| 957 | void dump(const Cfg *Func, Ostream &Str) const override; |
| 958 | |
| 959 | static bool classof(const Operand *Operand) { |
| 960 | return Operand->getKind() == static_cast<OperandKind>(kMem); |
| 961 | } |
| 962 | |
| 963 | void setRandomized(bool R) { Randomized = R; } |
| 964 | |
| 965 | bool getRandomized() const { return Randomized; } |
| 966 | |
| 967 | private: |
| 968 | X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 969 | Variable *Index, uint16_t Shift, bool IsRebased); |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 970 | |
John Porto | 56958cb | 2016-01-14 09:18:18 -0800 | [diff] [blame] | 971 | Variable *const Base; |
| 972 | Constant *const Offset; |
| 973 | Variable *const Index; |
| 974 | const uint16_t Shift; |
| 975 | const bool IsRebased; |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 976 | /// A flag to show if this memory operand is a randomized one. Randomized |
| 977 | /// memory operands are generated in |
| 978 | /// TargetX86Base::randomizeOrPoolImmediate() |
| 979 | bool Randomized = false; |
| 980 | }; |
| 981 | |
| 982 | /// VariableSplit is a way to treat an f64 memory location as a pair of i32 |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 983 | /// locations (Low and High). This is needed for some cases of the Bitcast |
| 984 | /// instruction. Since it's not possible for integer registers to access the |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 985 | /// XMM registers and vice versa, the lowering forces the f64 to be spilled to |
| 986 | /// the stack and then accesses through the VariableSplit. |
| 987 | // TODO(jpp): remove references to VariableSplit from IceInstX86Base as 64bit |
| 988 | // targets can natively handle these. |
| 989 | class VariableSplit : public X86Operand { |
| 990 | VariableSplit() = delete; |
| 991 | VariableSplit(const VariableSplit &) = delete; |
| 992 | VariableSplit &operator=(const VariableSplit &) = delete; |
| 993 | |
| 994 | public: |
| 995 | enum Portion { Low, High }; |
| 996 | static VariableSplit *create(Cfg *Func, Variable *Var, Portion Part) { |
| 997 | return new (Func->allocate<VariableSplit>()) |
| 998 | VariableSplit(Func, Var, Part); |
| 999 | } |
| 1000 | int32_t getOffset() const { return Part == High ? 4 : 0; } |
| 1001 | |
| 1002 | Address toAsmAddress(const Cfg *Func) const; |
| 1003 | void emit(const Cfg *Func) const override; |
| 1004 | using X86Operand::dump; |
| 1005 | void dump(const Cfg *Func, Ostream &Str) const override; |
| 1006 | |
| 1007 | static bool classof(const Operand *Operand) { |
| 1008 | return Operand->getKind() == static_cast<OperandKind>(kSplit); |
| 1009 | } |
| 1010 | |
| 1011 | private: |
| 1012 | VariableSplit(Cfg *Func, Variable *Var, Portion Part) |
| 1013 | : X86Operand(kSplit, IceType_i32), Var(Var), Part(Part) { |
| 1014 | assert(Var->getType() == IceType_f64); |
| 1015 | Vars = Func->allocateArrayOf<Variable *>(1); |
| 1016 | Vars[0] = Var; |
| 1017 | NumVars = 1; |
| 1018 | } |
| 1019 | |
| 1020 | Variable *Var; |
| 1021 | Portion Part; |
| 1022 | }; |
| 1023 | |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 1024 | // Note: The following data structures are defined in IceInstX8664.cpp. |
| 1025 | |
| 1026 | static const struct InstBrAttributesType { |
| 1027 | Cond::BrCond Opposite; |
| 1028 | const char *DisplayString; |
| 1029 | const char *EmitString; |
| 1030 | } InstBrAttributes[]; |
| 1031 | |
| 1032 | static const struct InstCmppsAttributesType { |
| 1033 | const char *EmitString; |
| 1034 | } InstCmppsAttributes[]; |
| 1035 | |
| 1036 | static const struct TypeAttributesType { |
Nicolas Capens | 7638e27 | 2016-10-06 11:33:55 -0400 | [diff] [blame] | 1037 | const char *CvtString; // i (integer), s (single FP), d (double FP) |
| 1038 | const char *SdSsString; // ss, sd, or <blank> |
| 1039 | const char *PdPsString; // ps, pd, or <blank> |
| 1040 | const char *SpSdString; // ss, sd, ps, pd, or <blank> |
| 1041 | const char *IntegralString; // b, w, d, or <blank> |
| 1042 | const char *UnpackString; // bw, wd, dq, or <blank> |
| 1043 | const char *PackString; // wb, dw, or <blank> |
| 1044 | const char *WidthString; // b, w, l, q, or <blank> |
| 1045 | const char *FldString; // s, l, or <blank> |
John Porto | 453660f | 2015-07-31 14:52:52 -0700 | [diff] [blame] | 1046 | } TypeAttributes[]; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 1047 | }; |
| 1048 | |
John Porto | 4a56686 | 2016-01-04 09:33:41 -0800 | [diff] [blame] | 1049 | using Traits = ::Ice::X8664::TargetX8664Traits; |
John Porto | 2fea26c | 2015-07-28 16:28:07 -0700 | [diff] [blame] | 1050 | } // end of namespace X8664 |
| 1051 | |
| 1052 | } // end of namespace Ice |
| 1053 | |
| 1054 | #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H |