Philip Tricca | 1ea84a5 | 2015-11-19 18:07:06 -0800 | [diff] [blame] | 1 | /***********************************************************************; |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, Intel Corporation |
wcarthur | f6d78ac | 2015-12-31 10:58:40 -0500 | [diff] [blame] | 3 | * |
| 4 | * Copyright 2015, Andreas Fuchs @ Fraunhofer SIT |
| 5 | * |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 6 | * All rights reserved. |
| 7 | * |
Philip Tricca | 1ea84a5 | 2015-11-19 18:07:06 -0800 | [diff] [blame] | 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions are met: |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 10 | * |
Philip Tricca | 1ea84a5 | 2015-11-19 18:07:06 -0800 | [diff] [blame] | 11 | * 1. Redistributions of source code must retain the above copyright notice, |
| 12 | * this list of conditions and the following disclaimer. |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 13 | * |
| 14 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
Philip Tricca | 1ea84a5 | 2015-11-19 18:07:06 -0800 | [diff] [blame] | 15 | * this list of conditions and the following disclaimer in the documentation |
| 16 | * and/or other materials provided with the distribution. |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 17 | * |
Philip Tricca | 1ea84a5 | 2015-11-19 18:07:06 -0800 | [diff] [blame] | 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 28 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 29 | ***********************************************************************/ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 30 | |
| 31 | #ifndef TSS2_COMMON_H |
| 32 | #define TSS2_COMMON_H |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 33 | #define TSS2_API_VERSION_1_2_1_108 |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 34 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 35 | #include <stdint.h> |
| 36 | /* |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 37 | * Type definitions |
| 38 | */ |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 39 | typedef uint8_t UINT8; |
| 40 | typedef uint8_t BYTE; |
| 41 | typedef int8_t INT8; |
| 42 | typedef int BOOL; |
| 43 | typedef uint16_t UINT16; |
| 44 | typedef int16_t INT16; |
| 45 | typedef uint32_t UINT32; |
| 46 | typedef int32_t INT32; |
| 47 | typedef uint64_t UINT64; |
| 48 | typedef int64_t INT64; |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 49 | |
Philip Tricca | 06dd0aa | 2018-03-07 19:30:02 -0800 | [diff] [blame] | 50 | typedef struct { |
| 51 | UINT16 size; |
| 52 | BYTE buffer[1]; |
| 53 | } TPM2B; |
| 54 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 55 | /* |
| 56 | * ABI runtime negotiation definitions |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 57 | */ |
| 58 | typedef struct { |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 59 | uint32_t tssCreator; |
| 60 | uint32_t tssFamily; |
| 61 | uint32_t tssLevel; |
| 62 | uint32_t tssVersion; |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 63 | } TSS2_ABI_VERSION; |
| 64 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 65 | #define TSS2_ABI_VERSION_CURRENT {1, 2, 1, 108} |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 66 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 67 | /* |
| 68 | * Return Codes |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 69 | */ |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 70 | /* The return type for all TSS2 functions */ |
| 71 | typedef uint32_t TSS2_RC; |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 72 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 73 | /* For return values other than SUCCESS, the second most significant |
| 74 | * byte of the return value is a layer code indicating the software |
| 75 | * layer that generated the error. |
| 76 | */ |
| 77 | #define TSS2_RC_LAYER_SHIFT (16) |
| 78 | #define TSS2_RC_LAYER(level) ((TSS2_RC)level << TSS2_RC_LAYER_SHIFT) |
| 79 | #define TSS2_RC_LAYER_MASK TSS2_RC_LAYER(0xff) |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 80 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 81 | /* These layer codes are reserved for software layers defined in the TCG |
| 82 | * specifications. |
| 83 | */ |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 84 | #define TSS2_TPM_RC_LAYER TSS2_RC_LAYER(0) |
| 85 | #define TSS2_FEATURE_RC_LAYER TSS2_RC_LAYER(6) |
| 86 | #define TSS2_ESAPI_RC_LAYER TSS2_RC_LAYER(7) |
| 87 | #define TSS2_SYS_RC_LAYER TSS2_RC_LAYER(8) |
| 88 | #define TSS2_MU_RC_LAYER TSS2_RC_LAYER(9) |
| 89 | #define TSS2_TCTI_RC_LAYER TSS2_RC_LAYER(10) |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 90 | #define TSS2_RESMGR_RC_LAYER TSS2_RC_LAYER(11) |
| 91 | #define TSS2_RESMGR_TPM_RC_LAYER TSS2_RC_LAYER(12) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 92 | #define TSS2_DRIVER_RC_LAYER TSS2_RC_LAYER(13) |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 93 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 94 | /* Base return codes. |
| 95 | * These base codes indicate the error that occurred. They are |
| 96 | * logical-ORed with a layer code to produce the TSS2 return value. |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 97 | */ |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 98 | #define TSS2_BASE_RC_GENERAL_FAILURE 1U /* Catch all for all errors not otherwise specifed */ |
| 99 | #define TSS2_BASE_RC_NOT_IMPLEMENTED 2U /* If called functionality isn't implemented */ |
| 100 | #define TSS2_BASE_RC_BAD_CONTEXT 3U /* A context structure is bad */ |
| 101 | #define TSS2_BASE_RC_ABI_MISMATCH 4U /* Passed in ABI version doesn't match called module's ABI version */ |
| 102 | #define TSS2_BASE_RC_BAD_REFERENCE 5U /* A pointer is NULL that isn't allowed to be NULL. */ |
| 103 | #define TSS2_BASE_RC_INSUFFICIENT_BUFFER 6U /* A buffer isn't large enough */ |
| 104 | #define TSS2_BASE_RC_BAD_SEQUENCE 7U /* Function called in the wrong order */ |
| 105 | #define TSS2_BASE_RC_NO_CONNECTION 8U /* Fails to connect to next lower layer */ |
| 106 | #define TSS2_BASE_RC_TRY_AGAIN 9U /* Operation timed out; function must be called again to be completed */ |
| 107 | #define TSS2_BASE_RC_IO_ERROR 10U /* IO failure */ |
| 108 | #define TSS2_BASE_RC_BAD_VALUE 11U /* A parameter has a bad value */ |
| 109 | #define TSS2_BASE_RC_NOT_PERMITTED 12U /* Operation not permitted. */ |
| 110 | #define TSS2_BASE_RC_INVALID_SESSIONS 13U /* Session structures were sent, but command doesn't use them or doesn't use the specifed number of them */ |
| 111 | #define TSS2_BASE_RC_NO_DECRYPT_PARAM 14U /* If function called that uses decrypt parameter, but command doesn't support crypt parameter. */ |
| 112 | #define TSS2_BASE_RC_NO_ENCRYPT_PARAM 15U /* If function called that uses encrypt parameter, but command doesn't support encrypt parameter. */ |
| 113 | #define TSS2_BASE_RC_BAD_SIZE 16U /* If size of a parameter is incorrect */ |
| 114 | #define TSS2_BASE_RC_MALFORMED_RESPONSE 17U /* Response is malformed */ |
| 115 | #define TSS2_BASE_RC_INSUFFICIENT_CONTEXT 18U /* Context not large enough */ |
| 116 | #define TSS2_BASE_RC_INSUFFICIENT_RESPONSE 19U /* Response is not long enough */ |
| 117 | #define TSS2_BASE_RC_INCOMPATIBLE_TCTI 20U /* Unknown or unusable TCTI version */ |
| 118 | #define TSS2_BASE_RC_NOT_SUPPORTED 21U /* Functionality not supported. */ |
| 119 | #define TSS2_BASE_RC_BAD_TCTI_STRUCTURE 22U /* TCTI context is bad. */ |
| 120 | #define TSS2_BASE_RC_MEMORY 23U /* memory allocation failed */ |
| 121 | #define TSS2_BASE_RC_BAD_TR 24U /* invalid ESYS_TR handle */ |
Juergen Repp | ff821bd | 2017-12-11 15:21:42 +0100 | [diff] [blame] | 122 | #define TSS2_BASE_RC_MULTIPLE_DECRYPT_SESSIONS 25U /* More than one session with TPMA_SESSION_DECRYPT bit set */ |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 123 | #define TSS2_BASE_RC_MULTIPLE_ENCRYPT_SESSIONS 26U /* More than one session with TPMA_SESSION_ENCRYPT bit set */ |
| 124 | #define TSS2_BASE_RC_RSP_AUTH_FAILED 27U /* Response HMAC from TPM did not verify */ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 125 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 126 | /* Base return codes in the range 0xf800 - 0xffff are reserved for |
| 127 | * implementation-specific purposes. |
| 128 | */ |
| 129 | #define TSS2_LAYER_IMPLEMENTATION_SPECIFIC_OFFSET 0xf800 |
wcarthur | 2efe291 | 2015-11-16 11:19:42 -0500 | [diff] [blame] | 130 | #define TSS2_LEVEL_IMPLEMENTATION_SPECIFIC_SHIFT 11 |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 131 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 132 | /* Success is the same for all software layers */ |
| 133 | #define TSS2_RC_SUCCESS ((TSS2_RC) 0) |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 134 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 135 | /* TCTI error codes */ |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 136 | #define TSS2_TCTI_RC_GENERAL_FAILURE ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 137 | TSS2_BASE_RC_GENERAL_FAILURE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 138 | #define TSS2_TCTI_RC_NOT_IMPLEMENTED ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 139 | TSS2_BASE_RC_NOT_IMPLEMENTED)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 140 | #define TSS2_TCTI_RC_BAD_CONTEXT ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 141 | TSS2_BASE_RC_BAD_CONTEXT)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 142 | #define TSS2_TCTI_RC_ABI_MISMATCH ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 143 | TSS2_BASE_RC_ABI_MISMATCH)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 144 | #define TSS2_TCTI_RC_BAD_REFERENCE ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 145 | TSS2_BASE_RC_BAD_REFERENCE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 146 | #define TSS2_TCTI_RC_INSUFFICIENT_BUFFER ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 147 | TSS2_BASE_RC_INSUFFICIENT_BUFFER)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 148 | #define TSS2_TCTI_RC_BAD_SEQUENCE ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 149 | TSS2_BASE_RC_BAD_SEQUENCE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 150 | #define TSS2_TCTI_RC_NO_CONNECTION ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 151 | TSS2_BASE_RC_NO_CONNECTION)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 152 | #define TSS2_TCTI_RC_TRY_AGAIN ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 153 | TSS2_BASE_RC_TRY_AGAIN)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 154 | #define TSS2_TCTI_RC_IO_ERROR ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 155 | TSS2_BASE_RC_IO_ERROR)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 156 | #define TSS2_TCTI_RC_BAD_VALUE ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 157 | TSS2_BASE_RC_BAD_VALUE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 158 | #define TSS2_TCTI_RC_NOT_PERMITTED ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 159 | TSS2_BASE_RC_NOT_PERMITTED)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 160 | #define TSS2_TCTI_RC_MALFORMED_RESPONSE ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 161 | TSS2_BASE_RC_MALFORMED_RESPONSE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 162 | #define TSS2_TCTI_RC_NOT_SUPPORTED ((TSS2_RC)(TSS2_TCTI_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 163 | TSS2_BASE_RC_NOT_SUPPORTED)) |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 164 | /* SAPI error codes */ |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 165 | #define TSS2_SYS_RC_GENERAL_FAILURE ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 166 | TSS2_BASE_RC_GENERAL_FAILURE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 167 | #define TSS2_SYS_RC_ABI_MISMATCH ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 168 | TSS2_BASE_RC_ABI_MISMATCH)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 169 | #define TSS2_SYS_RC_BAD_REFERENCE ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 170 | TSS2_BASE_RC_BAD_REFERENCE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 171 | #define TSS2_SYS_RC_INSUFFICIENT_BUFFER ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 172 | TSS2_BASE_RC_INSUFFICIENT_BUFFER)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 173 | #define TSS2_SYS_RC_BAD_SEQUENCE ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 174 | TSS2_BASE_RC_BAD_SEQUENCE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 175 | #define TSS2_SYS_RC_BAD_VALUE ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 176 | TSS2_BASE_RC_BAD_VALUE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 177 | #define TSS2_SYS_RC_INVALID_SESSIONS ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 178 | TSS2_BASE_RC_INVALID_SESSIONS)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 179 | #define TSS2_SYS_RC_NO_DECRYPT_PARAM ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 180 | TSS2_BASE_RC_NO_DECRYPT_PARAM)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 181 | #define TSS2_SYS_RC_NO_ENCRYPT_PARAM ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 182 | TSS2_BASE_RC_NO_ENCRYPT_PARAM)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 183 | #define TSS2_SYS_RC_BAD_SIZE ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 184 | TSS2_BASE_RC_BAD_SIZE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 185 | #define TSS2_SYS_RC_MALFORMED_RESPONSE ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 186 | TSS2_BASE_RC_MALFORMED_RESPONSE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 187 | #define TSS2_SYS_RC_INSUFFICIENT_CONTEXT ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 188 | TSS2_BASE_RC_INSUFFICIENT_CONTEXT)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 189 | #define TSS2_SYS_RC_INSUFFICIENT_RESPONSE ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 190 | TSS2_BASE_RC_INSUFFICIENT_RESPONSE)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 191 | #define TSS2_SYS_RC_INCOMPATIBLE_TCTI ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 192 | TSS2_BASE_RC_INCOMPATIBLE_TCTI)) |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 193 | #define TSS2_SYS_RC_BAD_TCTI_STRUCTURE ((TSS2_RC)(TSS2_SYS_RC_LAYER | \ |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 194 | TSS2_BASE_RC_BAD_TCTI_STRUCTURE)) |
| 195 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 196 | /* MUAPI error codes */ |
Andreas Fuchs | e66804b | 2017-11-28 16:24:43 +0100 | [diff] [blame] | 197 | #define TSS2_MU_RC_GENERAL_FAILURE ((TSS2_RC)(TSS2_MU_RC_LAYER | \ |
| 198 | TSS2_BASE_RC_GENERAL_FAILURE)) |
| 199 | #define TSS2_MU_RC_BAD_REFERENCE ((TSS2_RC)(TSS2_MU_RC_LAYER | \ |
| 200 | TSS2_BASE_RC_BAD_REFERENCE)) |
| 201 | #define TSS2_MU_RC_BAD_SIZE ((TSS2_RC)(TSS2_MU_RC_LAYER | \ |
| 202 | TSS2_BASE_RC_BAD_SIZE)) |
| 203 | #define TSS2_MU_RC_BAD_VALUE ((TSS2_RC)(TSS2_MU_RC_LAYER | \ |
| 204 | TSS2_BASE_RC_BAD_VALUE)) |
| 205 | #define TSS2_MU_RC_INSUFFICIENT_BUFFER ((TSS2_RC)(TSS2_MU_RC_LAYER | \ |
| 206 | TSS2_BASE_RC_INSUFFICIENT_BUFFER)) |
| 207 | |
Tadeusz Struk | a3e0374 | 2018-02-26 15:27:39 -0800 | [diff] [blame] | 208 | /* ESAPI Error Codes */ |
Juergen Repp | ff821bd | 2017-12-11 15:21:42 +0100 | [diff] [blame] | 209 | #define TSS2_ESYS_RC_GENERAL_FAILURE ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 210 | TSS2_BASE_RC_GENERAL_FAILURE)) |
| 211 | #define TSS2_ESYS_RC_ABI_MISMATCH ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 212 | TSS2_BASE_RC_ABI_MISMATCH)) |
| 213 | #define TSS2_ESYS_RC_BAD_REFERENCE ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 214 | TSS2_BASE_RC_BAD_REFERENCE)) |
| 215 | #define TSS2_ESYS_RC_INSUFFICIENT_BUFFER ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 216 | TSS2_BASE_RC_INSUFFICIENT_BUFFER)) |
| 217 | #define TSS2_ESYS_RC_BAD_SEQUENCE ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 218 | TSS2_BASE_RC_BAD_SEQUENCE)) |
| 219 | #define TSS2_ESYS_RC_INVALID_SESSIONS ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 220 | TSS2_BASE_RC_INVALID_SESSIONS)) |
| 221 | #define TSS2_ESYS_RC_TRY_AGAIN ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 222 | TSS2_BASE_RC_TRY_AGAIN)) |
| 223 | #define TSS2_ESYS_RC_IO_ERROR ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 224 | TSS2_BASE_RC_BAD_IO_ERROR)) |
| 225 | #define TSS2_ESYS_RC_BAD_VALUE ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 226 | TSS2_BASE_RC_BAD_VALUE)) |
| 227 | #define TSS2_ESYS_RC_NO_DECRYPT_PARAM ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 228 | TSS2_BASE_RC_NO_DECRYPT_PARAM)) |
| 229 | #define TSS2_ESYS_RC_NO_ENCRYPT_PARAM ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 230 | TSS2_BASE_RC_NO_ENCRYPT_PARAM)) |
| 231 | #define TSS2_ESYS_RC_BAD_SIZE ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 232 | TSS2_BASE_RC_BAD_SIZE)) |
| 233 | #define TSS2_ESYS_RC_MALFORMED_RESPONSE ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 234 | TSS2_BASE_RC_MALFORMED_RESPONSE)) |
| 235 | #define TSS2_ESYS_RC_INSUFFICIENT_CONTEXT ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 236 | TSS2_BASE_RC_INSUFFICIENT_CONTEXT)) |
| 237 | #define TSS2_ESYS_RC_INSUFFICIENT_RESPONSE ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 238 | TSS2_BASE_RC_INSUFFICIENT_RESPONSE)) |
| 239 | #define TSS2_ESYS_RC_INCOMPATIBLE_TCTI ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 240 | TSS2_BASE_RC_INCOMPATIBLE_TCTI)) |
| 241 | #define TSS2_ESYS_RC_BAD_TCTI_STRUCTURE ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 242 | TSS2_BASE_RC_BAD_TCTI_STRUCTURE)) |
| 243 | #define TSS2_ESYS_RC_MEMORY ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 244 | TSS2_BASE_RC_MEMORY)) |
| 245 | #define TSS2_ESYS_RC_BAD_TR ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 246 | TSS2_BASE_RC_BAD_TR)) |
| 247 | #define TSS2_ESYS_RC_MULTIPLE_DECRYPT_SESSIONS ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 248 | TSS2_BASE_RC_MULTIPLE_DECRYPT_SESSIONS)) |
| 249 | #define TSS2_ESYS_RC_MULTIPLE_ENCRYPT_SESSIONS ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 250 | TSS2_BASE_RC_MULTIPLE_ENCRYPT_SESSIONS)) |
| 251 | #define TSS2_ESYS_RC_AUTH_MISSING ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 252 | TSS2_BASE_RC_AUTH_MISSING)) |
| 253 | #define TSS2_ESYS_RC_NOT_IMPLEMENTED ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 254 | TSS2_BASE_RC_NOT_IMPLEMENTED)) |
| 255 | #define TSS2_ESYS_RC_BAD_CONTEXT ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 256 | TSS2_BASE_RC_BAD_CONTEXT)) |
| 257 | #define TSS2_ESYS_RC_FILE_ERROR ((TSS2_RC)(TSS2_ESAPI_RC_LAYER | \ |
| 258 | STSS2_BASE_RC_FILE_ERROR)) |
Will Arthur | 54e04e4 | 2015-07-15 11:29:25 -0400 | [diff] [blame] | 259 | #endif /* TSS2_COMMON_H */ |