Philip Tricca | 21fa321 | 2018-02-19 06:43:56 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015 - 2018 Intel Corporation |
Philip Tricca | a003d76 | 2017-10-17 13:25:42 -0700 | [diff] [blame] | 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are met: |
| 7 | * |
| 8 | * 1. Redistributions of source code must retain the above copyright notice, |
| 9 | * this list of conditions and the following disclaimer. |
| 10 | * |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| 12 | * this list of conditions and the following disclaimer in the documentation |
| 13 | * and/or other materials provided with the distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 18 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 19 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 20 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 21 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 22 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 23 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 24 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 25 | * THE POSSIBILITY OF SUCH DAMAGE. |
Philip Tricca | 21fa321 | 2018-02-19 06:43:56 -0800 | [diff] [blame] | 26 | */ |
wcarthur | eedecd6 | 2015-11-20 16:59:45 -0500 | [diff] [blame] | 27 | |
Philip Tricca | a003ae6 | 2018-02-19 10:32:46 -0800 | [diff] [blame] | 28 | #include <inttypes.h> |
wcarthur | eedecd6 | 2015-11-20 16:59:45 -0500 | [diff] [blame] | 29 | #include <stdio.h> |
Philip Tricca | a003d76 | 2017-10-17 13:25:42 -0700 | [diff] [blame] | 30 | #include <stdlib.h> |
Philip Tricca | a003ae6 | 2018-02-19 10:32:46 -0800 | [diff] [blame] | 31 | #include <unistd.h> |
wcarthur | eedecd6 | 2015-11-20 16:59:45 -0500 | [diff] [blame] | 32 | |
Kristen Carlson Accardi | 52a83ba | 2018-01-23 14:38:24 -0800 | [diff] [blame] | 33 | #include "tcti/common.h" |
Philip Tricca | dd3b03c | 2017-03-05 11:38:08 -0800 | [diff] [blame] | 34 | #include "sapi/tpm20.h" |
Philip Tricca | 3bc9603 | 2017-10-10 16:26:09 -0700 | [diff] [blame] | 35 | #include "tcti.h" |
Philip Tricca | a003ae6 | 2018-02-19 10:32:46 -0800 | [diff] [blame] | 36 | #define LOGMODULE tcti |
| 37 | #include "log/log.h" |
wcarthur | eedecd6 | 2015-11-20 16:59:45 -0500 | [diff] [blame] | 38 | |
Philip Tricca | 3f1828c | 2017-10-18 18:44:13 -0700 | [diff] [blame] | 39 | TSS2_RC tcti_common_checks ( |
| 40 | TSS2_TCTI_CONTEXT *tcti_context |
wcarthur | eedecd6 | 2015-11-20 16:59:45 -0500 | [diff] [blame] | 41 | ) |
| 42 | { |
Philip Tricca | 3f1828c | 2017-10-18 18:44:13 -0700 | [diff] [blame] | 43 | TSS2_TCTI_CONTEXT_INTEL *tcti_intel; |
Philip Tricca | 24f555c | 2017-10-13 17:51:53 -0700 | [diff] [blame] | 44 | |
Philip Tricca | 3f1828c | 2017-10-18 18:44:13 -0700 | [diff] [blame] | 45 | tcti_intel = tcti_context_intel_cast (tcti_context); |
| 46 | if (tcti_context == NULL) { |
Tadeusz Struk | 32aadee | 2017-06-14 13:23:42 -0700 | [diff] [blame] | 47 | return TSS2_TCTI_RC_BAD_REFERENCE; |
Philip Tricca | dfa41a5 | 2016-07-20 17:43:57 -0700 | [diff] [blame] | 48 | } |
Philip Tricca | 24f555c | 2017-10-13 17:51:53 -0700 | [diff] [blame] | 49 | if (tcti_intel->magic != TCTI_MAGIC || |
Philip Tricca | a003d76 | 2017-10-17 13:25:42 -0700 | [diff] [blame] | 50 | tcti_intel->version != TCTI_VERSION) { |
Tadeusz Struk | 32aadee | 2017-06-14 13:23:42 -0700 | [diff] [blame] | 51 | return TSS2_TCTI_RC_BAD_CONTEXT; |
wcarthur | 1ac1397 | 2015-11-20 18:10:04 -0500 | [diff] [blame] | 52 | } |
Philip Tricca | dfa41a5 | 2016-07-20 17:43:57 -0700 | [diff] [blame] | 53 | |
Tadeusz Struk | 32aadee | 2017-06-14 13:23:42 -0700 | [diff] [blame] | 54 | return TSS2_RC_SUCCESS; |
wcarthur | eedecd6 | 2015-11-20 16:59:45 -0500 | [diff] [blame] | 55 | } |
| 56 | |
Philip Tricca | 3f1828c | 2017-10-18 18:44:13 -0700 | [diff] [blame] | 57 | TSS2_RC tcti_send_checks ( |
| 58 | TSS2_TCTI_CONTEXT *tctiContext, |
Philip Tricca | ddf42b2 | 2018-02-21 15:37:23 -0800 | [diff] [blame] | 59 | const uint8_t *command_buffer |
Philip Tricca | 3f1828c | 2017-10-18 18:44:13 -0700 | [diff] [blame] | 60 | ) |
| 61 | { |
| 62 | TSS2_TCTI_CONTEXT_INTEL *tcti_intel; |
| 63 | TSS2_RC rc; |
| 64 | |
| 65 | tcti_intel = tcti_context_intel_cast (tctiContext);; |
| 66 | rc = tcti_common_checks (tctiContext); |
| 67 | if (rc != TSS2_RC_SUCCESS) { |
| 68 | return rc; |
| 69 | } |
| 70 | if (command_buffer == NULL) { |
| 71 | return TSS2_TCTI_RC_BAD_REFERENCE; |
| 72 | } |
| 73 | if (tcti_intel->previousStage == TCTI_STAGE_SEND_COMMAND) { |
| 74 | return TSS2_TCTI_RC_BAD_SEQUENCE; |
| 75 | } |
| 76 | |
| 77 | return TSS2_RC_SUCCESS; |
| 78 | } |
wcarthur | eedecd6 | 2015-11-20 16:59:45 -0500 | [diff] [blame] | 79 | |
Philip Tricca | a003d76 | 2017-10-17 13:25:42 -0700 | [diff] [blame] | 80 | TSS2_RC tcti_receive_checks ( |
| 81 | TSS2_TCTI_CONTEXT *tctiContext, |
| 82 | size_t *response_size, |
| 83 | unsigned char *response_buffer |
wcarthur | eedecd6 | 2015-11-20 16:59:45 -0500 | [diff] [blame] | 84 | ) |
| 85 | { |
Philip Tricca | 3f1828c | 2017-10-18 18:44:13 -0700 | [diff] [blame] | 86 | TSS2_TCTI_CONTEXT_INTEL *tcti_intel; |
| 87 | TSS2_RC rc; |
Philip Tricca | 24f555c | 2017-10-13 17:51:53 -0700 | [diff] [blame] | 88 | |
Philip Tricca | 3f1828c | 2017-10-18 18:44:13 -0700 | [diff] [blame] | 89 | tcti_intel = tcti_context_intel_cast (tctiContext); |
| 90 | rc = tcti_common_checks (tctiContext); |
| 91 | if (rc != TSS2_RC_SUCCESS) { |
| 92 | return rc; |
| 93 | } |
| 94 | if (response_buffer == NULL || response_size == NULL) { |
Tadeusz Struk | 32aadee | 2017-06-14 13:23:42 -0700 | [diff] [blame] | 95 | return TSS2_TCTI_RC_BAD_REFERENCE; |
Philip Tricca | dfa41a5 | 2016-07-20 17:43:57 -0700 | [diff] [blame] | 96 | } |
Philip Tricca | a003d76 | 2017-10-17 13:25:42 -0700 | [diff] [blame] | 97 | if (tcti_intel->previousStage == TCTI_STAGE_RECEIVE_RESPONSE) { |
Tadeusz Struk | 32aadee | 2017-06-14 13:23:42 -0700 | [diff] [blame] | 98 | return TSS2_TCTI_RC_BAD_SEQUENCE; |
wcarthur | eedecd6 | 2015-11-20 16:59:45 -0500 | [diff] [blame] | 99 | } |
Philip Tricca | dfa41a5 | 2016-07-20 17:43:57 -0700 | [diff] [blame] | 100 | |
Tadeusz Struk | 32aadee | 2017-06-14 13:23:42 -0700 | [diff] [blame] | 101 | return TSS2_RC_SUCCESS; |
Philip Tricca | 4ea417c | 2016-01-24 23:10:03 +0000 | [diff] [blame] | 102 | } |
Philip Tricca | a003ae6 | 2018-02-19 10:32:46 -0800 | [diff] [blame] | 103 | |
| 104 | ssize_t write_all ( |
| 105 | int fd, |
| 106 | const uint8_t *buf, |
| 107 | size_t size) |
| 108 | { |
| 109 | ssize_t written = 0; |
| 110 | size_t written_total = 0; |
| 111 | |
| 112 | do { |
| 113 | LOG_DEBUG("writing %zu bytes starting at 0x%" PRIxPTR " to fd %d", |
| 114 | size - written_total, |
| 115 | (uintptr_t)buf + written_total, |
| 116 | fd); |
| 117 | written = TEMP_RETRY (write (fd, |
| 118 | (const char*)&buf [written_total], |
| 119 | size - written_total)); |
| 120 | if (written >= 0) { |
| 121 | LOG_DEBUG ("wrote %zd bytes to fd %d", written, fd); |
| 122 | written_total += (size_t)written; |
| 123 | } else { |
| 124 | LOG_ERROR ("failed to write to fd %d: %s", fd, strerror (errno)); |
| 125 | return written_total; |
| 126 | } |
| 127 | } while (written_total < size); |
| 128 | |
| 129 | return (ssize_t)written_total; |
| 130 | } |
Philip Tricca | ee41115 | 2018-02-23 19:16:04 -0800 | [diff] [blame^] | 131 | |
| 132 | TSS2_RC tcti_make_sticky_not_implemented ( |
| 133 | TSS2_TCTI_CONTEXT *tctiContext, |
| 134 | TPM2_HANDLE *handle, |
| 135 | uint8_t sticky) |
| 136 | { |
| 137 | return TSS2_TCTI_RC_NOT_IMPLEMENTED; |
| 138 | } |