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gerrit-public.fairphone.software / platform / external / tpm2 / refs/heads/rel/p/fp2/21.10.0-rel / . / tpm_generated.h
blob: a398c603c5fb6b5b5a29a469d47862e12475393f [file] [log] [blame]
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1// Copyright 2015 The Chromium OS Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// THIS CODE IS GENERATED - DO NOT MODIFY!
6
7#ifndef TPM2_TPM_GENERATED_H_
8#define TPM2_TPM_GENERATED_H_
9
10#include <endian.h>
11#include <string.h>
12
13#include "TPM_Types.h"
14#include "Tpm.h"
15
16UINT16 uint8_t_Marshal(uint8_t* source, BYTE** buffer, INT32* size);
17
18TPM_RC uint8_t_Unmarshal(uint8_t* target, BYTE** buffer, INT32* size);
19
20UINT16 int8_t_Marshal(int8_t* source, BYTE** buffer, INT32* size);
21
22TPM_RC int8_t_Unmarshal(int8_t* target, BYTE** buffer, INT32* size);
23
24UINT16 uint16_t_Marshal(uint16_t* source, BYTE** buffer, INT32* size);
25
26TPM_RC uint16_t_Unmarshal(uint16_t* target, BYTE** buffer, INT32* size);
27
28UINT16 int16_t_Marshal(int16_t* source, BYTE** buffer, INT32* size);
29
30TPM_RC int16_t_Unmarshal(int16_t* target, BYTE** buffer, INT32* size);
31
32UINT16 uint32_t_Marshal(uint32_t* source, BYTE** buffer, INT32* size);
33
34TPM_RC uint32_t_Unmarshal(uint32_t* target, BYTE** buffer, INT32* size);
35
36UINT16 int32_t_Marshal(int32_t* source, BYTE** buffer, INT32* size);
37
38TPM_RC int32_t_Unmarshal(int32_t* target, BYTE** buffer, INT32* size);
39
40UINT16 uint64_t_Marshal(uint64_t* source, BYTE** buffer, INT32* size);
41
42TPM_RC uint64_t_Unmarshal(uint64_t* target, BYTE** buffer, INT32* size);
43
44UINT16 int64_t_Marshal(int64_t* source, BYTE** buffer, INT32* size);
45
46TPM_RC int64_t_Unmarshal(int64_t* target, BYTE** buffer, INT32* size);
47
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]48UINT16 BYTE_Marshal(BYTE* source, BYTE** buffer, INT32* size);
49
50TPM_RC BYTE_Unmarshal(BYTE* target, BYTE** buffer, INT32* size);
51
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]52UINT16 INT16_Marshal(INT16* source, BYTE** buffer, INT32* size);
53
54TPM_RC INT16_Unmarshal(INT16* target, BYTE** buffer, INT32* size);
55
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]56UINT16 INT32_Marshal(INT32* source, BYTE** buffer, INT32* size);
57
58TPM_RC INT32_Unmarshal(INT32* target, BYTE** buffer, INT32* size);
59
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]60UINT16 INT64_Marshal(INT64* source, BYTE** buffer, INT32* size);
61
62TPM_RC INT64_Unmarshal(INT64* target, BYTE** buffer, INT32* size);
63
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]64UINT16 INT8_Marshal(INT8* source, BYTE** buffer, INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]65
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]66TPM_RC INT8_Unmarshal(INT8* target, BYTE** buffer, INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]67
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]68UINT16 TPM2B_ATTEST_Marshal(TPM2B_ATTEST* source, BYTE** buffer, INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]69
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]70TPM_RC TPM2B_ATTEST_Unmarshal(TPM2B_ATTEST* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]71
72UINT16 TPM2B_DIGEST_Marshal(TPM2B_DIGEST* source, BYTE** buffer, INT32* size);
73
74TPM_RC TPM2B_DIGEST_Unmarshal(TPM2B_DIGEST* target, BYTE** buffer, INT32* size);
75
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]76UINT16 TPM2B_AUTH_Marshal(TPM2B_AUTH* source, BYTE** buffer, INT32* size);
77
78TPM_RC TPM2B_AUTH_Unmarshal(TPM2B_AUTH* target, BYTE** buffer, INT32* size);
79
80UINT16 TPM2B_CONTEXT_DATA_Marshal(TPM2B_CONTEXT_DATA* source,
81 BYTE** buffer,
82 INT32* size);
83
84TPM_RC TPM2B_CONTEXT_DATA_Unmarshal(TPM2B_CONTEXT_DATA* target,
85 BYTE** buffer,
86 INT32* size);
87
88UINT16 TPM2B_CONTEXT_SENSITIVE_Marshal(TPM2B_CONTEXT_SENSITIVE* source,
89 BYTE** buffer,
90 INT32* size);
91
92TPM_RC TPM2B_CONTEXT_SENSITIVE_Unmarshal(TPM2B_CONTEXT_SENSITIVE* target,
93 BYTE** buffer,
94 INT32* size);
95
96UINT16 TPM2B_CREATION_DATA_Marshal(TPM2B_CREATION_DATA* source,
97 BYTE** buffer,
98 INT32* size);
99
100TPM_RC TPM2B_CREATION_DATA_Unmarshal(TPM2B_CREATION_DATA* target,
101 BYTE** buffer,
102 INT32* size);
103
104UINT16 TPM2B_DATA_Marshal(TPM2B_DATA* source, BYTE** buffer, INT32* size);
105
106TPM_RC TPM2B_DATA_Unmarshal(TPM2B_DATA* target, BYTE** buffer, INT32* size);
107
108UINT16 TPM2B_DIGEST_VALUES_Marshal(TPM2B_DIGEST_VALUES* source,
109 BYTE** buffer,
110 INT32* size);
111
112TPM_RC TPM2B_DIGEST_VALUES_Unmarshal(TPM2B_DIGEST_VALUES* target,
113 BYTE** buffer,
114 INT32* size);
115
116UINT16 TPM2B_ECC_PARAMETER_Marshal(TPM2B_ECC_PARAMETER* source,
117 BYTE** buffer,
118 INT32* size);
119
120TPM_RC TPM2B_ECC_PARAMETER_Unmarshal(TPM2B_ECC_PARAMETER* target,
121 BYTE** buffer,
122 INT32* size);
123
124UINT16 TPM2B_ECC_POINT_Marshal(TPM2B_ECC_POINT* source,
125 BYTE** buffer,
126 INT32* size);
127
128TPM_RC TPM2B_ECC_POINT_Unmarshal(TPM2B_ECC_POINT* target,
129 BYTE** buffer,
130 INT32* size);
131
132UINT16 TPM2B_ENCRYPTED_SECRET_Marshal(TPM2B_ENCRYPTED_SECRET* source,
133 BYTE** buffer,
134 INT32* size);
135
136TPM_RC TPM2B_ENCRYPTED_SECRET_Unmarshal(TPM2B_ENCRYPTED_SECRET* target,
137 BYTE** buffer,
138 INT32* size);
139
140UINT16 TPM2B_EVENT_Marshal(TPM2B_EVENT* source, BYTE** buffer, INT32* size);
141
142TPM_RC TPM2B_EVENT_Unmarshal(TPM2B_EVENT* target, BYTE** buffer, INT32* size);
143
144UINT16 TPM2B_ID_OBJECT_Marshal(TPM2B_ID_OBJECT* source,
145 BYTE** buffer,
146 INT32* size);
147
148TPM_RC TPM2B_ID_OBJECT_Unmarshal(TPM2B_ID_OBJECT* target,
149 BYTE** buffer,
150 INT32* size);
151
152UINT16 TPM2B_IV_Marshal(TPM2B_IV* source, BYTE** buffer, INT32* size);
153
154TPM_RC TPM2B_IV_Unmarshal(TPM2B_IV* target, BYTE** buffer, INT32* size);
155
156UINT16 TPM2B_MAX_BUFFER_Marshal(TPM2B_MAX_BUFFER* source,
157 BYTE** buffer,
158 INT32* size);
159
160TPM_RC TPM2B_MAX_BUFFER_Unmarshal(TPM2B_MAX_BUFFER* target,
161 BYTE** buffer,
162 INT32* size);
163
164UINT16 TPM2B_MAX_NV_BUFFER_Marshal(TPM2B_MAX_NV_BUFFER* source,
165 BYTE** buffer,
166 INT32* size);
167
168TPM_RC TPM2B_MAX_NV_BUFFER_Unmarshal(TPM2B_MAX_NV_BUFFER* target,
169 BYTE** buffer,
170 INT32* size);
171
172UINT16 TPM2B_NAME_Marshal(TPM2B_NAME* source, BYTE** buffer, INT32* size);
173
174TPM_RC TPM2B_NAME_Unmarshal(TPM2B_NAME* target, BYTE** buffer, INT32* size);
175
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]176UINT16 TPM2B_NONCE_Marshal(TPM2B_NONCE* source, BYTE** buffer, INT32* size);
177
178TPM_RC TPM2B_NONCE_Unmarshal(TPM2B_NONCE* target, BYTE** buffer, INT32* size);
179
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]180UINT16 TPM2B_NV_PUBLIC_Marshal(TPM2B_NV_PUBLIC* source,
181 BYTE** buffer,
182 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]183
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]184TPM_RC TPM2B_NV_PUBLIC_Unmarshal(TPM2B_NV_PUBLIC* target,
185 BYTE** buffer,
186 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]187
188UINT16 TPM2B_OPERAND_Marshal(TPM2B_OPERAND* source, BYTE** buffer, INT32* size);
189
190TPM_RC TPM2B_OPERAND_Unmarshal(TPM2B_OPERAND* target,
191 BYTE** buffer,
192 INT32* size);
193
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]194UINT16 TPM2B_PRIVATE_Marshal(TPM2B_PRIVATE* source, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]195
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]196TPM_RC TPM2B_PRIVATE_Unmarshal(TPM2B_PRIVATE* target,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]197 BYTE** buffer,
198 INT32* size);
199
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]200UINT16 TPM2B_PRIVATE_KEY_RSA_Marshal(TPM2B_PRIVATE_KEY_RSA* source,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]201 BYTE** buffer,
202 INT32* size);
203
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]204TPM_RC TPM2B_PRIVATE_KEY_RSA_Unmarshal(TPM2B_PRIVATE_KEY_RSA* target,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]205 BYTE** buffer,
206 INT32* size);
207
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]208UINT16 TPM2B_PRIVATE_VENDOR_SPECIFIC_Marshal(
209 TPM2B_PRIVATE_VENDOR_SPECIFIC* source,
210 BYTE** buffer,
211 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]212
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]213TPM_RC TPM2B_PRIVATE_VENDOR_SPECIFIC_Unmarshal(
214 TPM2B_PRIVATE_VENDOR_SPECIFIC* target,
215 BYTE** buffer,
216 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]217
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]218UINT16 TPM2B_PUBLIC_Marshal(TPM2B_PUBLIC* source, BYTE** buffer, INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]219
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]220TPM_RC TPM2B_PUBLIC_Unmarshal(TPM2B_PUBLIC* target, BYTE** buffer, INT32* size);
221
222UINT16 TPM2B_PUBLIC_KEY_RSA_Marshal(TPM2B_PUBLIC_KEY_RSA* source,
223 BYTE** buffer,
224 INT32* size);
225
226TPM_RC TPM2B_PUBLIC_KEY_RSA_Unmarshal(TPM2B_PUBLIC_KEY_RSA* target,
227 BYTE** buffer,
228 INT32* size);
229
230UINT16 TPM2B_SENSITIVE_Marshal(TPM2B_SENSITIVE* source,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]231 BYTE** buffer,
232 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]233
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]234TPM_RC TPM2B_SENSITIVE_Unmarshal(TPM2B_SENSITIVE* target,
235 BYTE** buffer,
236 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]237
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]238UINT16 TPM2B_SENSITIVE_CREATE_Marshal(TPM2B_SENSITIVE_CREATE* source,
239 BYTE** buffer,
240 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]241
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]242TPM_RC TPM2B_SENSITIVE_CREATE_Unmarshal(TPM2B_SENSITIVE_CREATE* target,
243 BYTE** buffer,
244 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]245
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]246UINT16 TPM2B_SENSITIVE_DATA_Marshal(TPM2B_SENSITIVE_DATA* source,
247 BYTE** buffer,
248 INT32* size);
249
250TPM_RC TPM2B_SENSITIVE_DATA_Unmarshal(TPM2B_SENSITIVE_DATA* target,
251 BYTE** buffer,
252 INT32* size);
253
254UINT16 TPM2B_SYM_KEY_Marshal(TPM2B_SYM_KEY* source, BYTE** buffer, INT32* size);
255
256TPM_RC TPM2B_SYM_KEY_Unmarshal(TPM2B_SYM_KEY* target,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]257 BYTE** buffer,
258 INT32* size);
259
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]260UINT16 TPM2B_TIMEOUT_Marshal(TPM2B_TIMEOUT* source, BYTE** buffer, INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]261
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]262TPM_RC TPM2B_TIMEOUT_Unmarshal(TPM2B_TIMEOUT* target,
263 BYTE** buffer,
264 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]265
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]266UINT16 UINT32_Marshal(UINT32* source, BYTE** buffer, INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]267
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]268TPM_RC UINT32_Unmarshal(UINT32* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]269
270UINT16 TPMA_ALGORITHM_Marshal(TPMA_ALGORITHM* source,
271 BYTE** buffer,
272 INT32* size);
273
274TPM_RC TPMA_ALGORITHM_Unmarshal(TPMA_ALGORITHM* target,
275 BYTE** buffer,
276 INT32* size);
277
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]278UINT16 TPM_CC_Marshal(TPM_CC* source, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]279
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]280TPM_RC TPM_CC_Unmarshal(TPM_CC* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]281
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]282UINT16 TPMA_CC_Marshal(TPMA_CC* source, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]283
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]284TPM_RC TPMA_CC_Unmarshal(TPMA_CC* target, BYTE** buffer, INT32* size);
285
286UINT16 UINT8_Marshal(UINT8* source, BYTE** buffer, INT32* size);
287
288TPM_RC UINT8_Unmarshal(UINT8* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]289
290UINT16 TPMA_LOCALITY_Marshal(TPMA_LOCALITY* source, BYTE** buffer, INT32* size);
291
292TPM_RC TPMA_LOCALITY_Unmarshal(TPMA_LOCALITY* target,
293 BYTE** buffer,
294 INT32* size);
295
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]296UINT16 TPMA_MEMORY_Marshal(TPMA_MEMORY* source, BYTE** buffer, INT32* size);
297
298TPM_RC TPMA_MEMORY_Unmarshal(TPMA_MEMORY* target, BYTE** buffer, INT32* size);
299
300UINT16 TPMA_NV_Marshal(TPMA_NV* source, BYTE** buffer, INT32* size);
301
302TPM_RC TPMA_NV_Unmarshal(TPMA_NV* target, BYTE** buffer, INT32* size);
303
304UINT16 TPMA_OBJECT_Marshal(TPMA_OBJECT* source, BYTE** buffer, INT32* size);
305
306TPM_RC TPMA_OBJECT_Unmarshal(TPMA_OBJECT* target, BYTE** buffer, INT32* size);
307
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]308UINT16 TPMA_PERMANENT_Marshal(TPMA_PERMANENT* source,
309 BYTE** buffer,
310 INT32* size);
311
312TPM_RC TPMA_PERMANENT_Unmarshal(TPMA_PERMANENT* target,
313 BYTE** buffer,
314 INT32* size);
315
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]316UINT16 TPMA_SESSION_Marshal(TPMA_SESSION* source, BYTE** buffer, INT32* size);
317
318TPM_RC TPMA_SESSION_Unmarshal(TPMA_SESSION* target, BYTE** buffer, INT32* size);
319
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]320UINT16 TPMA_STARTUP_CLEAR_Marshal(TPMA_STARTUP_CLEAR* source,
321 BYTE** buffer,
322 INT32* size);
323
324TPM_RC TPMA_STARTUP_CLEAR_Unmarshal(TPMA_STARTUP_CLEAR* target,
325 BYTE** buffer,
326 INT32* size);
327
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]328UINT16 UINT16_Marshal(UINT16* source, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]329
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]330TPM_RC UINT16_Unmarshal(UINT16* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]331
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]332UINT16 TPM_KEY_BITS_Marshal(TPM_KEY_BITS* source, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]333
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]334TPM_RC TPM_KEY_BITS_Unmarshal(TPM_KEY_BITS* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]335
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]336UINT16 TPMI_AES_KEY_BITS_Marshal(TPMI_AES_KEY_BITS* source,
337 BYTE** buffer,
338 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]339
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]340TPM_RC TPMI_AES_KEY_BITS_Unmarshal(TPMI_AES_KEY_BITS* target,
341 BYTE** buffer,
342 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]343
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]344UINT16 TPM_ALG_ID_Marshal(TPM_ALG_ID* source, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]345
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]346TPM_RC TPM_ALG_ID_Unmarshal(TPM_ALG_ID* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]347
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]348UINT16 TPMI_ALG_ASYM_Marshal(TPMI_ALG_ASYM* source, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]349
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]350TPM_RC TPMI_ALG_ASYM_Unmarshal(TPMI_ALG_ASYM* target,
351 BYTE** buffer,
352 INT32* size,
353 BOOL allow_conditioanl_value);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]354
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]355UINT16 TPMI_ALG_ASYM_SCHEME_Marshal(TPMI_ALG_ASYM_SCHEME* source,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]356 BYTE** buffer,
357 INT32* size);
358
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]359TPM_RC TPMI_ALG_ASYM_SCHEME_Unmarshal(TPMI_ALG_ASYM_SCHEME* target,
360 BYTE** buffer,
361 INT32* size,
362 BOOL allow_conditioanl_value);
363
364UINT16 TPMI_ALG_ECC_SCHEME_Marshal(TPMI_ALG_ECC_SCHEME* source,
365 BYTE** buffer,
366 INT32* size);
367
368TPM_RC TPMI_ALG_ECC_SCHEME_Unmarshal(TPMI_ALG_ECC_SCHEME* target,
369 BYTE** buffer,
370 INT32* size,
371 BOOL allow_conditioanl_value);
372
373UINT16 TPMI_ALG_HASH_Marshal(TPMI_ALG_HASH* source, BYTE** buffer, INT32* size);
374
375TPM_RC TPMI_ALG_HASH_Unmarshal(TPMI_ALG_HASH* target,
376 BYTE** buffer,
377 INT32* size,
378 BOOL allow_conditioanl_value);
379
380UINT16 TPMI_ALG_KDF_Marshal(TPMI_ALG_KDF* source, BYTE** buffer, INT32* size);
381
382TPM_RC TPMI_ALG_KDF_Unmarshal(TPMI_ALG_KDF* target,
383 BYTE** buffer,
384 INT32* size,
385 BOOL allow_conditioanl_value);
386
387UINT16 TPMI_ALG_KEYEDHASH_SCHEME_Marshal(TPMI_ALG_KEYEDHASH_SCHEME* source,
388 BYTE** buffer,
389 INT32* size);
390
391TPM_RC TPMI_ALG_KEYEDHASH_SCHEME_Unmarshal(TPMI_ALG_KEYEDHASH_SCHEME* target,
392 BYTE** buffer,
393 INT32* size,
394 BOOL allow_conditioanl_value);
395
396UINT16 TPMI_ALG_PUBLIC_Marshal(TPMI_ALG_PUBLIC* source,
397 BYTE** buffer,
398 INT32* size);
399
400TPM_RC TPMI_ALG_PUBLIC_Unmarshal(TPMI_ALG_PUBLIC* target,
401 BYTE** buffer,
402 INT32* size);
403
404UINT16 TPMI_ALG_RSA_DECRYPT_Marshal(TPMI_ALG_RSA_DECRYPT* source,
405 BYTE** buffer,
406 INT32* size);
407
408TPM_RC TPMI_ALG_RSA_DECRYPT_Unmarshal(TPMI_ALG_RSA_DECRYPT* target,
409 BYTE** buffer,
410 INT32* size,
411 BOOL allow_conditioanl_value);
412
413UINT16 TPMI_ALG_RSA_SCHEME_Marshal(TPMI_ALG_RSA_SCHEME* source,
414 BYTE** buffer,
415 INT32* size);
416
417TPM_RC TPMI_ALG_RSA_SCHEME_Unmarshal(TPMI_ALG_RSA_SCHEME* target,
418 BYTE** buffer,
419 INT32* size,
420 BOOL allow_conditioanl_value);
421
422UINT16 TPMI_ALG_SIG_SCHEME_Marshal(TPMI_ALG_SIG_SCHEME* source,
423 BYTE** buffer,
424 INT32* size);
425
426TPM_RC TPMI_ALG_SIG_SCHEME_Unmarshal(TPMI_ALG_SIG_SCHEME* target,
427 BYTE** buffer,
428 INT32* size,
429 BOOL allow_conditioanl_value);
430
431UINT16 TPMI_ALG_SYM_Marshal(TPMI_ALG_SYM* source, BYTE** buffer, INT32* size);
432
433TPM_RC TPMI_ALG_SYM_Unmarshal(TPMI_ALG_SYM* target,
434 BYTE** buffer,
435 INT32* size,
436 BOOL allow_conditioanl_value);
437
438UINT16 TPMI_ALG_SYM_MODE_Marshal(TPMI_ALG_SYM_MODE* source,
439 BYTE** buffer,
440 INT32* size);
441
442TPM_RC TPMI_ALG_SYM_MODE_Unmarshal(TPMI_ALG_SYM_MODE* target,
443 BYTE** buffer,
444 INT32* size,
445 BOOL allow_conditioanl_value);
446
447UINT16 TPMI_ALG_SYM_OBJECT_Marshal(TPMI_ALG_SYM_OBJECT* source,
448 BYTE** buffer,
449 INT32* size);
450
451TPM_RC TPMI_ALG_SYM_OBJECT_Unmarshal(TPMI_ALG_SYM_OBJECT* target,
452 BYTE** buffer,
453 INT32* size,
454 BOOL allow_conditioanl_value);
455
Vadim Bendebury0232bac2015-09-17 17:26:29 -0700[diff] [blame]456UINT16 TPMI_CAMELLIA_KEY_BITS_Marshal(TPMI_CAMELLIA_KEY_BITS* source,
457 BYTE** buffer,
458 INT32* size);
459
460TPM_RC TPMI_CAMELLIA_KEY_BITS_Unmarshal(TPMI_CAMELLIA_KEY_BITS* target,
461 BYTE** buffer,
462 INT32* size);
463
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]464UINT16 TPM_HANDLE_Marshal(TPM_HANDLE* source, BYTE** buffer, INT32* size);
465
466TPM_RC TPM_HANDLE_Unmarshal(TPM_HANDLE* target, BYTE** buffer, INT32* size);
467
468UINT16 TPMI_DH_CONTEXT_Marshal(TPMI_DH_CONTEXT* source,
469 BYTE** buffer,
470 INT32* size);
471
472TPM_RC TPMI_DH_CONTEXT_Unmarshal(TPMI_DH_CONTEXT* target,
473 BYTE** buffer,
474 INT32* size);
475
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]476UINT16 TPMI_DH_ENTITY_Marshal(TPMI_DH_ENTITY* source,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]477 BYTE** buffer,
478 INT32* size);
479
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]480TPM_RC TPMI_DH_ENTITY_Unmarshal(TPMI_DH_ENTITY* target,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]481 BYTE** buffer,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]482 INT32* size,
483 BOOL allow_conditioanl_value);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]484
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]485UINT16 TPMI_DH_OBJECT_Marshal(TPMI_DH_OBJECT* source,
486 BYTE** buffer,
487 INT32* size);
488
489TPM_RC TPMI_DH_OBJECT_Unmarshal(TPMI_DH_OBJECT* target,
490 BYTE** buffer,
491 INT32* size,
492 BOOL allow_conditioanl_value);
493
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]494UINT16 TPMI_DH_PCR_Marshal(TPMI_DH_PCR* source, BYTE** buffer, INT32* size);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]495
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]496TPM_RC TPMI_DH_PCR_Unmarshal(TPMI_DH_PCR* target,
497 BYTE** buffer,
498 INT32* size,
499 BOOL allow_conditioanl_value);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]500
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]501UINT16 TPMI_DH_PERSISTENT_Marshal(TPMI_DH_PERSISTENT* source,
502 BYTE** buffer,
503 INT32* size);
504
505TPM_RC TPMI_DH_PERSISTENT_Unmarshal(TPMI_DH_PERSISTENT* target,
506 BYTE** buffer,
507 INT32* size);
508
509UINT16 TPM_ECC_CURVE_Marshal(TPM_ECC_CURVE* source, BYTE** buffer, INT32* size);
510
511TPM_RC TPM_ECC_CURVE_Unmarshal(TPM_ECC_CURVE* target,
512 BYTE** buffer,
513 INT32* size);
514
515UINT16 TPMI_ECC_CURVE_Marshal(TPMI_ECC_CURVE* source,
516 BYTE** buffer,
517 INT32* size);
518
519TPM_RC TPMI_ECC_CURVE_Unmarshal(TPMI_ECC_CURVE* target,
520 BYTE** buffer,
521 INT32* size);
522
523UINT16 TPMI_ECC_KEY_EXCHANGE_Marshal(TPMI_ECC_KEY_EXCHANGE* source,
524 BYTE** buffer,
525 INT32* size);
526
527TPM_RC TPMI_ECC_KEY_EXCHANGE_Unmarshal(TPMI_ECC_KEY_EXCHANGE* target,
528 BYTE** buffer,
529 INT32* size,
530 BOOL allow_conditioanl_value);
531
532UINT16 TPMI_RH_CLEAR_Marshal(TPMI_RH_CLEAR* source, BYTE** buffer, INT32* size);
533
534TPM_RC TPMI_RH_CLEAR_Unmarshal(TPMI_RH_CLEAR* target,
535 BYTE** buffer,
536 INT32* size);
537
538UINT16 TPMI_RH_ENABLES_Marshal(TPMI_RH_ENABLES* source,
539 BYTE** buffer,
540 INT32* size);
541
542TPM_RC TPMI_RH_ENABLES_Unmarshal(TPMI_RH_ENABLES* target,
543 BYTE** buffer,
544 INT32* size,
545 BOOL allow_conditioanl_value);
546
547UINT16 TPMI_RH_ENDORSEMENT_Marshal(TPMI_RH_ENDORSEMENT* source,
548 BYTE** buffer,
549 INT32* size);
550
551TPM_RC TPMI_RH_ENDORSEMENT_Unmarshal(TPMI_RH_ENDORSEMENT* target,
552 BYTE** buffer,
553 INT32* size,
554 BOOL allow_conditioanl_value);
555
556UINT16 TPMI_RH_HIERARCHY_Marshal(TPMI_RH_HIERARCHY* source,
557 BYTE** buffer,
558 INT32* size);
559
560TPM_RC TPMI_RH_HIERARCHY_Unmarshal(TPMI_RH_HIERARCHY* target,
561 BYTE** buffer,
562 INT32* size,
563 BOOL allow_conditioanl_value);
564
565UINT16 TPMI_RH_HIERARCHY_AUTH_Marshal(TPMI_RH_HIERARCHY_AUTH* source,
566 BYTE** buffer,
567 INT32* size);
568
569TPM_RC TPMI_RH_HIERARCHY_AUTH_Unmarshal(TPMI_RH_HIERARCHY_AUTH* target,
570 BYTE** buffer,
571 INT32* size);
572
573UINT16 TPMI_RH_LOCKOUT_Marshal(TPMI_RH_LOCKOUT* source,
574 BYTE** buffer,
575 INT32* size);
576
577TPM_RC TPMI_RH_LOCKOUT_Unmarshal(TPMI_RH_LOCKOUT* target,
578 BYTE** buffer,
579 INT32* size);
580
581UINT16 TPMI_RH_NV_AUTH_Marshal(TPMI_RH_NV_AUTH* source,
582 BYTE** buffer,
583 INT32* size);
584
585TPM_RC TPMI_RH_NV_AUTH_Unmarshal(TPMI_RH_NV_AUTH* target,
586 BYTE** buffer,
587 INT32* size);
588
589UINT16 TPMI_RH_NV_INDEX_Marshal(TPMI_RH_NV_INDEX* source,
590 BYTE** buffer,
591 INT32* size);
592
593TPM_RC TPMI_RH_NV_INDEX_Unmarshal(TPMI_RH_NV_INDEX* target,
594 BYTE** buffer,
595 INT32* size);
596
597UINT16 TPMI_RH_OWNER_Marshal(TPMI_RH_OWNER* source, BYTE** buffer, INT32* size);
598
599TPM_RC TPMI_RH_OWNER_Unmarshal(TPMI_RH_OWNER* target,
600 BYTE** buffer,
601 INT32* size,
602 BOOL allow_conditioanl_value);
603
604UINT16 TPMI_RH_PLATFORM_Marshal(TPMI_RH_PLATFORM* source,
605 BYTE** buffer,
606 INT32* size);
607
608TPM_RC TPMI_RH_PLATFORM_Unmarshal(TPMI_RH_PLATFORM* target,
609 BYTE** buffer,
610 INT32* size);
611
612UINT16 TPMI_RH_PROVISION_Marshal(TPMI_RH_PROVISION* source,
613 BYTE** buffer,
614 INT32* size);
615
616TPM_RC TPMI_RH_PROVISION_Unmarshal(TPMI_RH_PROVISION* target,
617 BYTE** buffer,
618 INT32* size);
619
620UINT16 TPMI_RSA_KEY_BITS_Marshal(TPMI_RSA_KEY_BITS* source,
621 BYTE** buffer,
622 INT32* size);
623
624TPM_RC TPMI_RSA_KEY_BITS_Unmarshal(TPMI_RSA_KEY_BITS* target,
625 BYTE** buffer,
626 INT32* size);
627
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]628UINT16 TPMI_SH_AUTH_SESSION_Marshal(TPMI_SH_AUTH_SESSION* source,
629 BYTE** buffer,
630 INT32* size);
631
632TPM_RC TPMI_SH_AUTH_SESSION_Unmarshal(TPMI_SH_AUTH_SESSION* target,
633 BYTE** buffer,
634 INT32* size,
635 BOOL allow_conditioanl_value);
636
637UINT16 TPMI_SH_HMAC_Marshal(TPMI_SH_HMAC* source, BYTE** buffer, INT32* size);
638
639TPM_RC TPMI_SH_HMAC_Unmarshal(TPMI_SH_HMAC* target, BYTE** buffer, INT32* size);
640
641UINT16 TPMI_SH_POLICY_Marshal(TPMI_SH_POLICY* source,
642 BYTE** buffer,
643 INT32* size);
644
645TPM_RC TPMI_SH_POLICY_Unmarshal(TPMI_SH_POLICY* target,
646 BYTE** buffer,
647 INT32* size);
648
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]649UINT16 TPMI_SM4_KEY_BITS_Marshal(TPMI_SM4_KEY_BITS* source,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]650 BYTE** buffer,
651 INT32* size);
652
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]653TPM_RC TPMI_SM4_KEY_BITS_Unmarshal(TPMI_SM4_KEY_BITS* target,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]654 BYTE** buffer,
655 INT32* size);
656
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]657UINT16 TPM_ST_Marshal(TPM_ST* source, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]658
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]659TPM_RC TPM_ST_Unmarshal(TPM_ST* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]660
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]661UINT16 TPMI_ST_ATTEST_Marshal(TPMI_ST_ATTEST* source,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]662 BYTE** buffer,
663 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]664
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]665TPM_RC TPMI_ST_ATTEST_Unmarshal(TPMI_ST_ATTEST* target,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]666 BYTE** buffer,
667 INT32* size);
668
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]669UINT16 TPMI_ST_COMMAND_TAG_Marshal(TPMI_ST_COMMAND_TAG* source,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]670 BYTE** buffer,
671 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]672
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]673TPM_RC TPMI_ST_COMMAND_TAG_Unmarshal(TPMI_ST_COMMAND_TAG* target,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]674 BYTE** buffer,
675 INT32* size);
676
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]677UINT16 TPMI_YES_NO_Marshal(TPMI_YES_NO* source, BYTE** buffer, INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]678
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]679TPM_RC TPMI_YES_NO_Unmarshal(TPMI_YES_NO* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]680
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]681UINT16 TPML_ALG_Marshal(TPML_ALG* source, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]682
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]683TPM_RC TPML_ALG_Unmarshal(TPML_ALG* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]684
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]685UINT16 TPML_ALG_PROPERTY_Marshal(TPML_ALG_PROPERTY* source,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]686 BYTE** buffer,
687 INT32* size);
688
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]689TPM_RC TPML_ALG_PROPERTY_Unmarshal(TPML_ALG_PROPERTY* target,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]690 BYTE** buffer,
691 INT32* size);
692
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]693UINT16 TPML_CC_Marshal(TPML_CC* source, BYTE** buffer, INT32* size);
694
695TPM_RC TPML_CC_Unmarshal(TPML_CC* target, BYTE** buffer, INT32* size);
696
697UINT16 TPML_CCA_Marshal(TPML_CCA* source, BYTE** buffer, INT32* size);
698
699TPM_RC TPML_CCA_Unmarshal(TPML_CCA* target, BYTE** buffer, INT32* size);
700
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]701UINT16 TPML_DIGEST_Marshal(TPML_DIGEST* source, BYTE** buffer, INT32* size);
702
703TPM_RC TPML_DIGEST_Unmarshal(TPML_DIGEST* target, BYTE** buffer, INT32* size);
704
705UINT16 TPML_DIGEST_VALUES_Marshal(TPML_DIGEST_VALUES* source,
706 BYTE** buffer,
707 INT32* size);
708
709TPM_RC TPML_DIGEST_VALUES_Unmarshal(TPML_DIGEST_VALUES* target,
710 BYTE** buffer,
711 INT32* size);
712
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]713UINT16 TPML_ECC_CURVE_Marshal(TPML_ECC_CURVE* source,
714 BYTE** buffer,
715 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]716
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]717TPM_RC TPML_ECC_CURVE_Unmarshal(TPML_ECC_CURVE* target,
718 BYTE** buffer,
719 INT32* size);
720
721UINT16 TPML_HANDLE_Marshal(TPML_HANDLE* source, BYTE** buffer, INT32* size);
722
723TPM_RC TPML_HANDLE_Unmarshal(TPML_HANDLE* target, BYTE** buffer, INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]724
725UINT16 TPML_PCR_SELECTION_Marshal(TPML_PCR_SELECTION* source,
726 BYTE** buffer,
727 INT32* size);
728
729TPM_RC TPML_PCR_SELECTION_Unmarshal(TPML_PCR_SELECTION* target,
730 BYTE** buffer,
731 INT32* size);
732
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]733UINT16 TPML_TAGGED_PCR_PROPERTY_Marshal(TPML_TAGGED_PCR_PROPERTY* source,
734 BYTE** buffer,
735 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]736
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]737TPM_RC TPML_TAGGED_PCR_PROPERTY_Unmarshal(TPML_TAGGED_PCR_PROPERTY* target,
738 BYTE** buffer,
739 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]740
741UINT16 TPML_TAGGED_TPM_PROPERTY_Marshal(TPML_TAGGED_TPM_PROPERTY* source,
742 BYTE** buffer,
743 INT32* size);
744
745TPM_RC TPML_TAGGED_TPM_PROPERTY_Unmarshal(TPML_TAGGED_TPM_PROPERTY* target,
746 BYTE** buffer,
747 INT32* size);
748
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]749UINT16 TPMS_ALGORITHM_DESCRIPTION_Marshal(TPMS_ALGORITHM_DESCRIPTION* source,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]750 BYTE** buffer,
751 INT32* size);
752
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]753TPM_RC TPMS_ALGORITHM_DESCRIPTION_Unmarshal(TPMS_ALGORITHM_DESCRIPTION* target,
754 BYTE** buffer,
755 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]756
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]757UINT16 TPMS_ALGORITHM_DETAIL_ECC_Marshal(TPMS_ALGORITHM_DETAIL_ECC* source,
758 BYTE** buffer,
759 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]760
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]761TPM_RC TPMS_ALGORITHM_DETAIL_ECC_Unmarshal(TPMS_ALGORITHM_DETAIL_ECC* target,
762 BYTE** buffer,
763 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]764
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]765UINT16 TPMS_ALG_PROPERTY_Marshal(TPMS_ALG_PROPERTY* source,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]766 BYTE** buffer,
767 INT32* size);
768
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]769TPM_RC TPMS_ALG_PROPERTY_Unmarshal(TPMS_ALG_PROPERTY* target,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]770 BYTE** buffer,
771 INT32* size);
772
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]773UINT16 TPMS_ASYM_PARMS_Marshal(TPMS_ASYM_PARMS* source,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]774 BYTE** buffer,
775 INT32* size);
776
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]777TPM_RC TPMS_ASYM_PARMS_Unmarshal(TPMS_ASYM_PARMS* target,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]778 BYTE** buffer,
779 INT32* size);
780
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]781UINT16 TPMS_ATTEST_Marshal(TPMS_ATTEST* source, BYTE** buffer, INT32* size);
782
783TPM_RC TPMS_ATTEST_Unmarshal(TPMS_ATTEST* target, BYTE** buffer, INT32* size);
784
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]785UINT16 TPMS_AUTH_COMMAND_Marshal(TPMS_AUTH_COMMAND* source,
786 BYTE** buffer,
787 INT32* size);
788
789TPM_RC TPMS_AUTH_COMMAND_Unmarshal(TPMS_AUTH_COMMAND* target,
790 BYTE** buffer,
791 INT32* size);
792
793UINT16 TPMS_AUTH_RESPONSE_Marshal(TPMS_AUTH_RESPONSE* source,
794 BYTE** buffer,
795 INT32* size);
796
797TPM_RC TPMS_AUTH_RESPONSE_Unmarshal(TPMS_AUTH_RESPONSE* target,
798 BYTE** buffer,
799 INT32* size);
800
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]801UINT16 TPMS_CAPABILITY_DATA_Marshal(TPMS_CAPABILITY_DATA* source,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]802 BYTE** buffer,
803 INT32* size);
804
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]805TPM_RC TPMS_CAPABILITY_DATA_Unmarshal(TPMS_CAPABILITY_DATA* target,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]806 BYTE** buffer,
807 INT32* size);
808
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]809UINT16 TPMS_CERTIFY_INFO_Marshal(TPMS_CERTIFY_INFO* source,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]810 BYTE** buffer,
811 INT32* size);
812
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]813TPM_RC TPMS_CERTIFY_INFO_Unmarshal(TPMS_CERTIFY_INFO* target,
814 BYTE** buffer,
815 INT32* size);
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]816
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]817UINT16 TPMS_CLOCK_INFO_Marshal(TPMS_CLOCK_INFO* source,
818 BYTE** buffer,
819 INT32* size);
820
821TPM_RC TPMS_CLOCK_INFO_Unmarshal(TPMS_CLOCK_INFO* target,
822 BYTE** buffer,
823 INT32* size);
824
825UINT16 TPMS_COMMAND_AUDIT_INFO_Marshal(TPMS_COMMAND_AUDIT_INFO* source,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]826 BYTE** buffer,
827 INT32* size);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]828
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]829TPM_RC TPMS_COMMAND_AUDIT_INFO_Unmarshal(TPMS_COMMAND_AUDIT_INFO* target,
830 BYTE** buffer,
831 INT32* size);
832
833UINT16 TPMS_CONTEXT_Marshal(TPMS_CONTEXT* source, BYTE** buffer, INT32* size);
834
835TPM_RC TPMS_CONTEXT_Unmarshal(TPMS_CONTEXT* target, BYTE** buffer, INT32* size);
836
837UINT16 TPMS_CONTEXT_DATA_Marshal(TPMS_CONTEXT_DATA* source,
838 BYTE** buffer,
839 INT32* size);
840
841TPM_RC TPMS_CONTEXT_DATA_Unmarshal(TPMS_CONTEXT_DATA* target,
842 BYTE** buffer,
843 INT32* size);
844
845UINT16 TPMS_CREATION_DATA_Marshal(TPMS_CREATION_DATA* source,
846 BYTE** buffer,
847 INT32* size);
848
849TPM_RC TPMS_CREATION_DATA_Unmarshal(TPMS_CREATION_DATA* target,
850 BYTE** buffer,
851 INT32* size);
852
853UINT16 TPMS_CREATION_INFO_Marshal(TPMS_CREATION_INFO* source,
854 BYTE** buffer,
855 INT32* size);
856
857TPM_RC TPMS_CREATION_INFO_Unmarshal(TPMS_CREATION_INFO* target,
858 BYTE** buffer,
859 INT32* size);
860
861UINT16 TPMS_ECC_PARMS_Marshal(TPMS_ECC_PARMS* source,
862 BYTE** buffer,
863 INT32* size);
864
865TPM_RC TPMS_ECC_PARMS_Unmarshal(TPMS_ECC_PARMS* target,
866 BYTE** buffer,
867 INT32* size);
868
869UINT16 TPMS_ECC_POINT_Marshal(TPMS_ECC_POINT* source,
870 BYTE** buffer,
871 INT32* size);
872
873TPM_RC TPMS_ECC_POINT_Unmarshal(TPMS_ECC_POINT* target,
874 BYTE** buffer,
875 INT32* size);
876
Vadim Bendebury0232bac2015-09-17 17:26:29 -0700[diff] [blame]877UINT16 TPMS_EMPTY_Marshal(TPMS_EMPTY* source, BYTE** buffer, INT32* size);
878
879TPM_RC TPMS_EMPTY_Unmarshal(TPMS_EMPTY* target, BYTE** buffer, INT32* size);
880
881UINT16 TPMS_SCHEME_HASH_Marshal(TPMS_SCHEME_HASH* source,
882 BYTE** buffer,
883 INT32* size);
884
885TPM_RC TPMS_SCHEME_HASH_Unmarshal(TPMS_SCHEME_HASH* target,
886 BYTE** buffer,
887 INT32* size);
888
889UINT16 TPMS_ENC_SCHEME_OAEP_Marshal(TPMS_ENC_SCHEME_OAEP* source,
890 BYTE** buffer,
891 INT32* size);
892
893TPM_RC TPMS_ENC_SCHEME_OAEP_Unmarshal(TPMS_ENC_SCHEME_OAEP* target,
894 BYTE** buffer,
895 INT32* size);
896
897UINT16 TPMS_ENC_SCHEME_RSAES_Marshal(TPMS_ENC_SCHEME_RSAES* source,
898 BYTE** buffer,
899 INT32* size);
900
901TPM_RC TPMS_ENC_SCHEME_RSAES_Unmarshal(TPMS_ENC_SCHEME_RSAES* target,
902 BYTE** buffer,
903 INT32* size);
904
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]905UINT16 TPMS_KEYEDHASH_PARMS_Marshal(TPMS_KEYEDHASH_PARMS* source,
906 BYTE** buffer,
907 INT32* size);
908
909TPM_RC TPMS_KEYEDHASH_PARMS_Unmarshal(TPMS_KEYEDHASH_PARMS* target,
910 BYTE** buffer,
911 INT32* size);
912
Vadim Bendebury0232bac2015-09-17 17:26:29 -0700[diff] [blame]913UINT16 TPMS_KEY_SCHEME_ECDH_Marshal(TPMS_KEY_SCHEME_ECDH* source,
914 BYTE** buffer,
915 INT32* size);
916
917TPM_RC TPMS_KEY_SCHEME_ECDH_Unmarshal(TPMS_KEY_SCHEME_ECDH* target,
918 BYTE** buffer,
919 INT32* size);
920
921UINT16 TPMS_KEY_SCHEME_ECMQV_Marshal(TPMS_KEY_SCHEME_ECMQV* source,
922 BYTE** buffer,
923 INT32* size);
924
925TPM_RC TPMS_KEY_SCHEME_ECMQV_Unmarshal(TPMS_KEY_SCHEME_ECMQV* target,
926 BYTE** buffer,
927 INT32* size);
928
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]929UINT16 TPMS_NV_CERTIFY_INFO_Marshal(TPMS_NV_CERTIFY_INFO* source,
930 BYTE** buffer,
931 INT32* size);
932
933TPM_RC TPMS_NV_CERTIFY_INFO_Unmarshal(TPMS_NV_CERTIFY_INFO* target,
934 BYTE** buffer,
935 INT32* size);
936
937UINT16 TPMS_NV_PUBLIC_Marshal(TPMS_NV_PUBLIC* source,
938 BYTE** buffer,
939 INT32* size);
940
941TPM_RC TPMS_NV_PUBLIC_Unmarshal(TPMS_NV_PUBLIC* target,
942 BYTE** buffer,
943 INT32* size);
944
945UINT16 TPMS_PCR_SELECT_Marshal(TPMS_PCR_SELECT* source,
946 BYTE** buffer,
947 INT32* size);
948
949TPM_RC TPMS_PCR_SELECT_Unmarshal(TPMS_PCR_SELECT* target,
950 BYTE** buffer,
951 INT32* size);
952
953UINT16 TPMS_PCR_SELECTION_Marshal(TPMS_PCR_SELECTION* source,
954 BYTE** buffer,
955 INT32* size);
956
957TPM_RC TPMS_PCR_SELECTION_Unmarshal(TPMS_PCR_SELECTION* target,
958 BYTE** buffer,
959 INT32* size);
960
961UINT16 TPMS_QUOTE_INFO_Marshal(TPMS_QUOTE_INFO* source,
962 BYTE** buffer,
963 INT32* size);
964
965TPM_RC TPMS_QUOTE_INFO_Unmarshal(TPMS_QUOTE_INFO* target,
966 BYTE** buffer,
967 INT32* size);
968
969UINT16 TPMS_RSA_PARMS_Marshal(TPMS_RSA_PARMS* source,
970 BYTE** buffer,
971 INT32* size);
972
973TPM_RC TPMS_RSA_PARMS_Unmarshal(TPMS_RSA_PARMS* target,
974 BYTE** buffer,
975 INT32* size);
976
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]977UINT16 TPMS_SCHEME_ECDAA_Marshal(TPMS_SCHEME_ECDAA* source,
978 BYTE** buffer,
979 INT32* size);
980
981TPM_RC TPMS_SCHEME_ECDAA_Unmarshal(TPMS_SCHEME_ECDAA* target,
982 BYTE** buffer,
983 INT32* size);
984
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]985UINT16 TPMS_SCHEME_HMAC_Marshal(TPMS_SCHEME_HMAC* source,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]986 BYTE** buffer,
987 INT32* size);
988
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]989TPM_RC TPMS_SCHEME_HMAC_Unmarshal(TPMS_SCHEME_HMAC* target,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]990 BYTE** buffer,
991 INT32* size);
992
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]993UINT16 TPMS_SCHEME_KDF1_SP800_108_Marshal(TPMS_SCHEME_KDF1_SP800_108* source,
994 BYTE** buffer,
995 INT32* size);
996
997TPM_RC TPMS_SCHEME_KDF1_SP800_108_Unmarshal(TPMS_SCHEME_KDF1_SP800_108* target,
998 BYTE** buffer,
999 INT32* size);
1000
Vadim Bendebury0232bac2015-09-17 17:26:29 -0700[diff] [blame]1001UINT16 TPMS_SCHEME_KDF1_SP800_56A_Marshal(TPMS_SCHEME_KDF1_SP800_56A* source,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1002 BYTE** buffer,
1003 INT32* size);
1004
Vadim Bendebury0232bac2015-09-17 17:26:29 -0700[diff] [blame]1005TPM_RC TPMS_SCHEME_KDF1_SP800_56A_Unmarshal(TPMS_SCHEME_KDF1_SP800_56A* target,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1006 BYTE** buffer,
1007 INT32* size);
1008
1009UINT16 TPMS_SCHEME_KDF2_Marshal(TPMS_SCHEME_KDF2* source,
1010 BYTE** buffer,
1011 INT32* size);
1012
1013TPM_RC TPMS_SCHEME_KDF2_Unmarshal(TPMS_SCHEME_KDF2* target,
1014 BYTE** buffer,
1015 INT32* size);
1016
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1017UINT16 TPMS_SCHEME_MGF1_Marshal(TPMS_SCHEME_MGF1* source,
1018 BYTE** buffer,
1019 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1020
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1021TPM_RC TPMS_SCHEME_MGF1_Unmarshal(TPMS_SCHEME_MGF1* target,
1022 BYTE** buffer,
1023 INT32* size);
1024
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1025UINT16 TPMS_SCHEME_XOR_Marshal(TPMS_SCHEME_XOR* source,
1026 BYTE** buffer,
1027 INT32* size);
1028
1029TPM_RC TPMS_SCHEME_XOR_Unmarshal(TPMS_SCHEME_XOR* target,
1030 BYTE** buffer,
1031 INT32* size);
1032
1033UINT16 TPMS_SENSITIVE_CREATE_Marshal(TPMS_SENSITIVE_CREATE* source,
1034 BYTE** buffer,
1035 INT32* size);
1036
1037TPM_RC TPMS_SENSITIVE_CREATE_Unmarshal(TPMS_SENSITIVE_CREATE* target,
1038 BYTE** buffer,
1039 INT32* size);
1040
1041UINT16 TPMS_SESSION_AUDIT_INFO_Marshal(TPMS_SESSION_AUDIT_INFO* source,
1042 BYTE** buffer,
1043 INT32* size);
1044
1045TPM_RC TPMS_SESSION_AUDIT_INFO_Unmarshal(TPMS_SESSION_AUDIT_INFO* target,
1046 BYTE** buffer,
1047 INT32* size);
1048
Vadim Bendebury0232bac2015-09-17 17:26:29 -0700[diff] [blame]1049UINT16 TPMS_SIGNATURE_ECC_Marshal(TPMS_SIGNATURE_ECC* source,
1050 BYTE** buffer,
1051 INT32* size);
1052
1053TPM_RC TPMS_SIGNATURE_ECC_Unmarshal(TPMS_SIGNATURE_ECC* target,
1054 BYTE** buffer,
1055 INT32* size);
1056
1057UINT16 TPMS_SIGNATURE_ECDAA_Marshal(TPMS_SIGNATURE_ECDAA* source,
1058 BYTE** buffer,
1059 INT32* size);
1060
1061TPM_RC TPMS_SIGNATURE_ECDAA_Unmarshal(TPMS_SIGNATURE_ECDAA* target,
1062 BYTE** buffer,
1063 INT32* size);
1064
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1065UINT16 TPMS_SIGNATURE_ECDSA_Marshal(TPMS_SIGNATURE_ECDSA* source,
1066 BYTE** buffer,
1067 INT32* size);
1068
1069TPM_RC TPMS_SIGNATURE_ECDSA_Unmarshal(TPMS_SIGNATURE_ECDSA* target,
1070 BYTE** buffer,
1071 INT32* size);
1072
Vadim Bendebury0232bac2015-09-17 17:26:29 -0700[diff] [blame]1073UINT16 TPMS_SIGNATURE_ECSCHNORR_Marshal(TPMS_SIGNATURE_ECSCHNORR* source,
1074 BYTE** buffer,
1075 INT32* size);
1076
1077TPM_RC TPMS_SIGNATURE_ECSCHNORR_Unmarshal(TPMS_SIGNATURE_ECSCHNORR* target,
1078 BYTE** buffer,
1079 INT32* size);
1080
1081UINT16 TPMS_SIGNATURE_RSA_Marshal(TPMS_SIGNATURE_RSA* source,
1082 BYTE** buffer,
1083 INT32* size);
1084
1085TPM_RC TPMS_SIGNATURE_RSA_Unmarshal(TPMS_SIGNATURE_RSA* target,
1086 BYTE** buffer,
1087 INT32* size);
1088
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1089UINT16 TPMS_SIGNATURE_RSAPSS_Marshal(TPMS_SIGNATURE_RSAPSS* source,
1090 BYTE** buffer,
1091 INT32* size);
1092
1093TPM_RC TPMS_SIGNATURE_RSAPSS_Unmarshal(TPMS_SIGNATURE_RSAPSS* target,
1094 BYTE** buffer,
1095 INT32* size);
1096
1097UINT16 TPMS_SIGNATURE_RSASSA_Marshal(TPMS_SIGNATURE_RSASSA* source,
1098 BYTE** buffer,
1099 INT32* size);
1100
1101TPM_RC TPMS_SIGNATURE_RSASSA_Unmarshal(TPMS_SIGNATURE_RSASSA* target,
1102 BYTE** buffer,
1103 INT32* size);
1104
Vadim Bendebury0232bac2015-09-17 17:26:29 -0700[diff] [blame]1105UINT16 TPMS_SIGNATURE_SM2_Marshal(TPMS_SIGNATURE_SM2* source,
1106 BYTE** buffer,
1107 INT32* size);
1108
1109TPM_RC TPMS_SIGNATURE_SM2_Unmarshal(TPMS_SIGNATURE_SM2* target,
1110 BYTE** buffer,
1111 INT32* size);
1112
1113UINT16 TPMS_SIG_SCHEME_ECDAA_Marshal(TPMS_SIG_SCHEME_ECDAA* source,
1114 BYTE** buffer,
1115 INT32* size);
1116
1117TPM_RC TPMS_SIG_SCHEME_ECDAA_Unmarshal(TPMS_SIG_SCHEME_ECDAA* target,
1118 BYTE** buffer,
1119 INT32* size);
1120
1121UINT16 TPMS_SIG_SCHEME_ECDSA_Marshal(TPMS_SIG_SCHEME_ECDSA* source,
1122 BYTE** buffer,
1123 INT32* size);
1124
1125TPM_RC TPMS_SIG_SCHEME_ECDSA_Unmarshal(TPMS_SIG_SCHEME_ECDSA* target,
1126 BYTE** buffer,
1127 INT32* size);
1128
1129UINT16 TPMS_SIG_SCHEME_ECSCHNORR_Marshal(TPMS_SIG_SCHEME_ECSCHNORR* source,
1130 BYTE** buffer,
1131 INT32* size);
1132
1133TPM_RC TPMS_SIG_SCHEME_ECSCHNORR_Unmarshal(TPMS_SIG_SCHEME_ECSCHNORR* target,
1134 BYTE** buffer,
1135 INT32* size);
1136
1137UINT16 TPMS_SIG_SCHEME_RSAPSS_Marshal(TPMS_SIG_SCHEME_RSAPSS* source,
1138 BYTE** buffer,
1139 INT32* size);
1140
1141TPM_RC TPMS_SIG_SCHEME_RSAPSS_Unmarshal(TPMS_SIG_SCHEME_RSAPSS* target,
1142 BYTE** buffer,
1143 INT32* size);
1144
1145UINT16 TPMS_SIG_SCHEME_RSASSA_Marshal(TPMS_SIG_SCHEME_RSASSA* source,
1146 BYTE** buffer,
1147 INT32* size);
1148
1149TPM_RC TPMS_SIG_SCHEME_RSASSA_Unmarshal(TPMS_SIG_SCHEME_RSASSA* target,
1150 BYTE** buffer,
1151 INT32* size);
1152
1153UINT16 TPMS_SIG_SCHEME_SM2_Marshal(TPMS_SIG_SCHEME_SM2* source,
1154 BYTE** buffer,
1155 INT32* size);
1156
1157TPM_RC TPMS_SIG_SCHEME_SM2_Unmarshal(TPMS_SIG_SCHEME_SM2* target,
1158 BYTE** buffer,
1159 INT32* size);
1160
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1161UINT16 TPMS_SYMCIPHER_PARMS_Marshal(TPMS_SYMCIPHER_PARMS* source,
1162 BYTE** buffer,
1163 INT32* size);
1164
1165TPM_RC TPMS_SYMCIPHER_PARMS_Unmarshal(TPMS_SYMCIPHER_PARMS* target,
1166 BYTE** buffer,
1167 INT32* size);
1168
1169UINT16 TPMS_TAGGED_PCR_SELECT_Marshal(TPMS_TAGGED_PCR_SELECT* source,
1170 BYTE** buffer,
1171 INT32* size);
1172
1173TPM_RC TPMS_TAGGED_PCR_SELECT_Unmarshal(TPMS_TAGGED_PCR_SELECT* target,
1174 BYTE** buffer,
1175 INT32* size);
1176
1177UINT16 TPMS_TAGGED_PROPERTY_Marshal(TPMS_TAGGED_PROPERTY* source,
1178 BYTE** buffer,
1179 INT32* size);
1180
1181TPM_RC TPMS_TAGGED_PROPERTY_Unmarshal(TPMS_TAGGED_PROPERTY* target,
1182 BYTE** buffer,
1183 INT32* size);
1184
1185UINT16 TPMS_TIME_ATTEST_INFO_Marshal(TPMS_TIME_ATTEST_INFO* source,
1186 BYTE** buffer,
1187 INT32* size);
1188
1189TPM_RC TPMS_TIME_ATTEST_INFO_Unmarshal(TPMS_TIME_ATTEST_INFO* target,
1190 BYTE** buffer,
1191 INT32* size);
1192
1193UINT16 TPMS_TIME_INFO_Marshal(TPMS_TIME_INFO* source,
1194 BYTE** buffer,
1195 INT32* size);
1196
1197TPM_RC TPMS_TIME_INFO_Unmarshal(TPMS_TIME_INFO* target,
1198 BYTE** buffer,
1199 INT32* size);
1200
1201UINT16 TPMT_ASYM_SCHEME_Marshal(TPMT_ASYM_SCHEME* source,
1202 BYTE** buffer,
1203 INT32* size);
1204
1205TPM_RC TPMT_ASYM_SCHEME_Unmarshal(TPMT_ASYM_SCHEME* target,
1206 BYTE** buffer,
1207 INT32* size);
1208
1209UINT16 TPMT_ECC_SCHEME_Marshal(TPMT_ECC_SCHEME* source,
1210 BYTE** buffer,
1211 INT32* size);
1212
1213TPM_RC TPMT_ECC_SCHEME_Unmarshal(TPMT_ECC_SCHEME* target,
1214 BYTE** buffer,
1215 INT32* size);
1216
1217UINT16 TPMT_HA_Marshal(TPMT_HA* source, BYTE** buffer, INT32* size);
1218
1219TPM_RC TPMT_HA_Unmarshal(TPMT_HA* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1220
1221UINT16 TPMT_KDF_SCHEME_Marshal(TPMT_KDF_SCHEME* source,
1222 BYTE** buffer,
1223 INT32* size);
1224
1225TPM_RC TPMT_KDF_SCHEME_Unmarshal(TPMT_KDF_SCHEME* target,
1226 BYTE** buffer,
1227 INT32* size);
1228
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1229UINT16 TPMT_KEYEDHASH_SCHEME_Marshal(TPMT_KEYEDHASH_SCHEME* source,
1230 BYTE** buffer,
1231 INT32* size);
1232
1233TPM_RC TPMT_KEYEDHASH_SCHEME_Unmarshal(TPMT_KEYEDHASH_SCHEME* target,
1234 BYTE** buffer,
1235 INT32* size);
1236
1237UINT16 TPMT_PUBLIC_Marshal(TPMT_PUBLIC* source, BYTE** buffer, INT32* size);
1238
1239TPM_RC TPMT_PUBLIC_Unmarshal(TPMT_PUBLIC* target, BYTE** buffer, INT32* size);
1240
1241UINT16 TPMT_PUBLIC_PARMS_Marshal(TPMT_PUBLIC_PARMS* source,
1242 BYTE** buffer,
1243 INT32* size);
1244
1245TPM_RC TPMT_PUBLIC_PARMS_Unmarshal(TPMT_PUBLIC_PARMS* target,
1246 BYTE** buffer,
1247 INT32* size);
1248
1249UINT16 TPMT_RSA_DECRYPT_Marshal(TPMT_RSA_DECRYPT* source,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1250 BYTE** buffer,
1251 INT32* size);
1252
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1253TPM_RC TPMT_RSA_DECRYPT_Unmarshal(TPMT_RSA_DECRYPT* target,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1254 BYTE** buffer,
1255 INT32* size);
1256
1257UINT16 TPMT_RSA_SCHEME_Marshal(TPMT_RSA_SCHEME* source,
1258 BYTE** buffer,
1259 INT32* size);
1260
1261TPM_RC TPMT_RSA_SCHEME_Unmarshal(TPMT_RSA_SCHEME* target,
1262 BYTE** buffer,
1263 INT32* size);
1264
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1265UINT16 TPMT_SENSITIVE_Marshal(TPMT_SENSITIVE* source,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1266 BYTE** buffer,
1267 INT32* size);
1268
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1269TPM_RC TPMT_SENSITIVE_Unmarshal(TPMT_SENSITIVE* target,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1270 BYTE** buffer,
1271 INT32* size);
1272
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1273UINT16 TPMT_SIGNATURE_Marshal(TPMT_SIGNATURE* source,
1274 BYTE** buffer,
1275 INT32* size);
1276
1277TPM_RC TPMT_SIGNATURE_Unmarshal(TPMT_SIGNATURE* target,
1278 BYTE** buffer,
1279 INT32* size);
1280
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1281UINT16 TPMT_SIG_SCHEME_Marshal(TPMT_SIG_SCHEME* source,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1282 BYTE** buffer,
1283 INT32* size);
1284
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1285TPM_RC TPMT_SIG_SCHEME_Unmarshal(TPMT_SIG_SCHEME* target,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1286 BYTE** buffer,
1287 INT32* size);
1288
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1289UINT16 TPMT_SYM_DEF_Marshal(TPMT_SYM_DEF* source, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1290
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1291TPM_RC TPMT_SYM_DEF_Unmarshal(TPMT_SYM_DEF* target, BYTE** buffer, INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1292
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1293UINT16 TPMT_SYM_DEF_OBJECT_Marshal(TPMT_SYM_DEF_OBJECT* source,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1294 BYTE** buffer,
1295 INT32* size);
1296
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1297TPM_RC TPMT_SYM_DEF_OBJECT_Unmarshal(TPMT_SYM_DEF_OBJECT* target,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1298 BYTE** buffer,
1299 INT32* size);
1300
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1301UINT16 TPMT_TK_AUTH_Marshal(TPMT_TK_AUTH* source, BYTE** buffer, INT32* size);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1302
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1303TPM_RC TPMT_TK_AUTH_Unmarshal(TPMT_TK_AUTH* target, BYTE** buffer, INT32* size);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1304
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1305UINT16 TPMT_TK_CREATION_Marshal(TPMT_TK_CREATION* source,
1306 BYTE** buffer,
1307 INT32* size);
1308
1309TPM_RC TPMT_TK_CREATION_Unmarshal(TPMT_TK_CREATION* target,
1310 BYTE** buffer,
1311 INT32* size);
1312
1313UINT16 TPMT_TK_HASHCHECK_Marshal(TPMT_TK_HASHCHECK* source,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1314 BYTE** buffer,
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1315 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1316
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1317TPM_RC TPMT_TK_HASHCHECK_Unmarshal(TPMT_TK_HASHCHECK* target,
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1318 BYTE** buffer,
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1319 INT32* size);
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1320
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1321UINT16 TPMT_TK_VERIFIED_Marshal(TPMT_TK_VERIFIED* source,
1322 BYTE** buffer,
1323 INT32* size);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1324
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1325TPM_RC TPMT_TK_VERIFIED_Unmarshal(TPMT_TK_VERIFIED* target,
1326 BYTE** buffer,
1327 INT32* size);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1328
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]1329UINT16 TPMU_ASYM_SCHEME_Marshal(TPMU_ASYM_SCHEME* source,
1330 BYTE** buffer,
1331 INT32* size,
1332 UINT32 selector);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1333
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]1334TPM_RC TPMU_ASYM_SCHEME_Unmarshal(TPMU_ASYM_SCHEME* target,
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1335 BYTE** buffer,
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]1336 INT32* size,
1337 UINT32 selector);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1338
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1339UINT16 TPMU_ATTEST_Marshal(TPMU_ATTEST* source,
1340 BYTE** buffer,
1341 INT32* size,
1342 UINT32 selector);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1343
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1344TPM_RC TPMU_ATTEST_Unmarshal(TPMU_ATTEST* target,
1345 BYTE** buffer,
1346 INT32* size,
1347 UINT32 selector);
1348
1349UINT16 TPMU_CAPABILITIES_Marshal(TPMU_CAPABILITIES* source,
1350 BYTE** buffer,
1351 INT32* size,
1352 UINT32 selector);
1353
1354TPM_RC TPMU_CAPABILITIES_Unmarshal(TPMU_CAPABILITIES* target,
1355 BYTE** buffer,
1356 INT32* size,
1357 UINT32 selector);
1358
1359UINT16 TPMU_HA_Marshal(TPMU_HA* source,
1360 BYTE** buffer,
1361 INT32* size,
1362 UINT32 selector);
1363
1364TPM_RC TPMU_HA_Unmarshal(TPMU_HA* target,
1365 BYTE** buffer,
1366 INT32* size,
1367 UINT32 selector);
1368
1369UINT16 TPMU_KDF_SCHEME_Marshal(TPMU_KDF_SCHEME* source,
1370 BYTE** buffer,
1371 INT32* size,
1372 UINT32 selector);
1373
1374TPM_RC TPMU_KDF_SCHEME_Unmarshal(TPMU_KDF_SCHEME* target,
1375 BYTE** buffer,
1376 INT32* size,
1377 UINT32 selector);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1378
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]1379UINT16 TPMU_PUBLIC_ID_Marshal(TPMU_PUBLIC_ID* source,
1380 BYTE** buffer,
1381 INT32* size,
1382 UINT32 selector);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1383
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]1384TPM_RC TPMU_PUBLIC_ID_Unmarshal(TPMU_PUBLIC_ID* target,
1385 BYTE** buffer,
1386 INT32* size,
1387 UINT32 selector);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1388
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]1389UINT16 TPMU_PUBLIC_PARMS_Marshal(TPMU_PUBLIC_PARMS* source,
1390 BYTE** buffer,
1391 INT32* size,
1392 UINT32 selector);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1393
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]1394TPM_RC TPMU_PUBLIC_PARMS_Unmarshal(TPMU_PUBLIC_PARMS* target,
1395 BYTE** buffer,
1396 INT32* size,
1397 UINT32 selector);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1398
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1399UINT16 TPMU_SCHEME_KEYEDHASH_Marshal(TPMU_SCHEME_KEYEDHASH* source,
1400 BYTE** buffer,
1401 INT32* size,
1402 UINT32 selector);
1403
1404TPM_RC TPMU_SCHEME_KEYEDHASH_Unmarshal(TPMU_SCHEME_KEYEDHASH* target,
1405 BYTE** buffer,
1406 INT32* size,
1407 UINT32 selector);
1408
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]1409UINT16 TPMU_SENSITIVE_COMPOSITE_Marshal(TPMU_SENSITIVE_COMPOSITE* source,
1410 BYTE** buffer,
1411 INT32* size,
1412 UINT32 selector);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1413
Vadim Bendebury61620362015-09-08 19:51:45 +0000[diff] [blame]1414TPM_RC TPMU_SENSITIVE_COMPOSITE_Unmarshal(TPMU_SENSITIVE_COMPOSITE* target,
1415 BYTE** buffer,
1416 INT32* size,
1417 UINT32 selector);
Vadim Bendeburyb594f812015-09-04 17:56:44 -0700[diff] [blame]1418
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1419UINT16 TPMU_SIGNATURE_Marshal(TPMU_SIGNATURE* source,
1420 BYTE** buffer,
1421 INT32* size,
1422 UINT32 selector);
1423
1424TPM_RC TPMU_SIGNATURE_Unmarshal(TPMU_SIGNATURE* target,
1425 BYTE** buffer,
1426 INT32* size,
1427 UINT32 selector);
1428
1429UINT16 TPMU_SIG_SCHEME_Marshal(TPMU_SIG_SCHEME* source,
1430 BYTE** buffer,
1431 INT32* size,
1432 UINT32 selector);
1433
1434TPM_RC TPMU_SIG_SCHEME_Unmarshal(TPMU_SIG_SCHEME* target,
1435 BYTE** buffer,
1436 INT32* size,
1437 UINT32 selector);
1438
Vadim Bendebury0232bac2015-09-17 17:26:29 -0700[diff] [blame]1439UINT16 TPMU_SYM_DETAILS_Marshal(TPMU_SYM_DETAILS* source,
1440 BYTE** buffer,
1441 INT32* size,
1442 UINT32 selector);
1443
1444TPM_RC TPMU_SYM_DETAILS_Unmarshal(TPMU_SYM_DETAILS* target,
1445 BYTE** buffer,
1446 INT32* size,
1447 UINT32 selector);
1448
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1449UINT16 TPMU_SYM_KEY_BITS_Marshal(TPMU_SYM_KEY_BITS* source,
1450 BYTE** buffer,
1451 INT32* size,
1452 UINT32 selector);
1453
1454TPM_RC TPMU_SYM_KEY_BITS_Unmarshal(TPMU_SYM_KEY_BITS* target,
1455 BYTE** buffer,
1456 INT32* size,
1457 UINT32 selector);
1458
1459UINT16 TPMU_SYM_MODE_Marshal(TPMU_SYM_MODE* source,
1460 BYTE** buffer,
1461 INT32* size,
1462 UINT32 selector);
1463
1464TPM_RC TPMU_SYM_MODE_Unmarshal(TPMU_SYM_MODE* target,
1465 BYTE** buffer,
1466 INT32* size,
1467 UINT32 selector);
1468
1469UINT16 TPM_ALGORITHM_ID_Marshal(TPM_ALGORITHM_ID* source,
1470 BYTE** buffer,
1471 INT32* size);
1472
1473TPM_RC TPM_ALGORITHM_ID_Unmarshal(TPM_ALGORITHM_ID* target,
1474 BYTE** buffer,
1475 INT32* size);
1476
1477UINT16 TPM_AUTHORIZATION_SIZE_Marshal(TPM_AUTHORIZATION_SIZE* source,
1478 BYTE** buffer,
1479 INT32* size);
1480
1481TPM_RC TPM_AUTHORIZATION_SIZE_Unmarshal(TPM_AUTHORIZATION_SIZE* target,
1482 BYTE** buffer,
1483 INT32* size);
1484
1485UINT16 TPM_CAP_Marshal(TPM_CAP* source, BYTE** buffer, INT32* size);
1486
1487TPM_RC TPM_CAP_Unmarshal(TPM_CAP* target, BYTE** buffer, INT32* size);
1488
1489UINT16 TPM_CLOCK_ADJUST_Marshal(TPM_CLOCK_ADJUST* source,
1490 BYTE** buffer,
1491 INT32* size);
1492
1493TPM_RC TPM_CLOCK_ADJUST_Unmarshal(TPM_CLOCK_ADJUST* target,
1494 BYTE** buffer,
1495 INT32* size);
1496
1497UINT16 TPM_EO_Marshal(TPM_EO* source, BYTE** buffer, INT32* size);
1498
1499TPM_RC TPM_EO_Unmarshal(TPM_EO* target, BYTE** buffer, INT32* size);
1500
1501UINT16 TPM_GENERATED_Marshal(TPM_GENERATED* source, BYTE** buffer, INT32* size);
1502
1503TPM_RC TPM_GENERATED_Unmarshal(TPM_GENERATED* target,
1504 BYTE** buffer,
1505 INT32* size);
1506
1507UINT16 TPM_HC_Marshal(TPM_HC* source, BYTE** buffer, INT32* size);
1508
1509TPM_RC TPM_HC_Unmarshal(TPM_HC* target, BYTE** buffer, INT32* size);
1510
1511UINT16 TPM_HT_Marshal(TPM_HT* source, BYTE** buffer, INT32* size);
1512
1513TPM_RC TPM_HT_Unmarshal(TPM_HT* target, BYTE** buffer, INT32* size);
1514
1515UINT16 TPM_KEY_SIZE_Marshal(TPM_KEY_SIZE* source, BYTE** buffer, INT32* size);
1516
1517TPM_RC TPM_KEY_SIZE_Unmarshal(TPM_KEY_SIZE* target, BYTE** buffer, INT32* size);
1518
1519UINT16 TPM_MODIFIER_INDICATOR_Marshal(TPM_MODIFIER_INDICATOR* source,
1520 BYTE** buffer,
1521 INT32* size);
1522
1523TPM_RC TPM_MODIFIER_INDICATOR_Unmarshal(TPM_MODIFIER_INDICATOR* target,
1524 BYTE** buffer,
1525 INT32* size);
1526
1527UINT16 TPM_NV_INDEX_Marshal(TPM_NV_INDEX* source, BYTE** buffer, INT32* size);
1528
1529TPM_RC TPM_NV_INDEX_Unmarshal(TPM_NV_INDEX* target, BYTE** buffer, INT32* size);
1530
1531UINT16 TPM_PARAMETER_SIZE_Marshal(TPM_PARAMETER_SIZE* source,
1532 BYTE** buffer,
1533 INT32* size);
1534
1535TPM_RC TPM_PARAMETER_SIZE_Unmarshal(TPM_PARAMETER_SIZE* target,
1536 BYTE** buffer,
1537 INT32* size);
1538
Vadim Bendebury0232bac2015-09-17 17:26:29 -0700[diff] [blame]1539UINT16 TPM_PS_Marshal(TPM_PS* source, BYTE** buffer, INT32* size);
1540
1541TPM_RC TPM_PS_Unmarshal(TPM_PS* target, BYTE** buffer, INT32* size);
1542
Vadim Bendebury51208492015-09-04 17:56:44 -0700[diff] [blame]1543UINT16 TPM_PT_Marshal(TPM_PT* source, BYTE** buffer, INT32* size);
1544
1545TPM_RC TPM_PT_Unmarshal(TPM_PT* target, BYTE** buffer, INT32* size);
1546
1547UINT16 TPM_PT_PCR_Marshal(TPM_PT_PCR* source, BYTE** buffer, INT32* size);
1548
1549TPM_RC TPM_PT_PCR_Unmarshal(TPM_PT_PCR* target, BYTE** buffer, INT32* size);
1550
1551UINT16 TPM_RC_Marshal(TPM_RC* source, BYTE** buffer, INT32* size);
1552
1553TPM_RC TPM_RC_Unmarshal(TPM_RC* target, BYTE** buffer, INT32* size);
1554
1555UINT16 TPM_RH_Marshal(TPM_RH* source, BYTE** buffer, INT32* size);
1556
1557TPM_RC TPM_RH_Unmarshal(TPM_RH* target, BYTE** buffer, INT32* size);
1558
1559UINT16 TPM_SE_Marshal(TPM_SE* source, BYTE** buffer, INT32* size);
1560
1561TPM_RC TPM_SE_Unmarshal(TPM_SE* target, BYTE** buffer, INT32* size);
1562
1563UINT16 TPM_SPEC_Marshal(TPM_SPEC* source, BYTE** buffer, INT32* size);
1564
1565TPM_RC TPM_SPEC_Unmarshal(TPM_SPEC* target, BYTE** buffer, INT32* size);
1566
1567UINT16 TPM_SU_Marshal(TPM_SU* source, BYTE** buffer, INT32* size);
1568
1569TPM_RC TPM_SU_Unmarshal(TPM_SU* target, BYTE** buffer, INT32* size);
1570
1571UINT16 UINT64_Marshal(UINT64* source, BYTE** buffer, INT32* size);
1572
1573TPM_RC UINT64_Unmarshal(UINT64* target, BYTE** buffer, INT32* size);
1574
1575UINT16 _ID_OBJECT_Marshal(_ID_OBJECT* source, BYTE** buffer, INT32* size);
1576
1577TPM_RC _ID_OBJECT_Unmarshal(_ID_OBJECT* target, BYTE** buffer, INT32* size);
1578
1579UINT16 _PRIVATE_Marshal(_PRIVATE* source, BYTE** buffer, INT32* size);
1580
1581TPM_RC _PRIVATE_Unmarshal(_PRIVATE* target, BYTE** buffer, INT32* size);
1582
ChromeOS Developere85c65b2015-07-10 10:12:43 -0700[diff] [blame]1583#endif // TPM2_TPM_GENERATED_H_