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wdenkc15f3122004-10-10 22:44:24 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8540 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/* mpc8560ads board configuration file */
28/* please refer to doc/README.mpc85xx for more info */
29/* make sure you change the MAC address and other network params first,
30 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
31 */
wdenk8b74bf32004-10-11 23:10:30 +000032
wdenkc15f3122004-10-10 22:44:24 +000033#ifndef __CONFIG_H
34#define __CONFIG_H
35
36#if XXX
37#define DEBUG /* General debug */
38#define ET_DEBUG
39#endif
40#define TSEC_DEBUG
41
42/* High Level Configuration Options */
43#define CONFIG_BOOKE 1 /* BOOKE */
44#define CONFIG_E500 1 /* BOOKE e500 family */
45#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
46#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
47
48
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050049#define CONFIG_CPM2 1 /* has CPM2 */
wdenkc15f3122004-10-10 22:44:24 +000050
Wolfgang Denk53677ef2008-05-20 16:00:29 +020051#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
Kumar Galaf0600542008-06-11 00:44:10 -050052#define CONFIG_MPC8540 1
wdenkc15f3122004-10-10 22:44:24 +000053
54#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
55
56#define CONFIG_TSEC_ENET /* tsec ethernet support */
57#undef CONFIG_PCI /* pci ethernet support */
58#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
59
Kumar Galae2b159d2008-01-16 09:05:27 -060060#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenkc15f3122004-10-10 22:44:24 +000061
62#define CONFIG_ENV_OVERWRITE
63
64/* Using Localbus SDRAM to emulate flash before we can program the flash,
65 * normally you need a flash-boot image(u-boot.bin), if so undef this.
66 */
67#undef CONFIG_RAM_AS_FLASH
68
69#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
70 #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
71#else
72 #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
73#endif
74
75/* below can be toggled for performance analysis. otherwise use default */
76#define CONFIG_L2_CACHE /* toggle L2 cache */
77#undef CONFIG_BTB /* toggle branch predition */
78#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
79
80#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
81
82#undef CFG_DRAM_TEST /* memory test, takes time */
83#define CFG_MEMTEST_START 0x00200000 /* memtest region */
84#define CFG_MEMTEST_END 0x00400000
85
86#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
87 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
88 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
89#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
90#endif
91
92/*
93 * Base addresses -- Note these are effective addresses where the
94 * actual resources get mapped (not physical addresses)
95 */
96#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
97
98#if XXX
99 #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
100#else
101 #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
102#endif
Kumar Galaf69766e2008-01-30 14:55:14 -0600103#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
wdenkc15f3122004-10-10 22:44:24 +0000104#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
105
106#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
107#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
108#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
109#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
110
111#undef CONFIG_DDR_ECC /* only for ECC DDR module */
112#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
113
114#if defined(CONFIG_MPC85xx_REV1)
115 #define CONFIG_DDR_DLL /* possible DLL fix needed */
116#endif
117
118#undef CONFIG_CLOCKS_IN_MHZ
119
120#if defined(CONFIG_RAM_AS_FLASH)
121 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
122 #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
123 #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
124 #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
125#else /* Boot from real Flash */
126 #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
127 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
128 #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
129 #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
130#endif
131#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
132
133/* local bus definitions */
134#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
135#define CFG_OR1_PRELIM 0xfc000ff7
136
137#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
138#define CFG_OR2_PRELIM 0x00000000
139
140#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
141#define CFG_OR3_PRELIM 0xfc000cc1
142
143#if defined(CONFIG_RAM_AS_FLASH)
144 #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
145#else
146 #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
147#endif
148#define CFG_OR4_PRELIM 0xfc000cc1
149
150#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
151#if 1
152 #define CFG_OR5_PRELIM 0xff000ff7
153#else
154 #define CFG_OR5_PRELIM 0xff0000f0
155#endif
156
157#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
158#define CFG_OR6_PRELIM 0xfc000ff7
159#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
160#define CFG_LBC_LBCR 0x00000000
161#define CFG_LBC_LSRT 0x20000000
162#define CFG_LBC_MRTPR 0x20000000
163#define CFG_LBC_LSDMR_1 0x2861b723
164#define CFG_LBC_LSDMR_2 0x0861b723
165#define CFG_LBC_LSDMR_3 0x0861b723
166#define CFG_LBC_LSDMR_4 0x1861b723
167#define CFG_LBC_LSDMR_5 0x4061b723
168
169/* just hijack the MOT BCSR def for SBC8560 misc devices */
170#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
171/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
172
173#define CONFIG_L1_INIT_RAM
174#define CFG_INIT_RAM_LOCK 1
175#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
176#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
177
178#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
179#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
180#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
181
182#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
183#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
184
185/* Serial Port */
186#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
187#undef CONFIG_CONS_NONE /* define if console on something else */
188
189#define CONFIG_CONS_INDEX 1
190#undef CONFIG_SERIAL_SOFTWARE_FIFO
191#define CFG_NS16550
192#define CFG_NS16550_SERIAL
193#define CFG_NS16550_REG_SIZE 1
194#if 0
195#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
196#else
197#define CFG_NS16550_CLK 264000000 /* get_bus_freq(0) */
198#endif
199
200#define CONFIG_BAUDRATE 9600
201
202#define CFG_BAUDRATE_TABLE \
203 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
204
205#if 0
206#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
207#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
208#else
wdenk8b74bf32004-10-11 23:10:30 +0000209/* SBC8540 uses internal COMM controller */
wdenkc15f3122004-10-10 22:44:24 +0000210#define CFG_NS16550_COM1 ((CFG_CCSRBAR & 0xfff00000)+0x00004500)
211#define CFG_NS16550_COM2 ((CFG_CCSRBAR & 0xfff00000)+0x00004600)
212#endif
213
214/* Use the HUSH parser */
215#define CFG_HUSH_PARSER
216#ifdef CFG_HUSH_PARSER
217#define CFG_PROMPT_HUSH_PS2 "> "
218#endif
219
Jon Loeliger20476722006-10-20 15:50:15 -0500220/*
221 * I2C
222 */
223#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
224#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenkc15f3122004-10-10 22:44:24 +0000225#undef CONFIG_SOFT_I2C /* I2C bit-banged */
226#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
227#define CFG_I2C_SLAVE 0x7F
228#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500229#define CFG_I2C_OFFSET 0x3000
wdenkc15f3122004-10-10 22:44:24 +0000230
231#define CFG_PCI_MEM_BASE 0xC0000000
232#define CFG_PCI_MEM_PHYS 0xC0000000
233#define CFG_PCI_MEM_SIZE 0x10000000
234
235#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
236
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500237# define CONFIG_NET_MULTI 1
238# define CONFIG_MPC85xx_TSEC1
239# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
240# define CONFIG_MII 1 /* MII PHY management */
241# define TSEC1_PHY_ADDR 25
242# define TSEC1_PHYIDX 0
243/* Options are: TSEC0 */
244# define CONFIG_ETHPRIME "TSEC0"
wdenkc15f3122004-10-10 22:44:24 +0000245
wdenk8b74bf32004-10-11 23:10:30 +0000246
wdenkc15f3122004-10-10 22:44:24 +0000247#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
248
249 #undef CONFIG_ETHER_NONE /* define if ether on something else */
250 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
251 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk8b74bf32004-10-11 23:10:30 +0000252
wdenkc15f3122004-10-10 22:44:24 +0000253 #if (CONFIG_ETHER_INDEX == 2)
254 /*
255 * - Rx-CLK is CLK13
256 * - Tx-CLK is CLK14
257 * - Select bus for bd/buffers
258 * - Full duplex
259 */
260 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
261 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
262 #define CFG_CPMFCR_RAMTYPE 0
263 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
wdenk8b74bf32004-10-11 23:10:30 +0000264
wdenkc15f3122004-10-10 22:44:24 +0000265 #elif (CONFIG_ETHER_INDEX == 3)
266 /* need more definitions here for FE3 */
267 #endif /* CONFIG_ETHER_INDEX */
wdenk8b74bf32004-10-11 23:10:30 +0000268
wdenkc15f3122004-10-10 22:44:24 +0000269 #define CONFIG_MII /* MII PHY management */
270 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
271 /*
272 * GPIO pins used for bit-banged MII communications
273 */
274 #define MDIO_PORT 2 /* Port C */
275 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
276 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
277 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
278
279 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
280 else iop->pdat &= ~0x00400000
281
282 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
283 else iop->pdat &= ~0x00200000
284
285 #define MIIDELAY udelay(1)
wdenk8b74bf32004-10-11 23:10:30 +0000286
wdenkc15f3122004-10-10 22:44:24 +0000287#endif
288
289/*-----------------------------------------------------------------------
290 * FLASH and environment organization
291 */
292
293#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
294#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
295#if 0
296#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
297#define CFG_FLASH_PROTECTION /* use hardware protection */
298#endif
299#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
300#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
301
302#undef CFG_FLASH_CHECKSUM
303#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
304#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
305
306#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
307
308#if 0
309/* XXX This doesn't work and I don't want to fix it */
310#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
311 #define CFG_RAMBOOT
312#else
313 #undef CFG_RAMBOOT
314#endif
315#endif
316
317/* Environment */
318#if !defined(CFG_RAMBOOT)
319 #if defined(CONFIG_RAM_AS_FLASH)
320 #define CFG_ENV_IS_NOWHERE
321 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
322 #define CFG_ENV_SIZE 0x2000
323 #else
324 #define CFG_ENV_IS_IN_FLASH 1
325 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
326 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
327 #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
328 #endif
329#else
330 #define CFG_NO_FLASH 1 /* Flash is not usable now */
331 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
332 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
333 #define CFG_ENV_SIZE 0x2000
334#endif
335
336#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
337/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
338#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
339#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
340
341#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
342#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
343
Jon Loeliger2835e512007-06-13 13:22:08 -0500344
345/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500346 * BOOTP options
347 */
348#define CONFIG_BOOTP_BOOTFILESIZE
349#define CONFIG_BOOTP_BOOTPATH
350#define CONFIG_BOOTP_GATEWAY
351#define CONFIG_BOOTP_HOSTNAME
352
353
354/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500355 * Command line configuration.
356 */
357#include <config_cmd_default.h>
358
359#define CONFIG_CMD_PING
360#define CONFIG_CMD_I2C
361
362#if defined(CONFIG_PCI)
363 #define CONFIG_CMD_PCI
wdenkc15f3122004-10-10 22:44:24 +0000364#endif
365
Jon Loeliger2835e512007-06-13 13:22:08 -0500366#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
367 #define CONFIG_CMD_MII
368#endif
369
370#if defined(CFG_RAMBOOT)
371 #undef CONFIG_CMD_ENV
372 #undef CONFIG_CMD_LOADS
373#endif
374
wdenkc15f3122004-10-10 22:44:24 +0000375
376#undef CONFIG_WATCHDOG /* watchdog disabled */
377
378/*
379 * Miscellaneous configurable options
380 */
381#define CFG_LONGHELP /* undef to save memory */
382#define CFG_PROMPT "SBC8540=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500383#if defined(CONFIG_CMD_KGDB)
wdenkc15f3122004-10-10 22:44:24 +0000384 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
385#else
386 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
387#endif
388#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
389#define CFG_MAXARGS 16 /* max number of command args */
390#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
391#define CFG_LOAD_ADDR 0x1000000 /* default load address */
392#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
393
394/*
395 * For booting Linux, the board info and command line data
396 * have to be in the first 8 MB of memory, since this is
397 * the maximum mapped by the Linux kernel during initialization.
398 */
399#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
400
wdenkc15f3122004-10-10 22:44:24 +0000401/*
402 * Internal Definitions
403 *
404 * Boot Flags
405 */
406#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
407#define BOOTFLAG_WARM 0x02 /* Software reboot */
408
Jon Loeliger2835e512007-06-13 13:22:08 -0500409#if defined(CONFIG_CMD_KGDB)
wdenkc15f3122004-10-10 22:44:24 +0000410 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
411 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
412#endif
413
414/*Note: change below for your network setting!!! */
415#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
wdenke2ffd592004-12-31 09:32:47 +0000416# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
417# define CONFIG_HAS_ETH1
418# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
419# define CONFIG_HAS_ETH2
420# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
wdenkc15f3122004-10-10 22:44:24 +0000421#endif
422
423#define CONFIG_SERVERIP YourServerIP
424#define CONFIG_IPADDR YourTargetIP
425#define CONFIG_GATEWAYIP YourGatewayIP
426#define CONFIG_NETMASK 255.255.255.0
427#define CONFIG_HOSTNAME SBC8560
428#define CONFIG_ROOTPATH YourRootPath
429#define CONFIG_BOOTFILE YourImageName
430
431#endif /* __CONFIG_H */