blob: e178e3509726f3f7e86ed10e4844b3631f4fb885 [file] [log] [blame]
TsiChungLiew57a12722008-01-15 14:15:46 -06001/*
2 * Configuation settings for the Freescale MCF5485 FireEngine board.
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef _M5485EVB_H
31#define _M5485EVB_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MCF547x_8x /* define processor family */
38#define CONFIG_M548x /* define processor type */
39#define CONFIG_M5485 /* define processor type */
40
TsiChungLiew57a12722008-01-15 14:15:46 -060041#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_UART_PORT (0)
TsiChungLiew57a12722008-01-15 14:15:46 -060043#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
TsiChungLiew57a12722008-01-15 14:15:46 -060045
46#define CONFIG_HW_WATCHDOG
47#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
48
49/* Command line configuration */
50#include <config_cmd_default.h>
51
52#define CONFIG_CMD_CACHE
53#undef CONFIG_CMD_DATE
54#define CONFIG_CMD_ELF
55#define CONFIG_CMD_FLASH
56#define CONFIG_CMD_I2C
57#define CONFIG_CMD_MEMORY
58#define CONFIG_CMD_MISC
59#define CONFIG_CMD_MII
60#define CONFIG_CMD_NET
61#define CONFIG_CMD_PCI
62#define CONFIG_CMD_PING
63#define CONFIG_CMD_REGINFO
64#define CONFIG_CMD_USB
65
66#define CONFIG_SLTTMR
67
68#define CONFIG_FSLDMAFEC
69#ifdef CONFIG_FSLDMAFEC
70# define CONFIG_NET_MULTI 1
71# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050072# define CONFIG_MII_INIT 1
TsiChungLiew57a12722008-01-15 14:15:46 -060073# define CONFIG_HAS_ETH1
74
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075# define CONFIG_SYS_DMA_USE_INTSRAM 1
76# define CONFIG_SYS_DISCOVER_PHY
77# define CONFIG_SYS_RX_ETH_BUFFER 32
78# define CONFIG_SYS_TX_ETH_BUFFER 48
79# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew57a12722008-01-15 14:15:46 -060080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081# define CONFIG_SYS_FEC0_PINMUX 0
82# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
83# define CONFIG_SYS_FEC1_PINMUX 0
84# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
TsiChungLiew57a12722008-01-15 14:15:46 -060085
Wolfgang Denk53677ef2008-05-20 16:00:29 +020086# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
88# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew57a12722008-01-15 14:15:46 -060089# define FECDUPLEX FULL
90# define FECSPEED _100BASET
91# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
93# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew57a12722008-01-15 14:15:46 -060094# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew57a12722008-01-15 14:15:46 -060096
97# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
98# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
99# define CONFIG_IPADDR 192.162.1.2
100# define CONFIG_NETMASK 255.255.255.0
101# define CONFIG_SERVERIP 192.162.1.1
102# define CONFIG_GATEWAYIP 192.162.1.1
103# define CONFIG_OVERWRITE_ETHADDR_ONCE
104
105#endif
106
107#ifdef CONFIG_CMD_USB
108# define CONFIG_USB_STORAGE
109# define CONFIG_DOS_PARTITION
110# define CONFIG_USB_OHCI_NEW
111# ifndef CONFIG_CMD_PCI
112# define CONFIG_CMD_PCI
113# endif
114/*# define CONFIG_PCI_OHCI*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
116# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
117# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
118# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
TsiChungLiew57a12722008-01-15 14:15:46 -0600119#endif
120
121/* I2C */
122#define CONFIG_FSL_I2C
123#define CONFIG_HARD_I2C /* I2C with hw support */
124#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_I2C_SPEED 80000
126#define CONFIG_SYS_I2C_SLAVE 0x7F
127#define CONFIG_SYS_I2C_OFFSET 0x00008F00
128#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiew57a12722008-01-15 14:15:46 -0600129
130/* PCI */
131#ifdef CONFIG_CMD_PCI
132#define CONFIG_PCI 1
133#define CONFIG_PCI_PNP 1
TsiChung Liewf33fca22008-03-30 01:19:06 -0500134#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
TsiChungLiew57a12722008-01-15 14:15:46 -0600135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
137#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
138#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
TsiChungLiew57a12722008-01-15 14:15:46 -0600139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_PCI_IO_BUS 0x71000000
141#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
142#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
TsiChungLiew57a12722008-01-15 14:15:46 -0600143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
145#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
146#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
TsiChungLiew57a12722008-01-15 14:15:46 -0600147#endif
148
149#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
150#define CONFIG_UDP_CHECKSUM
151
152#define CONFIG_HOSTNAME M548xEVB
153#define CONFIG_EXTRA_ENV_SETTINGS \
154 "netdev=eth0\0" \
155 "loadaddr=10000\0" \
156 "u-boot=u-boot.bin\0" \
157 "load=tftp ${loadaddr) ${u-boot}\0" \
158 "upd=run load; run prog\0" \
159 "prog=prot off bank 1;" \
160 "era ff800000 ff82ffff;" \
161 "cp.b ${loadaddr} ff800000 ${filesize};"\
162 "save\0" \
163 ""
164
165#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_PROMPT "-> "
167#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiew57a12722008-01-15 14:15:46 -0600168
169#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiew57a12722008-01-15 14:15:46 -0600171#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiew57a12722008-01-15 14:15:46 -0600173#endif
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
176#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
177#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
178#define CONFIG_SYS_LOAD_ADDR 0x00010000
TsiChungLiew57a12722008-01-15 14:15:46 -0600179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_HZ 1000
181#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
182#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
TsiChungLiew57a12722008-01-15 14:15:46 -0600183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MBAR 0xF0000000
185#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
186#define CONFIG_SYS_INTSRAMSZ 0x8000
TsiChungLiew57a12722008-01-15 14:15:46 -0600187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
TsiChungLiew57a12722008-01-15 14:15:46 -0600189
190/*
191 * Low Level Configuration Settings
192 * (address mappings, register initial values, etc.)
193 * You should know what you are doing if you make changes here.
194 */
195/*-----------------------------------------------------------------------
196 * Definitions for initial stack pointer and data area (in DPRAM)
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200199#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_INIT_RAM_CTRL 0x21
Wolfgang Denk553f0982010-10-26 13:32:32 +0200201#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
203#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200204#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiew57a12722008-01-15 14:15:46 -0600206
207/*-----------------------------------------------------------------------
208 * Start addresses for the final memory configuration
209 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiew57a12722008-01-15 14:15:46 -0600211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_SDRAM_BASE 0x00000000
213#define CONFIG_SYS_SDRAM_CFG1 0x73711630
214#define CONFIG_SYS_SDRAM_CFG2 0x46770000
215#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
216#define CONFIG_SYS_SDRAM_EMOD 0x40010000
217#define CONFIG_SYS_SDRAM_MODE 0x018D0000
218#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
219#ifdef CONFIG_SYS_DRAMSZ1
220# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
TsiChungLiew57a12722008-01-15 14:15:46 -0600221#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
TsiChungLiew57a12722008-01-15 14:15:46 -0600223#endif
224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
226#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiew57a12722008-01-15 14:15:46 -0600227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
229#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiew57a12722008-01-15 14:15:46 -0600230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
232#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChungLiew57a12722008-01-15 14:15:46 -0600233
234/*
235 * For booting Linux, the board info and command line data
236 * have to be in the first 8 MB of memory, since this is
237 * the maximum mapped by the Linux kernel during initialization ??
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChungLiew57a12722008-01-15 14:15:46 -0600240
241/*-----------------------------------------------------------------------
242 * FLASH organization
243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_FLASH_CFI
245#ifdef CONFIG_SYS_FLASH_CFI
246# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200247# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
249# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
250# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
251# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
252#ifdef CONFIG_SYS_NOR1SZ
253# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
254# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
255# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
TsiChungLiew57a12722008-01-15 14:15:46 -0600256#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
258# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
TsiChungLiew57a12722008-01-15 14:15:46 -0600259#endif
260#endif
261
262/* Configuration for environment
263 * Environment is embedded in u-boot in the second sector of the flash
264 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200265#define CONFIG_ENV_OFFSET 0x2000
266#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200267#define CONFIG_ENV_IS_IN_FLASH 1
TsiChungLiew57a12722008-01-15 14:15:46 -0600268
269/*-----------------------------------------------------------------------
270 * Cache Configuration
271 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiew57a12722008-01-15 14:15:46 -0600273
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600274#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200275 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600276#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200277 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600278#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
279 CF_CACR_IDCM)
280#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
281#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
282 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
283 CF_ACR_EN | CF_ACR_SM_ALL)
284#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
285 CF_CACR_IEC | CF_CACR_ICINVA)
286#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
287 CF_CACR_DEC | CF_CACR_DDCM_P | \
288 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
289
TsiChungLiew57a12722008-01-15 14:15:46 -0600290/*-----------------------------------------------------------------------
291 * Chipselect bank definitions
292 */
293/*
294 * CS0 - NOR Flash 1, 2, 4, or 8MB
295 * CS1 - NOR Flash
296 * CS2 - Available
297 * CS3 - Available
298 * CS4 - Available
299 * CS5 - Available
300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_CS0_BASE 0xFF800000
302#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
303#define CONFIG_SYS_CS0_CTRL 0x00101980
TsiChungLiew57a12722008-01-15 14:15:46 -0600304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#ifdef CONFIG_SYS_NOR1SZ
306#define CONFIG_SYS_CS1_BASE 0xE0000000
307#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
308#define CONFIG_SYS_CS1_CTRL 0x00101D80
TsiChungLiew57a12722008-01-15 14:15:46 -0600309#endif
310
311#endif /* _M5485EVB_H */