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Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02001/*
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +01002 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02003 * wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this project.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010014 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020015 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020025/*
26 * High Level Configuration Options
27 * (easy to change)
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010028 */
29#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
30#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
31#define CONFIG_V38B 1 /* ...on V38B board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020032
33#define CONFIG_SYS_TEXT_BASE 0xFF000000
34
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020036
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010037#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
38#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020039
Bartlomiej Siekace3f1a42006-11-11 22:48:22 +010040#undef CONFIG_HW_WATCHDOG /* don't use watchdog */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020041
42#define CONFIG_NETCONSOLE 1
43
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010044#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +010045#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */
Mike Frysingerd8d21e62009-02-16 18:03:14 -050046#define CONFIG_MISC_INIT_R
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020047
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020049
Becky Bruce31d82672008-05-08 19:02:12 -050050#define CONFIG_HIGH_BATS 1 /* High BATs supported */
51
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020052/*
53 * Serial console configuration
54 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010055#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
56#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020058
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020059/*
60 * DDR
61 */
62#define SDRAM_DDR 1 /* is DDR */
63/* Settings for XLB = 132 MHz */
64#define SDRAM_MODE 0x018D0000
65#define SDRAM_EMODE 0x40090000
66#define SDRAM_CONTROL 0x704f0f00
67#define SDRAM_CONFIG1 0x73722930
68#define SDRAM_CONFIG2 0x47770000
69#define SDRAM_TAPDELAY 0x10000000
70
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020071/*
72 * PCI - no suport
73 */
74#undef CONFIG_PCI
75
76/*
77 * Partitions
78 */
79#define CONFIG_MAC_PARTITION 1
80#define CONFIG_DOS_PARTITION 1
81
82/*
83 * USB
84 */
85#define CONFIG_USB_OHCI
86#define CONFIG_USB_STORAGE
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010087#define CONFIG_USB_CLOCK 0x0001BBBB
88#define CONFIG_USB_CONFIG 0x00001000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020089
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050090
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020091/*
Jon Loeliger079a1362007-07-10 10:12:10 -050092 * BOOTP options
93 */
94#define CONFIG_BOOTP_BOOTFILESIZE
95#define CONFIG_BOOTP_BOOTPATH
96#define CONFIG_BOOTP_GATEWAY
97#define CONFIG_BOOTP_HOSTNAME
98
99
100/*
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500101 * Command line configuration.
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200102 */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500103#include <config_cmd_default.h>
104
105#define CONFIG_CMD_FAT
106#define CONFIG_CMD_I2C
107#define CONFIG_CMD_IDE
108#define CONFIG_CMD_PING
109#define CONFIG_CMD_DHCP
110#define CONFIG_CMD_DIAG
111#define CONFIG_CMD_IRQ
112#define CONFIG_CMD_JFFS2
113#define CONFIG_CMD_MII
114#define CONFIG_CMD_SDRAM
115#define CONFIG_CMD_DATE
116#define CONFIG_CMD_USB
117#define CONFIG_CMD_FAT
118
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200119
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100120#define CONFIG_TIMESTAMP /* Print image info with timestamp */
121
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200122/*
123 * Boot low with 16 MB Flash
124 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_LOWBOOT 1
126#define CONFIG_SYS_LOWBOOT16 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200127
128/*
129 * Autobooting
130 */
131#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
132
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100133#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100134 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200135 "echo"
136
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100137#undef CONFIG_BOOTARGS
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200138
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200139#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200140 "bootcmd=run net_nfs\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100141 "bootdelay=3\0" \
142 "baudrate=115200\0" \
143 "preboot=echo;echo Type \"run flash_nfs\" to mount root " \
144 "filesystem over NFS; echo\0" \
145 "netdev=eth0\0" \
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +0100146 "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200147 "addip=setenv bootargs $(bootargs) " \
148 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
149 "$(netmask):$(hostname):$(netdev):off panic=1\0" \
150 "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
151 "flash_self=run ramargs addip;bootm $(kernel_addr) " \
152 "$(ramdisk_addr)\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100153 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200154 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +0100155 "nfsroot=$(serverip):$(rootpath) wdt=off\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100156 "hostname=v38b\0" \
Heiko Schocher48690d82010-07-20 17:45:02 +0200157 "ethact=FEC\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100158 "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
159 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
160 "cp.b 200000 ff000000 $(filesize);" \
161 "prot on ff000000 ff03ffff\0" \
162 "load=tftp 200000 $(u-boot)\0" \
163 "netmask=255.255.0.0\0" \
164 "ipaddr=192.168.160.18\0" \
165 "serverip=192.168.1.1\0" \
166 "ethaddr=00:e0:ee:00:05:2e\0" \
167 "bootfile=/tftpboot/v38b/uImage\0" \
168 "u-boot=/tftpboot/v38b/u-boot.bin\0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200169 ""
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200170
171#define CONFIG_BOOTCOMMAND "run net_nfs"
172
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200173/*
174 * IPB Bus clocking configuration.
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100177
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200178/*
179 * I2C configuration
180 */
181#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
183#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
184#define CONFIG_SYS_I2C_SLAVE 0x7F
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200185
186/*
187 * EEPROM configuration
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
190#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
191#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
192#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200193
194/*
195 * RTC configuration
196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_I2C_RTC_ADDR 0x51
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200198
199/*
200 * Flash configuration - use CFI driver
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200203#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
205#define CONFIG_SYS_FLASH_BASE 0xFF000000
206#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
207#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
208#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */
209#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
210#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200211
212/*
213 * Environment settings
214 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200215#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200217#define CONFIG_ENV_SIZE 0x10000
218#define CONFIG_ENV_SECT_SIZE 0x10000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200219#define CONFIG_ENV_OVERWRITE 1
220
221/*
222 * Memory map
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MBAR 0xF0000000
225#define CONFIG_SYS_SDRAM_BASE 0x00000000
226#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200227
228/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200230#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200231
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200232#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200234
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200235#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
237# define CONFIG_SYS_RAMBOOT 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200238#endif
239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
241#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
242#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200243
244/*
245 * Ethernet configuration
246 */
247#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800248#define CONFIG_MPC5xxx_FEC_MII100
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200249#define CONFIG_PHY_ADDR 0x00
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200250#define CONFIG_MII 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200251
252/*
253 * GPIO configuration
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200256
257/*
258 * Miscellaneous configurable options
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_LONGHELP /* undef to save memory */
261#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500262#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200264#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200266#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
268#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
269#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
272#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500279#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500281#endif
282
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200283/*
284 * Various low-level settings
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
287#define CONFIG_SYS_HID0_FINAL HID0_ICE
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
290#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
291#define CONFIG_SYS_BOOTCS_CFG 0x00047801
292#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
293#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200294
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_CS_BURST 0x00000000
296#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200299
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100300/*
301 * IDE/ATA (supports IDE harddisk)
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200302 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100303#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
304#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
305#undef CONFIG_IDE_LED /* LED for ide not supported */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200306
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100307#define CONFIG_IDE_RESET /* reset for ide supported */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200308#define CONFIG_IDE_PREINIT
309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
311#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200318
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200324
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100325/*
326 * Status LED
327 */
328#define CONFIG_STATUS_LED /* Status LED enabled */
329#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200332#ifndef __ASSEMBLY__
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200333typedef unsigned int led_id_t;
334
335#define __led_toggle(_msk) \
336 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337 *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200338 } while(0)
339
340#define __led_set(_msk, _st) \
341 do { \
342 if ((_st)) \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343 *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200344 else \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200346 } while(0)
347
348#define __led_init(_msk, st) \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100349 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100351 } while(0)
352#endif /* __ASSEMBLY__ */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200353
354#endif /* __CONFIG_H */