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Matthias Fuchs8ba132c2007-12-28 17:07:24 +01001/*
Matthias Fuchs76b565b2008-10-28 13:36:58 +01002 * (C) Copyright 2007-2008
Matthias Fuchs8ba132c2007-12-28 17:07:24 +01003 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on the sequoia configuration file.
5 *
6 * (C) Copyright 2006-2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * (C) Copyright 2006
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/************************************************************************
30 * PMC440.h - configuration for esd PMC440 boards
31 ***********************************************************************/
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35/*-----------------------------------------------------------------------
36 * High Level Configuration Options
37 *----------------------------------------------------------------------*/
38#define CONFIG_440EPX 1 /* Specific PPC440EPx */
39#define CONFIG_440 1 /* ... PPC440 family */
40#define CONFIG_4xx 1 /* ... PPC4xx family */
41
42#define CONFIG_SYS_CLK_FREQ 33333400
43
Matthias Fuchsff41ffc2008-01-11 14:55:16 +010044#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010045#define CONFIG_4xx_DCACHE /* enable dcache */
Matthias Fuchsff41ffc2008-01-11 14:55:16 +010046#endif
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010047
48#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Matthias Fuchs76b565b2008-10-28 13:36:58 +010049#define CONFIG_MISC_INIT_F 1
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010050#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
51#define CONFIG_BOARD_TYPES 1 /* support board types */
52/*-----------------------------------------------------------------------
53 * Base addresses -- Note these are effective addresses where the
54 * actual resources get mapped (not physical addresses)
55 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
57#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010058
59#define CONFIG_PRAM 0 /* use pram variable to overwrite */
60
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
62#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
63#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
64#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
65#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
66#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
67#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
68#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
69#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
70#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
71#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
72#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
73#define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010074
75/* Don't change either of these */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_USB2D0_BASE 0xe0000100
79#define CONFIG_SYS_USB_DEVICE 0xe0000000
80#define CONFIG_SYS_USB_HOST 0xe0000400
81#define CONFIG_SYS_FPGA_BASE0 0xef000000 /* 32 bit */
82#define CONFIG_SYS_FPGA_BASE1 0xef100000 /* 16 bit */
Matthias Fuchs76b565b2008-10-28 13:36:58 +010083#define CONFIG_SYS_RESET_BASE 0xef200000
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010084
85/*-----------------------------------------------------------------------
86 * Initial RAM & stack pointer
87 *----------------------------------------------------------------------*/
88/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
90#define CONFIG_SYS_INIT_RAM_END (4 << 10)
91#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
92#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
93#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010094
95/*-----------------------------------------------------------------------
96 * Serial Port
97 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010099#define CONFIG_BAUDRATE 115200
100#define CONFIG_SERIAL_MULTI 1
101#undef CONFIG_UART1_CONSOLE /* console on front panel */
102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_BAUDRATE_TABLE \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100104 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
105
106/*-----------------------------------------------------------------------
107 * Environment
108 *----------------------------------------------------------------------*/
109#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200110#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100111#else
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200112#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200113#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100114#endif
115
116/*-----------------------------------------------------------------------
117 * RTC
118 *----------------------------------------------------------------------*/
119#define CONFIG_RTC_RX8025
120
121/*-----------------------------------------------------------------------
122 * FLASH related
123 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200125#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
130#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
133#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
136#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
139#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100140
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200141#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100144#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100145
146/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200147#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
148#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100149#endif
150
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200151#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200152#define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
153#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100154#endif
155
156/*
157 * IPL (Initial Program Loader, integrated inside CPU)
158 * Will load first 4k from NAND (SPL) into cache and execute it from there.
159 *
160 * SPL (Secondary Program Loader)
161 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
162 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
163 * controller and the NAND controller so that the special U-Boot image can be
164 * loaded from NAND to SDRAM.
165 *
166 * NUB (NAND U-Boot)
167 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
168 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
169 *
170 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
171 * set up. While still running from cache, I experienced problems accessing
172 * the NAND controller. sr - 2006-08-25
173 */
Matthias Fuchs7d5d7562008-01-08 11:13:09 +0100174#if defined (CONFIG_NAND_U_BOOT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
176#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
177#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
178#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
179#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
180#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100181
182/*
183 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
186#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100187
188/*
189 * Now the NAND chip has to be defined (no autodetection used!)
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
192#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
193#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
194#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
195#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_NAND_ECCSIZE 256
198#define CONFIG_SYS_NAND_ECCBYTES 3
199#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
200#define CONFIG_SYS_NAND_OOBSIZE 16
201#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
202#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
Matthias Fuchs7d5d7562008-01-08 11:13:09 +0100203#endif
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100204
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200205#ifdef CONFIG_ENV_IS_IN_NAND
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100206/*
207 * For NAND booting the environment is embedded in the U-Boot image. Please take
208 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
211#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100213#endif
214
215/*-----------------------------------------------------------------------
216 * DDR SDRAM
217 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100219#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
220#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
221#endif
Jean-Christophe PLAGNIOL-VILLARD3aed3aa2008-12-14 10:29:39 +0100222#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
223 /* 440EPx errata CHIP 11 */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100224
225/*-----------------------------------------------------------------------
226 * I2C
227 *----------------------------------------------------------------------*/
228#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
229#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100230#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_I2C_SLAVE 0x7F
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100232
233#define CONFIG_I2C_CMD_TREE 1
234#define CONFIG_I2C_MULTI_BUS 1
235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_I2C_MULTI_EEPROMS
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
239#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
240#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
241#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
242#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_EEPROM_WREN 1
245#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100246
247/*
248 * standard dtt sensor configuration - bottom bit will determine local or
249 * remote sensor of the TMP401
250 */
251#define CONFIG_DTT_SENSORS { 0, 1 }
252
253/*
254 * The PMC440 uses a TI TMP401 temperature sensor. This part
255 * is basically compatible to the ADM1021 that is supported
256 * by U-Boot.
257 *
258 * - i2c addr 0x4c
259 * - conversion rate 0x02 = 0.25 conversions/second
260 * - ALERT ouput disabled
261 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
262 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
263 */
264#define CONFIG_DTT_ADM1021
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100266
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100267#define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \
268 "\\\"painit\\\" to preboot command"
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100269
270#undef CONFIG_BOOTARGS
271
272/* Setup some board specific values for the default environment variables */
273#define CONFIG_HOSTNAME pmc440
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100274#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0"
275#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100276
277#define CONFIG_EXTRA_ENV_SETTINGS \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100278 CONFIG_SYS_BOOTFILE \
279 CONFIG_SYS_ROOTPATH \
280 "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100281 "netdev=eth0\0" \
Matthias Fuchsff41ffc2008-01-11 14:55:16 +0100282 "ethrotate=no\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100283 "nfsargs=setenv bootargs root=/dev/nfs rw " \
284 "nfsroot=${serverip}:${rootpath}\0" \
285 "ramargs=setenv bootargs root=/dev/ram rw\0" \
286 "addip=setenv bootargs ${bootargs} " \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100287 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
288 ":${hostname}:${netdev}:off panic=1\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100289 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100290 "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
291 "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
292 "nand_boot=run nandargs addip addtty addmisc;bootm ${kernel_addr}\0" \
293 "nand_boot_fdt=run nandargs addip addtty addmisc;" \
294 "bootm ${kernel_addr} - ${fdt_addr}\0" \
295 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
296 "run nfsargs addip addtty addmisc;" \
297 "bootm\0" \
298 "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \
299 "tftp ${fdt_addr_r} ${fdt_file};" \
300 "run nfsargs addip addtty addmisc;" \
301 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
302 "kernel_addr=ffc00000\0" \
303 "kernel_addr_r=200000\0" \
304 "fpga_addr=fff00000\0" \
305 "fdt_addr=fff80000\0" \
306 "fdt_addr_r=800000\0" \
307 "fpga=fpga loadb 0 ${fpga_addr}\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100308 "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100309 "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
310 "cp.b 200000 fffa0000 60000\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100311 ""
312
313#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
314
315#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100317
Ben Warren96e21f82008-10-27 23:50:15 -0700318#define CONFIG_PPC4xx_EMAC
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100319#define CONFIG_IBM_EMAC4_V4 1
320#define CONFIG_MII 1 /* MII PHY management */
321#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
322
323#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
324
325#define CONFIG_HAS_ETH0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100327
328#define CONFIG_NET_MULTI 1
329#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
330#define CONFIG_PHY1_ADDR 1
331#define CONFIG_RESET_PHY_R 1
332
333/* USB */
334#define CONFIG_USB_OHCI_NEW
335#define CONFIG_USB_STORAGE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_OHCI_BE_CONTROLLER
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
339#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
340#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
341#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
342#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100343
344/* Comment this out to enable USB 1.1 device */
345#define USB_2_0_DEVICE
346
347/* Partitions */
348#define CONFIG_MAC_PARTITION
349#define CONFIG_DOS_PARTITION
350#define CONFIG_ISO_PARTITION
351
352#include <config_cmd_default.h>
353
354#define CONFIG_CMD_BSP
355#define CONFIG_CMD_DATE
356#define CONFIG_CMD_ASKENV
357#define CONFIG_CMD_DHCP
358#define CONFIG_CMD_DTT
359#define CONFIG_CMD_DIAG
360#define CONFIG_CMD_EEPROM
361#define CONFIG_CMD_ELF
362#define CONFIG_CMD_FAT
363#define CONFIG_CMD_I2C
364#define CONFIG_CMD_IRQ
365#define CONFIG_CMD_MII
366#define CONFIG_CMD_NAND
367#define CONFIG_CMD_NET
368#define CONFIG_CMD_NFS
369#define CONFIG_CMD_PCI
370#define CONFIG_CMD_PING
371#define CONFIG_CMD_USB
372#define CONFIG_CMD_REGINFO
373#define CONFIG_CMD_SDRAM
374
375/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
377 CONFIG_SYS_POST_CPU | \
378 CONFIG_SYS_POST_UART | \
379 CONFIG_SYS_POST_I2C | \
380 CONFIG_SYS_POST_CACHE | \
381 CONFIG_SYS_POST_FPU | \
382 CONFIG_SYS_POST_ETHER | \
383 CONFIG_SYS_POST_SPR)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100384
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100386#define CONFIG_LOGBUFFER
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100387#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100388
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100390
391#define CONFIG_SUPPORT_VFAT
392
393/*-----------------------------------------------------------------------
394 * Miscellaneous configurable options
395 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_LONGHELP /* undef to save memory */
397#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Stefan Roesebe88b162008-01-17 07:50:17 +0100398#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100400#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100402#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
404#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
405#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
408#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100409
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
411#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100412
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100414
415#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
416#define CONFIG_LOOPW 1 /* enable loopw command */
417#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
418#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
419#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
420
421#define CONFIG_AUTOBOOT_KEYED 1
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200422#define CONFIG_AUTOBOOT_PROMPT \
423 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100424#undef CONFIG_AUTOBOOT_DELAY_STR
425#define CONFIG_AUTOBOOT_STOP_STR " "
426
427/*-----------------------------------------------------------------------
428 * PCI stuff
429 *----------------------------------------------------------------------*/
430/* General PCI */
431#define CONFIG_PCI /* include pci support */
432#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100434#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100436
437/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_PCI_TARGET_INIT
439#define CONFIG_SYS_PCI_MASTER_INIT
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100440
441/* PCI identification */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
443#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
444#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
445#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
446#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100447
448/*
449 * For booting Linux, the board info and command line data
450 * have to be in the first 8 MB of memory, since this is
451 * the maximum mapped by the Linux kernel during initialization.
452 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100454
455/*-----------------------------------------------------------------------
456 * FPGA stuff
457 *----------------------------------------------------------------------*/
458#define CONFIG_FPGA
459#define CONFIG_FPGA_XILINX
460#define CONFIG_FPGA_SPARTAN2
461#define CONFIG_FPGA_SPARTAN3
462
463#define CONFIG_FPGA_COUNT 2
464/*-----------------------------------------------------------------------
465 * External Bus Controller (EBC) Setup
466 *----------------------------------------------------------------------*/
467
468/*
469 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
470 */
471#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100473
474/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_EBC_PB0AP 0x03017200
476#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100477
478/* Memory Bank 2 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_EBC_PB2AP 0x018003c0
480#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100481#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100483/* Memory Bank 2 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_EBC_PB2AP 0x03017200
485#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100486
487/* Memory Bank 0 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_EBC_PB0AP 0x018003c0
489#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100490#endif
491
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100492/* Memory Bank 1 (RESET) initialization */
Wolfgang Denk455ae7e2008-12-16 01:02:17 +0100493#define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */
Jean-Christophe PLAGNIOL-VILLARD3aed3aa2008-12-14 10:29:39 +0100494#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100495
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100496/* Memory Bank 4 (FPGA / 32Bit) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
498#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100499
500/* Memory Bank 5 (FPGA / 16Bit) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
502#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100503
504/*-----------------------------------------------------------------------
505 * NAND FLASH
506 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_MAX_NAND_DEVICE 1
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100508#define NAND_MAX_CHIPS 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
510#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
511#define CONFIG_SYS_NAND_QUIET_TEST 1
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100512
513/*
514 * Internal Definitions
515 *
516 * Boot Flags
517 */
518#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
519#define BOOTFLAG_WARM 0x02 /* Software reboot */
520
Stefan Roesebe88b162008-01-17 07:50:17 +0100521#if defined(CONFIG_CMD_KGDB)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100522#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
523#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
524#endif
525
526/* pass open firmware flat tree */
527#define CONFIG_OF_LIBFDT 1
528#define CONFIG_OF_BOARD_SETUP 1
529
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100530#define CONFIG_API 1
531
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100532#endif /* __CONFIG_H */