wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004 Freescale Semiconductor. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 23 | #include <common.h> |
| 24 | #include <pci.h> |
| 25 | #include <asm/processor.h> |
| 26 | #include <asm/immap_85xx.h> |
| 27 | #include <spd.h> |
| 28 | |
| 29 | #include "../common/cadmus.h" |
| 30 | #include "../common/eeprom.h" |
| 31 | |
| 32 | #if defined(CONFIG_DDR_ECC) |
| 33 | extern void ddr_enable_ecc(unsigned int dram_size); |
| 34 | #endif |
| 35 | |
| 36 | extern long int spd_sdram(void); |
| 37 | |
| 38 | void local_bus_init(void); |
| 39 | void sdram_init(void); |
| 40 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 41 | int board_early_init_f (void) |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 42 | { |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 43 | return 0; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 44 | } |
| 45 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 46 | int checkboard (void) |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 47 | { |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 48 | volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; |
| 49 | volatile ccsr_gur_t *gur = &immap->im_gur; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 50 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 51 | /* PCI slot in USER bits CSR[6:7] by convention. */ |
| 52 | uint pci_slot = get_pci_slot (); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 53 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 54 | uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ |
| 55 | uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ |
| 56 | uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ |
| 57 | uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 58 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 59 | uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 60 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 61 | uint cpu_board_rev = get_cpu_board_revision (); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 62 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 63 | printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", |
| 64 | get_board_version (), pci_slot); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 65 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 66 | printf ("CPU Board Revision %d.%d (0x%04x)\n", |
| 67 | MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), |
| 68 | MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 69 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 70 | printf (" PCI1: %d bit, %s MHz, %s\n", |
| 71 | (pci1_32) ? 32 : 64, |
| 72 | (pci1_speed == 33000000) ? "33" : |
| 73 | (pci1_speed == 66000000) ? "66" : "unknown", |
| 74 | pci1_clk_sel ? "sync" : "async"); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 75 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 76 | if (pci_dual) { |
| 77 | printf (" PCI2: 32 bit, 66 MHz, %s\n", |
| 78 | pci2_clk_sel ? "sync" : "async"); |
| 79 | } else { |
| 80 | printf (" PCI2: disabled\n"); |
| 81 | } |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 82 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 83 | /* |
| 84 | * Initialize local bus. |
| 85 | */ |
| 86 | local_bus_init (); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 87 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame^] | 88 | return 0; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 89 | } |
| 90 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 91 | long int |
| 92 | initdram(int board_type) |
| 93 | { |
| 94 | long dram_size = 0; |
| 95 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 96 | |
| 97 | puts("Initializing\n"); |
| 98 | |
| 99 | #if defined(CONFIG_DDR_DLL) |
| 100 | { |
| 101 | /* |
| 102 | * Work around to stabilize DDR DLL MSYNC_IN. |
| 103 | * Errata DDR9 seems to have been fixed. |
| 104 | * This is now the workaround for Errata DDR11: |
| 105 | * Override DLL = 1, Course Adj = 1, Tap Select = 0 |
| 106 | */ |
| 107 | |
| 108 | volatile ccsr_gur_t *gur= &immap->im_gur; |
| 109 | |
| 110 | gur->ddrdllcr = 0x81000000; |
| 111 | asm("sync;isync;msync"); |
| 112 | udelay(200); |
| 113 | } |
| 114 | #endif |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 115 | dram_size = spd_sdram(); |
| 116 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 117 | #if defined(CONFIG_DDR_ECC) |
| 118 | /* |
| 119 | * Initialize and enable DDR ECC. |
| 120 | */ |
| 121 | ddr_enable_ecc(dram_size); |
| 122 | #endif |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 123 | /* |
| 124 | * SDRAM Initialization |
| 125 | */ |
| 126 | sdram_init(); |
| 127 | |
| 128 | puts(" DDR: "); |
| 129 | return dram_size; |
| 130 | } |
| 131 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 132 | /* |
| 133 | * Initialize Local Bus |
| 134 | */ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 135 | void |
| 136 | local_bus_init(void) |
| 137 | { |
| 138 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 139 | volatile ccsr_gur_t *gur = &immap->im_gur; |
| 140 | volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
| 141 | |
| 142 | uint clkdiv; |
| 143 | uint lbc_hz; |
| 144 | sys_info_t sysinfo; |
| 145 | uint temp_lbcdll; |
| 146 | |
| 147 | /* |
| 148 | * Errata LBC11. |
| 149 | * Fix Local Bus clock glitch when DLL is enabled. |
| 150 | * |
| 151 | * If localbus freq is < 66Mhz, DLL bypass mode must be used. |
| 152 | * If localbus freq is > 133Mhz, DLL can be safely enabled. |
| 153 | * Between 66 and 133, the DLL is enabled with an override workaround. |
| 154 | */ |
| 155 | |
| 156 | get_sys_info(&sysinfo); |
| 157 | clkdiv = lbc->lcrr & 0x0f; |
| 158 | lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
| 159 | |
| 160 | if (lbc_hz < 66) { |
| 161 | lbc->lcrr |= 0x80000000; /* DLL Bypass */ |
| 162 | |
| 163 | } else if (lbc_hz >= 133) { |
| 164 | lbc->lcrr &= (~0x80000000); /* DLL Enabled */ |
| 165 | |
| 166 | } else { |
| 167 | lbc->lcrr &= (~0x8000000); /* DLL Enabled */ |
| 168 | udelay(200); |
| 169 | |
| 170 | /* |
| 171 | * Sample LBC DLL ctrl reg, upshift it to set the |
| 172 | * override bits. |
| 173 | */ |
| 174 | temp_lbcdll = gur->lbcdllcr; |
| 175 | gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
| 176 | asm("sync;isync;msync"); |
| 177 | } |
| 178 | } |
| 179 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 180 | /* |
| 181 | * Initialize SDRAM memory on the Local Bus. |
| 182 | */ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 183 | void |
| 184 | sdram_init(void) |
| 185 | { |
| 186 | #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) |
| 187 | |
| 188 | uint idx; |
| 189 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 190 | volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
| 191 | uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; |
| 192 | uint cpu_board_rev; |
| 193 | uint lsdmr_common; |
| 194 | |
| 195 | puts(" SDRAM: "); |
| 196 | |
| 197 | print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
| 198 | |
| 199 | /* |
| 200 | * Setup SDRAM Base and Option Registers |
| 201 | */ |
| 202 | lbc->or2 = CFG_OR2_PRELIM; |
| 203 | asm("msync"); |
| 204 | |
| 205 | lbc->br2 = CFG_BR2_PRELIM; |
| 206 | asm("msync"); |
| 207 | |
| 208 | lbc->lbcr = CFG_LBC_LBCR; |
| 209 | asm("msync"); |
| 210 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 211 | lbc->lsrt = CFG_LBC_LSRT; |
| 212 | lbc->mrtpr = CFG_LBC_MRTPR; |
| 213 | asm("msync"); |
| 214 | |
| 215 | /* |
| 216 | * Determine which address lines to use baed on CPU board rev. |
| 217 | */ |
| 218 | cpu_board_rev = get_cpu_board_revision(); |
| 219 | lsdmr_common = CFG_LBC_LSDMR_COMMON; |
| 220 | if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { |
| 221 | lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; |
| 222 | } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { |
| 223 | lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; |
| 224 | } else { |
| 225 | /* |
| 226 | * Assume something unable to identify itself is |
| 227 | * really old, and likely has lines 16/17 mapped. |
| 228 | */ |
| 229 | lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; |
| 230 | } |
| 231 | |
| 232 | /* |
| 233 | * Issue PRECHARGE ALL command. |
| 234 | */ |
| 235 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; |
| 236 | asm("sync;msync"); |
| 237 | *sdram_addr = 0xff; |
| 238 | ppcDcbf((unsigned long) sdram_addr); |
| 239 | udelay(100); |
| 240 | |
| 241 | /* |
| 242 | * Issue 8 AUTO REFRESH commands. |
| 243 | */ |
| 244 | for (idx = 0; idx < 8; idx++) { |
| 245 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; |
| 246 | asm("sync;msync"); |
| 247 | *sdram_addr = 0xff; |
| 248 | ppcDcbf((unsigned long) sdram_addr); |
| 249 | udelay(100); |
| 250 | } |
| 251 | |
| 252 | /* |
| 253 | * Issue 8 MODE-set command. |
| 254 | */ |
| 255 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; |
| 256 | asm("sync;msync"); |
| 257 | *sdram_addr = 0xff; |
| 258 | ppcDcbf((unsigned long) sdram_addr); |
| 259 | udelay(100); |
| 260 | |
| 261 | /* |
| 262 | * Issue NORMAL OP command. |
| 263 | */ |
| 264 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; |
| 265 | asm("sync;msync"); |
| 266 | *sdram_addr = 0xff; |
| 267 | ppcDcbf((unsigned long) sdram_addr); |
| 268 | udelay(200); /* Overkill. Must wait > 200 bus cycles */ |
| 269 | |
| 270 | #endif /* enable SDRAM init */ |
| 271 | } |
| 272 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 273 | #if defined(CFG_DRAM_TEST) |
| 274 | int |
| 275 | testdram(void) |
| 276 | { |
| 277 | uint *pstart = (uint *) CFG_MEMTEST_START; |
| 278 | uint *pend = (uint *) CFG_MEMTEST_END; |
| 279 | uint *p; |
| 280 | |
| 281 | printf("Testing DRAM from 0x%08x to 0x%08x\n", |
| 282 | CFG_MEMTEST_START, |
| 283 | CFG_MEMTEST_END); |
| 284 | |
| 285 | printf("DRAM test phase 1:\n"); |
| 286 | for (p = pstart; p < pend; p++) |
| 287 | *p = 0xaaaaaaaa; |
| 288 | |
| 289 | for (p = pstart; p < pend; p++) { |
| 290 | if (*p != 0xaaaaaaaa) { |
| 291 | printf ("DRAM test fails at: %08x\n", (uint) p); |
| 292 | return 1; |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | printf("DRAM test phase 2:\n"); |
| 297 | for (p = pstart; p < pend; p++) |
| 298 | *p = 0x55555555; |
| 299 | |
| 300 | for (p = pstart; p < pend; p++) { |
| 301 | if (*p != 0x55555555) { |
| 302 | printf ("DRAM test fails at: %08x\n", (uint) p); |
| 303 | return 1; |
| 304 | } |
| 305 | } |
| 306 | |
| 307 | printf("DRAM test passed.\n"); |
| 308 | return 0; |
| 309 | } |
| 310 | #endif |
| 311 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 312 | #if defined(CONFIG_PCI) |
| 313 | |
| 314 | /* |
| 315 | * Initialize PCI Devices, report devices found. |
| 316 | */ |
| 317 | |
| 318 | #ifndef CONFIG_PCI_PNP |
| 319 | static struct pci_config_table pci_mpc85xxcds_config_table[] = { |
| 320 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 321 | PCI_IDSEL_NUMBER, PCI_ANY_ID, |
| 322 | pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
| 323 | PCI_ENET0_MEMADDR, |
| 324 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
| 325 | } }, |
| 326 | { } |
| 327 | }; |
| 328 | #endif |
| 329 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 330 | static struct pci_controller hose = { |
| 331 | #ifndef CONFIG_PCI_PNP |
| 332 | config_table: pci_mpc85xxcds_config_table, |
| 333 | #endif |
| 334 | }; |
| 335 | |
| 336 | #endif /* CONFIG_PCI */ |
| 337 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 338 | void |
| 339 | pci_init_board(void) |
| 340 | { |
| 341 | #ifdef CONFIG_PCI |
| 342 | extern void pci_mpc85xx_init(struct pci_controller *hose); |
| 343 | |
| 344 | pci_mpc85xx_init(&hose); |
| 345 | #endif |
| 346 | } |