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wdenk03329902003-06-20 22:36:30 +00001/*
2 * (C) Copyright 2001, 2002, 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk03329902003-06-20 22:36:30 +00006 */
7
8/* ------------------------------------------------------------------------- */
9/*
10 * Configuration settings for the A-3000 board (Artis Microsystems Inc.).
11 * http://artismicro.com
12 */
13
14/* ------------------------------------------------------------------------- */
15
16/*
17 * board/config.h - configuration options, board specific
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
24 * High Level Configuration Options
25 * (easy to change)
26 */
27
wdenk03329902003-06-20 22:36:30 +000028#define CONFIG_MPC8245 1
29#define CONFIG_A3000 1
30
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031#define CONFIG_SYS_TEXT_BASE 0xFFF00000
wdenk03329902003-06-20 22:36:30 +000032
33#define CONFIG_CONS_INDEX 1
34#define CONFIG_BAUDRATE 9600
wdenk03329902003-06-20 22:36:30 +000035
36#define CONFIG_BOOTDELAY 5
37
wdenk03329902003-06-20 22:36:30 +000038
Jon Loeliger498ff9a2007-07-05 19:13:52 -050039/*
Jon Loeliger11799432007-07-10 09:02:57 -050040 * BOOTP options
41 */
42#define CONFIG_BOOTP_BOOTFILESIZE
43#define CONFIG_BOOTP_BOOTPATH
44#define CONFIG_BOOTP_GATEWAY
45#define CONFIG_BOOTP_HOSTNAME
46
47
48/*
Jon Loeliger498ff9a2007-07-05 19:13:52 -050049 * Command line configuration.
50 */
51#include <config_cmd_default.h>
wdenk03329902003-06-20 22:36:30 +000052
53
54/*
55 * Miscellaneous configurable options
56 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#undef CONFIG_SYS_LONGHELP /* undef to save memory */
58#define CONFIG_SYS_PROMPT "A3000> " /* Monitor Command Prompt */
59#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk03329902003-06-20 22:36:30 +000060
61/* Print Buffer Size
62 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
64#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
65#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
66#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* Default load address */
wdenk03329902003-06-20 22:36:30 +000067
68/*-----------------------------------------------------------------------
69 * PCI stuff
70 *-----------------------------------------------------------------------
71 */
Heiko Schocherea818db2013-01-29 08:53:15 +010072#define CONFIG_HARD_I2C 1 /* To enable I2C support */
73#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
75#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk03329902003-06-20 22:36:30 +000076
77/*-----------------------------------------------------------------------
78 * PCI stuff
79 *-----------------------------------------------------------------------
80 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020081#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +000082#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020083#undef CONFIG_PCI_PNP
84#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenk03329902003-06-20 22:36:30 +000085
wdenk03329902003-06-20 22:36:30 +000086
87/* #define CONFIG_TULIP */
88/* #define CONFIG_EEPRO100 */
wdenk8bde7f72003-06-27 21:31:46 +000089#define CONFIG_NATSEMI
wdenk03329902003-06-20 22:36:30 +000090
91#define PCI_ENET0_IOADDR 0x80000000
92#define PCI_ENET0_MEMADDR 0x80000000
93#define PCI_ENET1_IOADDR 0x81000000
94#define PCI_ENET1_MEMADDR 0x81000000
95#define PCI_ENET2_IOADDR 0x82000000
96#define PCI_ENET2_MEMADDR 0x82000000
wdenk8564acf2003-07-14 22:13:32 +000097#define PCI_ENET3_IOADDR 0x83000000
98#define PCI_ENET3_MEMADDR 0x83000000
wdenk03329902003-06-20 22:36:30 +000099
100
101/*-----------------------------------------------------------------------
102 * Start addresses for the final memory configuration
103 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk03329902003-06-20 22:36:30 +0000105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenk03329902003-06-20 22:36:30 +0000107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */
109#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
110#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM
111#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM }
wdenk03329902003-06-20 22:36:30 +0000112
113/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
114 * reset vector is actually located at FFB00100, but the 8245
115 * takes care of us.
116 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenk03329902003-06-20 22:36:30 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenk03329902003-06-20 22:36:30 +0000120
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200121#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
123#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk03329902003-06-20 22:36:30 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
126#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenk03329902003-06-20 22:36:30 +0000127
128 /* Maximum amount of RAM.
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */
wdenk03329902003-06-20 22:36:30 +0000131
132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
134#undef CONFIG_SYS_RAMBOOT
wdenk03329902003-06-20 22:36:30 +0000135#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_RAMBOOT
wdenk03329902003-06-20 22:36:30 +0000137#endif
138
139/*
140 * NS16550 Configuration
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_NS16550
143#define CONFIG_SYS_NS16550_SERIAL
wdenk03329902003-06-20 22:36:30 +0000144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk03329902003-06-20 22:36:30 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03329902003-06-20 22:36:30 +0000148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
150#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
wdenk03329902003-06-20 22:36:30 +0000151
152/*-----------------------------------------------------------------------
153 * Definitions for initial stack pointer and data area
154 */
155
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200156/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200158#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200159#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk03329902003-06-20 22:36:30 +0000160
161
162/*
163 * Low Level Configuration Settings
164 * (address mappings, register initial values, etc.)
165 * You should know what you are doing if you make changes here.
166 * For the detail description refer to the MPC8240 user's manual.
167 */
168
169#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenk03329902003-06-20 22:36:30 +0000170
171 /* Bit-field values for MCCR1.
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_ROMNAL 7
174#define CONFIG_SYS_ROMFAL 11
175#define CONFIG_SYS_DBUS_SIZE 0x3
wdenk03329902003-06-20 22:36:30 +0000176
177 /* Bit-field values for MCCR2.
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
180#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
wdenk03329902003-06-20 22:36:30 +0000181
182 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_BSTOPRE 121
wdenk03329902003-06-20 22:36:30 +0000185
186 /* Bit-field values for MCCR3.
187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
wdenk03329902003-06-20 22:36:30 +0000189
190 /* Bit-field values for MCCR4.
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */
193#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
194#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */
195#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
196#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
197#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
198#define CONFIG_SYS_EXTROM 1
199#define CONFIG_SYS_REGDIMM 0
wdenk03329902003-06-20 22:36:30 +0000200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
wdenk03329902003-06-20 22:36:30 +0000202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
wdenk03329902003-06-20 22:36:30 +0000204
205/* Memory bank settings.
206 * Only bits 20-29 are actually used from these vales to set the
207 * start/end addresses. The upper two bits will always be 0, and the lower
208 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
209 * address. Refer to the MPC8240 book.
210 */
211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_BANK0_START 0x00000000
213#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
214#define CONFIG_SYS_BANK0_ENABLE 1
215#define CONFIG_SYS_BANK1_START 0x3ff00000
216#define CONFIG_SYS_BANK1_END 0x3fffffff
217#define CONFIG_SYS_BANK1_ENABLE 0
218#define CONFIG_SYS_BANK2_START 0x3ff00000
219#define CONFIG_SYS_BANK2_END 0x3fffffff
220#define CONFIG_SYS_BANK2_ENABLE 0
221#define CONFIG_SYS_BANK3_START 0x3ff00000
222#define CONFIG_SYS_BANK3_END 0x3fffffff
223#define CONFIG_SYS_BANK3_ENABLE 0
224#define CONFIG_SYS_BANK4_START 0x3ff00000
225#define CONFIG_SYS_BANK4_END 0x3fffffff
226#define CONFIG_SYS_BANK4_ENABLE 0
227#define CONFIG_SYS_BANK5_START 0x3ff00000
228#define CONFIG_SYS_BANK5_END 0x3fffffff
229#define CONFIG_SYS_BANK5_ENABLE 0
230#define CONFIG_SYS_BANK6_START 0x3ff00000
231#define CONFIG_SYS_BANK6_END 0x3fffffff
232#define CONFIG_SYS_BANK6_ENABLE 0
233#define CONFIG_SYS_BANK7_START 0x3ff00000
234#define CONFIG_SYS_BANK7_END 0x3fffffff
235#define CONFIG_SYS_BANK7_ENABLE 0
wdenk03329902003-06-20 22:36:30 +0000236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_ODCR 0xff
wdenk03329902003-06-20 22:36:30 +0000238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
240#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk03329902003-06-20 22:36:30 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
243#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenk03329902003-06-20 22:36:30 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
246#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk03329902003-06-20 22:36:30 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
249#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk03329902003-06-20 22:36:30 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
252#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
253#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
254#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
255#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
256#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
257#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
258#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenk03329902003-06-20 22:36:30 +0000259
260/*
261 * For booting Linux, the board info and command line data
262 * have to be in the first 8 MB of memory, since this is
263 * the maximum mapped by the Linux kernel during initialization.
264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk03329902003-06-20 22:36:30 +0000266
267/*-----------------------------------------------------------------------
268 * FLASH organization
269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
271#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors per flash */
wdenk03329902003-06-20 22:36:30 +0000272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
274#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk03329902003-06-20 22:36:30 +0000275
276
277 /* Warining: environment is not EMBEDDED in the U-Boot code.
278 * It's stored in flash separately.
279 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200280#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200281#define CONFIG_ENV_ADDR 0xFFFE0000
282#define CONFIG_ENV_SIZE 0x00020000 /* Size of the Environment */
283#define CONFIG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */
wdenk03329902003-06-20 22:36:30 +0000284
285/*-----------------------------------------------------------------------
286 * Cache Configuration
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500289#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk03329902003-06-20 22:36:30 +0000291#endif
292
wdenk03329902003-06-20 22:36:30 +0000293#endif /* __CONFIG_H */