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Chin Liang Seec5c1af22013-12-30 18:26:14 -06001
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3SOCFPGA Documentation for U-Boot and SPL
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5
6This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
7based SOCFPGA. To know more about the hardware itself, please refer to
8www.altera.com.
9
10
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12socfpga_dw_mmc
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14Here are macro and detailed configuration required to enable DesignWare SDMMC
15controller support within SOCFPGA
16
17#define CONFIG_MMC
18-> To enable the SD MMC framework support
19
20#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS)
21-> The base address of CSR register for DesignWare SDMMC controller
22
23#define CONFIG_GENERIC_MMC
24-> Enable the generic MMC driver
25
26#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
27-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
28
29#define CONFIG_DWMMC
30-> Enable the common DesignWare SDMMC controller framework
31
32#define CONFIG_SOCFPGA_DWMMC
33-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller
34
35#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
36-> The FIFO depth for SOCFPGA DesignWare SDMMC controller
37
38#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
39-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to
40the card to meet hold time requirements. SD clock is running at 50MHz and
41drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time
42is 135 / 360 * 20ns = 7.5ns.
43
44#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
45-> Phase-shifted clock of sdmmc_clk used to sample the command and data from
46the card
47
48#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4
49-> Bus width of data line which either 1, 4 or 8 and based on board routing.
50
51#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000
52-> The clock rate to controller. Do note the controller have a wrapper which
53divide the clock from PLL by 4.