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Igor Grinbergb09bf722014-11-05 14:25:35 +02001/*
2 * (C) Copyright 2013 CompuLab, Ltd.
3 * Author: Igor Grinberg <grinberg@compulab.co.il>
4 *
5 * Configuration settings for the CompuLab CM-T3517 board
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * High Level Configuration Options
15 */
16#define CONFIG_OMAP /* in a TI OMAP core */
17#define CONFIG_CM_T3517 /* working with CM-T3517 */
18#define CONFIG_OMAP_COMMON
Nishanth Menonc6f90e12015-03-09 17:12:08 -050019/* Common ARM Erratas */
20#define CONFIG_ARM_ERRATA_454179
21#define CONFIG_ARM_ERRATA_430973
22#define CONFIG_ARM_ERRATA_621766
Igor Grinbergb09bf722014-11-05 14:25:35 +020023
24#define CONFIG_SYS_TEXT_BASE 0x80008000
25
26/*
27 * This is needed for the DMA stuff.
28 * Although the default iss 64, we still define it
29 * to be on the safe side once the default is changed.
30 */
Igor Grinbergb09bf722014-11-05 14:25:35 +020031
32#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
33
34#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menon987ec582015-03-09 17:12:04 -050035#include <asm/arch/omap.h>
Igor Grinbergb09bf722014-11-05 14:25:35 +020036
Dmitry Lifshitzf3b44e82015-09-09 11:27:17 +030037#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
38
Igor Grinbergb09bf722014-11-05 14:25:35 +020039/* Clock Defines */
40#define V_OSCK 26000000 /* Clock output from T2 */
41#define V_SCLK (V_OSCK >> 1)
42
43#define CONFIG_MISC_INIT_R
44
Igor Grinbergb09bf722014-11-05 14:25:35 +020045/*
46 * The early kernel mapping on ARM currently only maps from the base of DRAM
47 * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
48 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
49 * so that leaves DRAM base to DRAM base + 0x4000 available.
50 */
51#define CONFIG_SYS_BOOTMAPSZ 0x4000
52
53#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
54#define CONFIG_SETUP_MEMORY_TAGS
55#define CONFIG_INITRD_TAG
56#define CONFIG_REVISION_TAG
57#define CONFIG_SERIAL_TAG
58
59/*
60 * Size of malloc() pool
61 */
Dmitry Lifshitz2f6e4bf2015-09-09 11:25:39 +030062#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Igor Grinbergb09bf722014-11-05 14:25:35 +020063#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
64
65/*
66 * Hardware drivers
67 */
68
69/*
70 * NS16550 Configuration
71 */
Igor Grinbergb09bf722014-11-05 14:25:35 +020072#define CONFIG_SYS_NS16550_SERIAL
73#define CONFIG_SYS_NS16550_REG_SIZE (-4)
74#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
75
76/*
77 * select serial console configuration
78 */
79#define CONFIG_CONS_INDEX 3
80#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
81#define CONFIG_SERIAL3 3 /* UART3 */
82#define CONFIG_SYS_CONSOLE_IS_IN_ENV
83
84/* allow to overwrite serial and ethaddr */
85#define CONFIG_ENV_OVERWRITE
86#define CONFIG_BAUDRATE 115200
87#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
88 115200}
89
90#define CONFIG_OMAP_GPIO
91
92#define CONFIG_GENERIC_MMC
93#define CONFIG_MMC
94#define CONFIG_OMAP_HSMMC
95#define CONFIG_DOS_PARTITION
96
Igor Grinberg011f5c12014-11-03 11:32:25 +020097/* USB */
98#define CONFIG_USB_MUSB_AM35X
99
100#ifndef CONFIG_USB_MUSB_AM35X
101#define CONFIG_USB_OMAP3
102#define CONFIG_USB_EHCI
103#define CONFIG_USB_EHCI_OMAP
104#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
105#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
106#else /* !CONFIG_USB_MUSB_AM35X */
Paul Kocialkowski95de1e22015-08-04 17:04:06 +0200107#define CONFIG_USB_MUSB_PIO_ONLY
Igor Grinberg011f5c12014-11-03 11:32:25 +0200108#endif /* CONFIG_USB_MUSB_AM35X */
109
Igor Grinbergb09bf722014-11-05 14:25:35 +0200110/* commands to include */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200111#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
112#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
113#define CONFIG_MTD_PARTITIONS
114#define MTDIDS_DEFAULT "nand0=nand"
115#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
116 "1920k(u-boot),256k(u-boot-env),"\
117 "4m(kernel),-(fs)"
118
Igor Grinbergb09bf722014-11-05 14:25:35 +0200119#define CONFIG_CMD_NAND /* NAND support */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200120
Igor Grinbergb09bf722014-11-05 14:25:35 +0200121#define CONFIG_SYS_NO_FLASH
122#define CONFIG_SYS_I2C
123#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
124#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
125#define CONFIG_SYS_I2C_OMAP34XX
126#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
127#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
128#define CONFIG_SYS_I2C_EEPROM_BUS 0
129#define CONFIG_I2C_MULTI_BUS
130
131/*
132 * Board NAND Info.
133 */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200134#define CONFIG_NAND_OMAP_GPMC
135#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
136 /* to access nand */
137#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
138 /* to access nand at */
139 /* CS0 */
140#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
141 /* devices */
142
143/* Environment information */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200144#define CONFIG_EXTRA_ENV_SETTINGS \
145 "loadaddr=0x82000000\0" \
146 "baudrate=115200\0" \
147 "console=ttyO2,115200n8\0" \
Dmitry Lifshitze093d0b2015-09-08 09:50:00 +0300148 "netretry=yes\0" \
Igor Grinbergb09bf722014-11-05 14:25:35 +0200149 "mpurate=auto\0" \
150 "vram=12M\0" \
151 "dvimode=1024x768MR-16@60\0" \
152 "defaultdisplay=dvi\0" \
153 "mmcdev=0\0" \
154 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
155 "mmcrootfstype=ext4\0" \
156 "nandroot=/dev/mtdblock4 rw\0" \
157 "nandrootfstype=ubifs\0" \
158 "mmcargs=setenv bootargs console=${console} " \
159 "mpurate=${mpurate} " \
160 "vram=${vram} " \
161 "omapfb.mode=dvi:${dvimode} " \
162 "omapdss.def_disp=${defaultdisplay} " \
163 "root=${mmcroot} " \
164 "rootfstype=${mmcrootfstype}\0" \
165 "nandargs=setenv bootargs console=${console} " \
166 "mpurate=${mpurate} " \
167 "vram=${vram} " \
168 "omapfb.mode=dvi:${dvimode} " \
169 "omapdss.def_disp=${defaultdisplay} " \
170 "root=${nandroot} " \
171 "rootfstype=${nandrootfstype}\0" \
172 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
173 "bootscript=echo Running bootscript from mmc ...; " \
174 "source ${loadaddr}\0" \
175 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
176 "mmcboot=echo Booting from mmc ...; " \
177 "run mmcargs; " \
178 "bootm ${loadaddr}\0" \
179 "nandboot=echo Booting from nand ...; " \
180 "run nandargs; " \
181 "nand read ${loadaddr} 2a0000 400000; " \
182 "bootm ${loadaddr}\0" \
183
Igor Grinbergb09bf722014-11-05 14:25:35 +0200184#define CONFIG_BOOTCOMMAND \
185 "mmc dev ${mmcdev}; if mmc rescan; then " \
186 "if run loadbootscript; then " \
187 "run bootscript; " \
188 "else " \
189 "if run loaduimage; then " \
190 "run mmcboot; " \
191 "else run nandboot; " \
192 "fi; " \
193 "fi; " \
194 "else run nandboot; fi"
195
196/*
197 * Miscellaneous configurable options
198 */
199#define CONFIG_AUTO_COMPLETE
200#define CONFIG_CMDLINE_EDITING
201#define CONFIG_TIMESTAMP
202#define CONFIG_SYS_AUTOLOAD "no"
203#define CONFIG_SYS_LONGHELP /* undef to save memory */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200204#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
205/* Print Buffer Size */
206#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
207 sizeof(CONFIG_SYS_PROMPT) + 16)
208#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
209/* Boot Argument Buffer Size */
210#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
211
212#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
213
214/*
215 * AM3517 has 12 GP timers, they can be driven by the system clock
216 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
217 * This rate is divided by a local divisor.
218 */
219#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
220#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
221#define CONFIG_SYS_HZ 1000
222
223/*-----------------------------------------------------------------------
224 * Physical Memory Map
225 */
226#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */
227#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
228#define CONFIG_SYS_CS0_SIZE (256 << 20)
229
230/*-----------------------------------------------------------------------
231 * FLASH and environment organization
232 */
233
234/* **** PISMO SUPPORT *** */
235/* Monitor at start of flash */
236#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
237#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
238
239#define CONFIG_ENV_IS_IN_NAND
240#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
241#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
242#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
243
Igor Grinberga8a78c72014-11-03 11:32:26 +0200244#if defined(CONFIG_CMD_NET)
245#define CONFIG_DRIVER_TI_EMAC
246#define CONFIG_DRIVER_TI_EMAC_USE_RMII
247#define CONFIG_MII
248#define CONFIG_SMC911X
249#define CONFIG_SMC911X_32_BIT
250#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20))
Dmitry Lifshitze093d0b2015-09-08 09:50:00 +0300251#define CONFIG_ARP_TIMEOUT 200UL
252#define CONFIG_NET_RETRY_COUNT 5
Igor Grinberga8a78c72014-11-03 11:32:26 +0200253#endif /* CONFIG_CMD_NET */
254
Igor Grinbergb09bf722014-11-05 14:25:35 +0200255/* additions for new relocation code, must be added to all boards */
256#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
257#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
258#define CONFIG_SYS_INIT_RAM_SIZE 0x800
259#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
260 CONFIG_SYS_INIT_RAM_SIZE - \
261 GENERATED_GBL_DATA_SIZE)
262
263/* Status LED */
264#define CONFIG_STATUS_LED /* Status LED enabled */
265#define CONFIG_BOARD_SPECIFIC_LED
266#define CONFIG_GPIO_LED
267#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
268#define GREEN_LED_DEV 0
269#define STATUS_LED_BIT GREEN_LED_GPIO
270#define STATUS_LED_STATE STATUS_LED_ON
271#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
272#define STATUS_LED_BOOT GREEN_LED_DEV
273
274/* GPIO banks */
275#ifdef CONFIG_STATUS_LED
276#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
277#endif
278
Igor Grinberg40bbd522014-11-03 11:32:27 +0200279/* Display Configuration */
280#define CONFIG_OMAP3_GPIO_2
281#define CONFIG_OMAP3_GPIO_5
282#define CONFIG_VIDEO_OMAP3
283#define LCD_BPP LCD_COLOR16
284
285#define CONFIG_LCD
286#define CONFIG_SPLASH_SCREEN
287#define CONFIG_SPLASHIMAGE_GUARD
288#define CONFIG_CMD_BMP
289#define CONFIG_BMP_16BPP
290#define CONFIG_SCF0403_LCD
291
292#define CONFIG_OMAP3_SPI
293
Nikita Kiryanov19a90ed2016-04-16 17:55:08 +0300294/* EEPROM */
295#define CONFIG_CMD_EEPROM
296#define CONFIG_ENV_EEPROM_IS_ON_I2C
297#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
298#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
299#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
300#define CONFIG_SYS_EEPROM_SIZE 256
301
302#define CONFIG_CMD_EEPROM_LAYOUT
303#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3"
304
Igor Grinbergb09bf722014-11-05 14:25:35 +0200305#endif /* __CONFIG_H */