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Dirk Eibacha605ea72010-10-21 10:50:05 +02001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibacha605ea72010-10-21 10:50:05 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibacha605ea72010-10-21 10:50:05 +020012#define CONFIG_IO 1 /* on a Io board */
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME io
Dirk Eibacha605ea72010-10-21 10:50:05 +020020#include "amcc-common.h"
21
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000022#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibachb19bf832012-04-26 03:54:23 +000023#define CONFIG_MISC_INIT_R
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000024#define CONFIG_LAST_STAGE_INIT
Dirk Eibacha605ea72010-10-21 10:50:05 +020025
26#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
27
28/*
29 * Configure PLL
30 */
31#define PLLMR0_DEFAULT PLLMR0_266_133_66
32#define PLLMR1_DEFAULT PLLMR1_266_133_66
33
34/* new uImage format support */
Dirk Eibach9a4f4792014-07-03 09:28:26 +020035#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibacha605ea72010-10-21 10:50:05 +020036
37#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
38
39/*
40 * Default environment variables
41 */
42#define CONFIG_EXTRA_ENV_SETTINGS \
43 CONFIG_AMCC_DEF_ENV \
44 CONFIG_AMCC_DEF_ENV_POWERPC \
45 CONFIG_AMCC_DEF_ENV_NOR_UPD \
46 "kernel_addr=fc000000\0" \
47 "fdt_addr=fc1e0000\0" \
48 "ramdisk_addr=fc200000\0" \
49 ""
50
51#define CONFIG_PHY_ADDR 4 /* PHY address */
52#define CONFIG_HAS_ETH0
53#define CONFIG_HAS_ETH1
54#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
55#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
56
57/*
58 * Commands additional to the ones defined in amcc-common.h
59 */
Dirk Eibachb19bf832012-04-26 03:54:23 +000060#define CONFIG_CMD_DTT
Dirk Eibach4fb9b412014-07-03 09:28:25 +020061#undef CONFIG_CMD_DIAG
Dirk Eibacha605ea72010-10-21 10:50:05 +020062#undef CONFIG_CMD_EEPROM
Dirk Eibach4fb9b412014-07-03 09:28:25 +020063#undef CONFIG_CMD_IRQ
Dirk Eibacha605ea72010-10-21 10:50:05 +020064
65/*
66 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
67 */
68#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
69
70/* SDRAM timings used in datasheet */
71#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
72#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
73#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
74#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
75#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
76
77/*
78 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
79 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
80 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
81 * The Linux BASE_BAUD define should match this configuration.
82 * baseBaud = cpuClock/(uartDivisor*16)
83 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
84 * set Linux BASE_BAUD to 403200.
85 */
86#define CONFIG_CONS_INDEX 1 /* Use UART0 */
87#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
88#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
89#define CONFIG_SYS_BASE_BAUD 691200
90
91/*
92 * I2C stuff
93 */
Dirk Eibach880540d2013-04-25 02:40:01 +000094#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Dirk Eibacha605ea72010-10-21 10:50:05 +020095
96/* Temp sensor/hwmon/dtt */
97#define CONFIG_DTT_LM63 1 /* National LM63 */
98#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
99#define CONFIG_DTT_PWM_LOOKUPTABLE \
100 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
101#define CONFIG_DTT_TACH_LIMIT 0xa10
102
103/*
104 * FLASH organization
105 */
106#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
107#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
108
109#define CONFIG_SYS_FLASH_BASE 0xFC000000
110#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
111
112#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
113#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
114
115#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
116#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
117
118#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibacha605ea72010-10-21 10:50:05 +0200119
120#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
121#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
122
123#ifdef CONFIG_ENV_IS_IN_FLASH
124#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
125#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
126#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
127
128/* Address and size of Redundant Environment Sector */
129#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
130#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
131#endif
132
133/* Gbit PHYs */
134#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
135#define CONFIG_BITBANGMII_MULTI
136
137#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13) /* our MDIO is GPIO0 */
138#define CONFIG_SYS_MDC_PIN (0x80000000 >> 7) /* our MDC is GPIO7 */
139
140#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy"
141
142/*
143 * PPC405 GPIO Configuration
144 */
145#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
146{ \
147/* GPIO Core 0 */ \
148{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
149{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
150{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
151{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
152{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
153{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
154{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
155{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
156{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
157{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
158{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
159{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
160{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
161{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
162{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
163{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
164{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
165{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
166{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
167{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
168{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
169{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
170{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
171{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
172{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
173{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
174{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
175{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
176{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
177{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
178{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
179{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
180} \
181}
182
183/*
184 * Definitions for initial stack pointer and data area (in data cache)
185 */
186/* use on chip memory (OCM) for temperary stack until sdram is tested */
187#define CONFIG_SYS_TEMP_STACK_OCM 1
188
189/* On Chip Memory location */
190#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
191#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
192#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
York Sunb39d1212016-04-06 13:22:10 -0700193#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
Dirk Eibacha605ea72010-10-21 10:50:05 +0200194
Dirk Eibacha605ea72010-10-21 10:50:05 +0200195#define CONFIG_SYS_GBL_DATA_OFFSET \
York Sunb39d1212016-04-06 13:22:10 -0700196 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200197#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
198
199/*
200 * External Bus Controller (EBC) Setup
201 */
202
203/* Memory Bank 0 (NOR-FLASH) initialization */
204#define CONFIG_SYS_EBC_PB0AP 0xa382a880
205/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
206#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
207
208/* Memory Bank 1 (NVRAM) initializatio */
209#define CONFIG_SYS_EBC_PB1AP 0x92015480
210/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
211#define CONFIG_SYS_EBC_PB1CR 0x7f318000
212
213/* Memory Bank 2 (FPGA) initialization */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100214#define CONFIG_SYS_FPGA0_BASE 0x7f100000
Dirk Eibacha605ea72010-10-21 10:50:05 +0200215#define CONFIG_SYS_EBC_PB2AP 0x02025080
216/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
217#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
218
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100219#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
220#define CONFIG_SYS_FPGA_DONE(k) 0x0010
221
222#define CONFIG_SYS_FPGA_COUNT 1
Dirk Eibacha605ea72010-10-21 10:50:05 +0200223
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200224#define CONFIG_SYS_FPGA_PTR \
225 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
226
227#define CONFIG_SYS_FPGA_COMMON
228
Dirk Eibacha605ea72010-10-21 10:50:05 +0200229/* Memory Bank 3 (Latches) initialization */
230#define CONFIG_SYS_LATCH_BASE 0x7f200000
231#define CONFIG_SYS_EBC_PB3AP 0xa2015480
232/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
233#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
234
235#define CONFIG_SYS_LATCH0_RESET 0xffff
236#define CONFIG_SYS_LATCH0_BOOT 0xffff
237#define CONFIG_SYS_LATCH1_RESET 0xffbf
238#define CONFIG_SYS_LATCH1_BOOT 0xffff
239
240#endif /* __CONFIG_H */