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Kumar Gala129ba612008-08-12 11:13:08 -05001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
Kumar Gala129ba612008-08-12 11:13:08 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8572ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Kumar Gala509c4c42010-05-21 04:05:14 -050030#include "../board/freescale/common/ics307_clk.h"
31
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020032#ifdef CONFIG_36BIT
Kumar Galaf9edcc12009-09-10 16:23:45 -050033#define CONFIG_PHYS_64BIT
34#endif
35
Kumar Galacb14e932010-11-12 08:22:01 -060036#ifdef CONFIG_NAND
37#define CONFIG_NAND_U_BOOT
38#define CONFIG_RAMBOOT_NAND
39#ifdef CONFIG_NAND_SPL
40#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
41#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
42#else
43#define CONFIG_SYS_TEXT_BASE 0xf8f82000
44#endif /* CONFIG_NAND_SPL */
45#endif
46
47#ifndef CONFIG_SYS_TEXT_BASE
48#define CONFIG_SYS_TEXT_BASE 0xeff80000
49#endif
50
Kumar Gala7a577fd2011-01-12 02:48:53 -060051#ifndef CONFIG_RESET_VECTOR_ADDRESS
52#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
53#endif
54
Kumar Galacb14e932010-11-12 08:22:01 -060055#ifndef CONFIG_SYS_MONITOR_BASE
56#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
57#endif
58
Kumar Gala129ba612008-08-12 11:13:08 -050059/* High Level Configuration Options */
60#define CONFIG_BOOKE 1 /* BOOKE */
61#define CONFIG_E500 1 /* BOOKE e500 family */
62#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
63#define CONFIG_MPC8572 1
64#define CONFIG_MPC8572DS 1
65#define CONFIG_MP 1 /* support multiple processors */
Kumar Gala129ba612008-08-12 11:13:08 -050066
Kumar Galac51fc5d2009-01-23 14:22:13 -060067#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala129ba612008-08-12 11:13:08 -050068#define CONFIG_PCI 1 /* Enable PCI/PCIE */
69#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
70#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
71#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
72#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
73#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050074#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala129ba612008-08-12 11:13:08 -050075
76#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
77
78#define CONFIG_TSEC_ENET /* tsec ethernet support */
79#define CONFIG_ENV_OVERWRITE
80
Kumar Gala509c4c42010-05-21 04:05:14 -050081#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
82#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
Haiying Wang4ca06602008-10-03 12:37:41 -040083#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala129ba612008-08-12 11:13:08 -050084
85/*
86 * These can be toggled for performance analysis, otherwise use default.
87 */
88#define CONFIG_L2_CACHE /* toggle L2 cache */
89#define CONFIG_BTB /* toggle branch predition */
Kumar Gala129ba612008-08-12 11:13:08 -050090
91#define CONFIG_ENABLE_36BIT_PHYS 1
92
Kumar Gala18af1c52009-01-23 14:22:14 -060093#ifdef CONFIG_PHYS_64BIT
94#define CONFIG_ADDR_MAP 1
95#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
96#endif
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
99#define CONFIG_SYS_MEMTEST_END 0x7fffffff
Kumar Gala129ba612008-08-12 11:13:08 -0500100#define CONFIG_PANIC_HANG /* do not reset board on panic */
101
102/*
Kumar Galacb14e932010-11-12 08:22:01 -0600103 * Config the L2 Cache as L2 SRAM
104 */
105#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
106#ifdef CONFIG_PHYS_64BIT
107#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
108#else
109#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
110#endif
111#define CONFIG_SYS_L2_SIZE (512 << 10)
112#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
113
114/*
Kumar Gala129ba612008-08-12 11:13:08 -0500115 * Base addresses -- Note these are effective addresses where the
116 * actual resources get mapped (not physical addresses)
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Kumar Gala18af1c52009-01-23 14:22:14 -0600119#ifdef CONFIG_PHYS_64BIT
120#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
121#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
Kumar Gala18af1c52009-01-23 14:22:14 -0600123#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Kumar Gala129ba612008-08-12 11:13:08 -0500125
Kumar Galacb14e932010-11-12 08:22:01 -0600126#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
127#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
128#else
129#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
130#endif
131
Kumar Gala129ba612008-08-12 11:13:08 -0500132/* DDR Setup */
Kumar Galaf8523cb2009-02-06 09:56:35 -0600133#define CONFIG_VERY_BIG_RAM
Kumar Gala129ba612008-08-12 11:13:08 -0500134#define CONFIG_FSL_DDR2
135#undef CONFIG_FSL_DDR_INTERACTIVE
136#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
137#define CONFIG_DDR_SPD
Kumar Gala129ba612008-08-12 11:13:08 -0500138
York Sund34897d2011-01-25 21:51:29 -0800139#define CONFIG_DDR_ECC
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800140#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Kumar Gala129ba612008-08-12 11:13:08 -0500141#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
144#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala129ba612008-08-12 11:13:08 -0500145
146#define CONFIG_NUM_DDR_CONTROLLERS 2
147#define CONFIG_DIMM_SLOTS_PER_CTLR 1
148#define CONFIG_CHIP_SELECTS_PER_CTRL 2
149
150/* I2C addresses of SPD EEPROMs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500152#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
153#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
154
155/* These are used when DDR doesn't use SPD. */
Dave Liudc889e82008-11-28 20:16:58 +0800156#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
157#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
158#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
159#define CONFIG_SYS_DDR_TIMING_3 0x00020000
160#define CONFIG_SYS_DDR_TIMING_0 0x00260802
161#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
162#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
163#define CONFIG_SYS_DDR_MODE_1 0x00440462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_DDR_MODE_2 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800165#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
Dave Liudc889e82008-11-28 20:16:58 +0800167#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
168#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800170#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
171#define CONFIG_SYS_DDR_CONTROL2 0x24400000
Kumar Gala129ba612008-08-12 11:13:08 -0500172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
174#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
175#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala129ba612008-08-12 11:13:08 -0500176
177/*
Kumar Gala129ba612008-08-12 11:13:08 -0500178 * Make sure required options are set
179 */
180#ifndef CONFIG_SPD_EEPROM
181#error ("CONFIG_SPD_EEPROM is required")
182#endif
183
184#undef CONFIG_CLOCKS_IN_MHZ
185
186/*
187 * Memory map
188 *
189 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
190 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
191 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
192 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
193 *
194 * Localbus cacheable (TBD)
195 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
196 *
197 * Localbus non-cacheable
198 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
199 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100200 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala129ba612008-08-12 11:13:08 -0500201 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
202 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
203 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
204 */
205
206/*
207 * Local Bus Definitions
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala18af1c52009-01-23 14:22:14 -0600210#ifdef CONFIG_PHYS_64BIT
211#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
212#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600213#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600214#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500215
Kumar Galacb14e932010-11-12 08:22:01 -0600216
217#define CONFIG_FLASH_BR_PRELIM \
218 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
219 | BR_PS_16 | BR_V)
220#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500221
Kumar Galac953ddf2008-12-02 14:19:34 -0600222#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
223#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500224
Kumar Gala18af1c52009-01-23 14:22:14 -0600225#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala129ba612008-08-12 11:13:08 -0500227#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
230#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
231#undef CONFIG_SYS_FLASH_CHECKSUM
232#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
233#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala129ba612008-08-12 11:13:08 -0500234
Kumar Galacb14e932010-11-12 08:22:01 -0600235#if defined(CONFIG_RAMBOOT_NAND)
236#define CONFIG_SYS_RAMBOOT
237#define CONFIG_SYS_EXTRA_ENV_RELOC
238#else
239#undef CONFIG_SYS_RAMBOOT
240#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500241
242#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_FLASH_CFI
244#define CONFIG_SYS_FLASH_EMPTY_INFO
245#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala129ba612008-08-12 11:13:08 -0500246
247#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
248
Kumar Gala558710b2010-11-19 08:53:25 -0600249#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala129ba612008-08-12 11:13:08 -0500250#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
251#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala18af1c52009-01-23 14:22:14 -0600252#ifdef CONFIG_PHYS_64BIT
253#define PIXIS_BASE_PHYS 0xfffdf0000ull
254#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600255#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600256#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500257
Kumar Gala52b565f2008-12-02 14:19:33 -0600258#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala129ba612008-08-12 11:13:08 -0500260
261#define PIXIS_ID 0x0 /* Board ID at offset 0 */
262#define PIXIS_VER 0x1 /* Board version at offset 1 */
263#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
264#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
265#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
266#define PIXIS_PWR 0x5 /* PIXIS Power status register */
267#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
268#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
269#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
270#define PIXIS_VCTL 0x10 /* VELA Control Register */
271#define PIXIS_VSTAT 0x11 /* VELA Status Register */
272#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
273#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
274#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
275#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500276#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
277#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
278#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
279#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
280#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500281#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
282#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
283#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
284#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
285#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
286#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
287#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
288#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
289#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
290#define PIXIS_VWATCH 0x24 /* Watchdog Register */
291#define PIXIS_LED 0x25 /* LED Register */
292
Kumar Galacb14e932010-11-12 08:22:01 -0600293#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
294
Kumar Gala129ba612008-08-12 11:13:08 -0500295/* old pixis referenced names */
296#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
297#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
Liu Yu7e183ca2008-10-10 11:40:59 +0800299#define PIXIS_VSPEED2_TSEC1SER 0x8
300#define PIXIS_VSPEED2_TSEC2SER 0x4
301#define PIXIS_VSPEED2_TSEC3SER 0x2
302#define PIXIS_VSPEED2_TSEC4SER 0x1
303#define PIXIS_VCFGEN1_TSEC1SER 0x20
304#define PIXIS_VCFGEN1_TSEC2SER 0x20
305#define PIXIS_VCFGEN1_TSEC3SER 0x20
306#define PIXIS_VCFGEN1_TSEC4SER 0x20
307#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
308 | PIXIS_VSPEED2_TSEC2SER \
309 | PIXIS_VSPEED2_TSEC3SER \
310 | PIXIS_VSPEED2_TSEC4SER)
311#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
312 | PIXIS_VCFGEN1_TSEC2SER \
313 | PIXIS_VCFGEN1_TSEC3SER \
314 | PIXIS_VCFGEN1_TSEC4SER)
Kumar Gala129ba612008-08-12 11:13:08 -0500315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_INIT_RAM_LOCK 1
317#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200318#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala129ba612008-08-12 11:13:08 -0500319
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200320#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
324#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala129ba612008-08-12 11:13:08 -0500325
Kumar Galacb14e932010-11-12 08:22:01 -0600326#ifndef CONFIG_NAND_SPL
Haiying Wangc013b742008-10-29 13:32:59 -0400327#define CONFIG_SYS_NAND_BASE 0xffa00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600328#ifdef CONFIG_PHYS_64BIT
329#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
330#else
Haiying Wangc013b742008-10-29 13:32:59 -0400331#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600332#endif
Kumar Galacb14e932010-11-12 08:22:01 -0600333#else
334#define CONFIG_SYS_NAND_BASE 0xfff00000
335#ifdef CONFIG_PHYS_64BIT
336#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
337#else
338#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
339#endif
340#endif
341
Haiying Wangc013b742008-10-29 13:32:59 -0400342#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
343 CONFIG_SYS_NAND_BASE + 0x40000, \
344 CONFIG_SYS_NAND_BASE + 0x80000,\
345 CONFIG_SYS_NAND_BASE + 0xC0000}
346#define CONFIG_SYS_MAX_NAND_DEVICE 4
Haiying Wangc013b742008-10-29 13:32:59 -0400347#define CONFIG_MTD_NAND_VERIFY_WRITE
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100348#define CONFIG_CMD_NAND 1
349#define CONFIG_NAND_FSL_ELBC 1
Haiying Wangc013b742008-10-29 13:32:59 -0400350#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
351
Kumar Galacb14e932010-11-12 08:22:01 -0600352/* NAND boot: 4K NAND loader config */
353#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
354#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
355#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
356#define CONFIG_SYS_NAND_U_BOOT_START \
357 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
358#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
359#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
360#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
361
362
Haiying Wangc013b742008-10-29 13:32:59 -0400363/* NAND flash config */
Kumar Gala72a9414a2009-01-23 14:22:12 -0600364#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100365 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
366 | BR_PS_8 /* Port Size = 8 bit */ \
367 | BR_MS_FCM /* MSEL = FCM */ \
368 | BR_V) /* valid */
369#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
370 | OR_FCM_PGS /* Large Page*/ \
371 | OR_FCM_CSCT \
372 | OR_FCM_CST \
373 | OR_FCM_CHT \
374 | OR_FCM_SCY_1 \
375 | OR_FCM_TRLX \
376 | OR_FCM_EHTR)
Haiying Wangc013b742008-10-29 13:32:59 -0400377
Kumar Galacb14e932010-11-12 08:22:01 -0600378#ifdef CONFIG_RAMBOOT_NAND
379#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
380#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
381#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
382#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
383#else
384#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
385#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400386#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
387#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Kumar Galacb14e932010-11-12 08:22:01 -0600388#endif
Kumar Gala72a9414a2009-01-23 14:22:12 -0600389#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100390 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
391 | BR_PS_8 /* Port Size = 8 bit */ \
392 | BR_MS_FCM /* MSEL = FCM */ \
393 | BR_V) /* valid */
394#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Kumar Gala72a9414a2009-01-23 14:22:12 -0600395#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100396 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
397 | BR_PS_8 /* Port Size = 8 bit */ \
398 | BR_MS_FCM /* MSEL = FCM */ \
399 | BR_V) /* valid */
400#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400401
Kumar Gala72a9414a2009-01-23 14:22:12 -0600402#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100403 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
404 | BR_PS_8 /* Port Size = 8 bit */ \
405 | BR_MS_FCM /* MSEL = FCM */ \
406 | BR_V) /* valid */
407#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400408
409
Kumar Gala129ba612008-08-12 11:13:08 -0500410/* Serial Port - controlled on board with jumper J8
411 * open - index 2
412 * shorted - index 1
413 */
414#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_NS16550
416#define CONFIG_SYS_NS16550_SERIAL
417#define CONFIG_SYS_NS16550_REG_SIZE 1
418#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Galacb14e932010-11-12 08:22:01 -0600419#ifdef CONFIG_NAND_SPL
420#define CONFIG_NS16550_MIN_FUNCTIONS
421#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500422
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala129ba612008-08-12 11:13:08 -0500424 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
425
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
427#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Kumar Gala129ba612008-08-12 11:13:08 -0500428
429/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_HUSH_PARSER
431#ifdef CONFIG_SYS_HUSH_PARSER
432#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Kumar Gala129ba612008-08-12 11:13:08 -0500433#endif
434
435/*
436 * Pass open firmware flat tree
437 */
438#define CONFIG_OF_LIBFDT 1
439#define CONFIG_OF_BOARD_SETUP 1
440#define CONFIG_OF_STDOUT_VIA_ALIAS 1
441
Kumar Gala129ba612008-08-12 11:13:08 -0500442/* new uImage format support */
443#define CONFIG_FIT 1
444#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
445
446/* I2C */
447#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
448#define CONFIG_HARD_I2C /* I2C with hardware support */
449#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Haiying Wang1f3ba312008-10-03 11:46:59 -0400450#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
452#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
453#define CONFIG_SYS_I2C_SLAVE 0x7F
454#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
455#define CONFIG_SYS_I2C_OFFSET 0x3000
456#define CONFIG_SYS_I2C2_OFFSET 0x3100
Kumar Gala129ba612008-08-12 11:13:08 -0500457
458/*
Haiying Wang445a7b32008-10-03 11:47:30 -0400459 * I2C2 EEPROM
460 */
461#define CONFIG_ID_EEPROM
462#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_I2C_EEPROM_NXID
Haiying Wang445a7b32008-10-03 11:47:30 -0400464#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
466#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
467#define CONFIG_SYS_EEPROM_BUS_NUM 1
Haiying Wang445a7b32008-10-03 11:47:30 -0400468
469/*
Kumar Gala129ba612008-08-12 11:13:08 -0500470 * General PCI
471 * Memory space is mapped 1-1, but I/O space must start from 0.
472 */
473
Kumar Gala129ba612008-08-12 11:13:08 -0500474/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600475#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600476#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600477#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500478#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600479#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
480#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600481#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600482#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600483#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600485#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600486#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600487#ifdef CONFIG_PHYS_64BIT
488#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
489#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600491#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500493
494/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600495#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600496#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600497#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500498#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600499#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
500#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600501#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600502#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600503#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600505#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600506#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600507#ifdef CONFIG_PHYS_64BIT
508#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
509#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
Kumar Gala18af1c52009-01-23 14:22:14 -0600511#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500513
514/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600515#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600516#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600517#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500518#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600519#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
520#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600521#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600522#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600523#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600525#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600526#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600527#ifdef CONFIG_PHYS_64BIT
528#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
529#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
Kumar Gala18af1c52009-01-23 14:22:14 -0600531#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500533
534#if defined(CONFIG_PCI)
535
536/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600537#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Kumar Gala129ba612008-08-12 11:13:08 -0500538
539/* video */
540#define CONFIG_VIDEO
541
542#if defined(CONFIG_VIDEO)
543#define CONFIG_BIOSEMU
544#define CONFIG_CFB_CONSOLE
545#define CONFIG_VIDEO_SW_CURSOR
546#define CONFIG_VGA_AS_SINGLE_DEVICE
547#define CONFIG_ATI_RADEON_FB
548#define CONFIG_VIDEO_LOGO
549/*#define CONFIG_CONSOLE_CURSOR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200550#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500551#endif
552
553#define CONFIG_NET_MULTI
554#define CONFIG_PCI_PNP /* do pci plug-and-play */
555
556#undef CONFIG_EEPRO100
557#undef CONFIG_TULIP
558#undef CONFIG_RTL8139
Kumar Gala16855ec2010-11-09 23:19:50 -0600559#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Kumar Gala129ba612008-08-12 11:13:08 -0500560
Kumar Gala129ba612008-08-12 11:13:08 -0500561#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600562 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
563 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
Kumar Gala129ba612008-08-12 11:13:08 -0500564 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
565#endif
566
567#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
568#define CONFIG_DOS_PARTITION
569#define CONFIG_SCSI_AHCI
570
571#ifdef CONFIG_SCSI_AHCI
572#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200573#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
574#define CONFIG_SYS_SCSI_MAX_LUN 1
575#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
576#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Kumar Gala129ba612008-08-12 11:13:08 -0500577#endif /* SCSI */
578
579#endif /* CONFIG_PCI */
580
581
582#if defined(CONFIG_TSEC_ENET)
583
584#ifndef CONFIG_NET_MULTI
585#define CONFIG_NET_MULTI 1
586#endif
587
588#define CONFIG_MII 1 /* MII PHY management */
589#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
590#define CONFIG_TSEC1 1
591#define CONFIG_TSEC1_NAME "eTSEC1"
592#define CONFIG_TSEC2 1
593#define CONFIG_TSEC2_NAME "eTSEC2"
594#define CONFIG_TSEC3 1
595#define CONFIG_TSEC3_NAME "eTSEC3"
596#define CONFIG_TSEC4 1
597#define CONFIG_TSEC4_NAME "eTSEC4"
598
Liu Yu7e183ca2008-10-10 11:40:59 +0800599#define CONFIG_PIXIS_SGMII_CMD
600#define CONFIG_FSL_SGMII_RISER 1
601#define SGMII_RISER_PHY_OFFSET 0x1c
602
603#ifdef CONFIG_FSL_SGMII_RISER
604#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
605#endif
606
Kumar Gala129ba612008-08-12 11:13:08 -0500607#define TSEC1_PHY_ADDR 0
608#define TSEC2_PHY_ADDR 1
609#define TSEC3_PHY_ADDR 2
610#define TSEC4_PHY_ADDR 3
611
612#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
613#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
614#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
615#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
616
617#define TSEC1_PHYIDX 0
618#define TSEC2_PHYIDX 0
619#define TSEC3_PHYIDX 0
620#define TSEC4_PHYIDX 0
621
622#define CONFIG_ETHPRIME "eTSEC1"
623
624#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
625#endif /* CONFIG_TSEC_ENET */
626
627/*
628 * Environment
629 */
Kumar Galacb14e932010-11-12 08:22:01 -0600630
631#if defined(CONFIG_SYS_RAMBOOT)
632#if defined(CONFIG_RAMBOOT_NAND)
633#define CONFIG_ENV_IS_IN_NAND 1
634#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
635#define CONFIG_ENV_OFFSET ((512 * 1024)\
636 + CONFIG_SYS_NAND_BLOCK_SIZE)
Kumar Gala129ba612008-08-12 11:13:08 -0500637#endif
Kumar Galacb14e932010-11-12 08:22:01 -0600638
639#else
640 #define CONFIG_ENV_IS_IN_FLASH 1
641 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
642 #define CONFIG_ENV_ADDR 0xfff80000
643 #else
644 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
645 #endif
646 #define CONFIG_ENV_SIZE 0x2000
647 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
648#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500649
650#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200651#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala129ba612008-08-12 11:13:08 -0500652
653/*
654 * Command line configuration.
655 */
656#include <config_cmd_default.h>
657
York Sun67f94472011-01-26 00:14:57 -0600658#define CONFIG_CMD_ERRATA
Kumar Gala129ba612008-08-12 11:13:08 -0500659#define CONFIG_CMD_IRQ
660#define CONFIG_CMD_PING
661#define CONFIG_CMD_I2C
662#define CONFIG_CMD_MII
663#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500664#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500665#define CONFIG_CMD_REGINFO
Kumar Gala129ba612008-08-12 11:13:08 -0500666
667#if defined(CONFIG_PCI)
668#define CONFIG_CMD_PCI
Kumar Gala129ba612008-08-12 11:13:08 -0500669#define CONFIG_CMD_NET
670#define CONFIG_CMD_SCSI
671#define CONFIG_CMD_EXT2
672#endif
673
674#undef CONFIG_WATCHDOG /* watchdog disabled */
675
676/*
677 * Miscellaneous configurable options
678 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200679#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500680#define CONFIG_CMDLINE_EDITING /* Command-line editing */
681#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200682#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
683#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kumar Gala129ba612008-08-12 11:13:08 -0500684#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200685#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500686#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200687#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500688#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200689#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
690#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
691#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
692#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kumar Gala129ba612008-08-12 11:13:08 -0500693
694/*
695 * For booting Linux, the board info and command line data
Kumar Gala89188a62009-07-15 08:54:50 -0500696 * have to be in the first 16 MB of memory, since this is
Kumar Gala129ba612008-08-12 11:13:08 -0500697 * the maximum mapped by the Linux kernel during initialization.
698 */
Kumar Gala89188a62009-07-15 08:54:50 -0500699#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Kumar Gala7c57f3e2011-01-11 00:52:35 -0600700#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Kumar Gala129ba612008-08-12 11:13:08 -0500701
Kumar Gala129ba612008-08-12 11:13:08 -0500702#if defined(CONFIG_CMD_KGDB)
703#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
704#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
705#endif
706
707/*
708 * Environment Configuration
709 */
710
711/* The mac addresses for all ethernet interface */
712#if defined(CONFIG_TSEC_ENET)
713#define CONFIG_HAS_ETH0
714#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
715#define CONFIG_HAS_ETH1
716#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
717#define CONFIG_HAS_ETH2
718#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
719#define CONFIG_HAS_ETH3
720#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
721#endif
722
723#define CONFIG_IPADDR 192.168.1.254
724
725#define CONFIG_HOSTNAME unknown
726#define CONFIG_ROOTPATH /opt/nfsroot
727#define CONFIG_BOOTFILE uImage
728#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
729
730#define CONFIG_SERVERIP 192.168.1.1
731#define CONFIG_GATEWAYIP 192.168.1.1
732#define CONFIG_NETMASK 255.255.255.0
733
734/* default location for tftp and bootm */
735#define CONFIG_LOADADDR 1000000
736
737#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
738#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
739
740#define CONFIG_BAUDRATE 115200
741
742#define CONFIG_EXTRA_ENV_SETTINGS \
Haiying Wang4ca06602008-10-03 12:37:41 -0400743 "memctl_intlv_ctl=2\0" \
Kumar Gala129ba612008-08-12 11:13:08 -0500744 "netdev=eth0\0" \
745 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
746 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200747 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
748 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
749 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
750 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
751 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Kumar Gala129ba612008-08-12 11:13:08 -0500752 "consoledev=ttyS0\0" \
753 "ramdiskaddr=2000000\0" \
754 "ramdiskfile=8572ds/ramdisk.uboot\0" \
755 "fdtaddr=c00000\0" \
756 "fdtfile=8572ds/mpc8572ds.dtb\0" \
757 "bdev=sda3\0"
758
759#define CONFIG_HDBOOT \
760 "setenv bootargs root=/dev/$bdev rw " \
761 "console=$consoledev,$baudrate $othbootargs;" \
762 "tftp $loadaddr $bootfile;" \
763 "tftp $fdtaddr $fdtfile;" \
764 "bootm $loadaddr - $fdtaddr"
765
766#define CONFIG_NFSBOOTCOMMAND \
767 "setenv bootargs root=/dev/nfs rw " \
768 "nfsroot=$serverip:$rootpath " \
769 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
770 "console=$consoledev,$baudrate $othbootargs;" \
771 "tftp $loadaddr $bootfile;" \
772 "tftp $fdtaddr $fdtfile;" \
773 "bootm $loadaddr - $fdtaddr"
774
775#define CONFIG_RAMBOOTCOMMAND \
776 "setenv bootargs root=/dev/ram rw " \
777 "console=$consoledev,$baudrate $othbootargs;" \
778 "tftp $ramdiskaddr $ramdiskfile;" \
779 "tftp $loadaddr $bootfile;" \
780 "tftp $fdtaddr $fdtfile;" \
781 "bootm $loadaddr $ramdiskaddr $fdtaddr"
782
783#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
784
785#endif /* __CONFIG_H */