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Daniel Hellstrom69403832008-03-26 23:34:47 +01001/* Configuration header file for Gaisler Research AB's Template
2 * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
3 * Development board Stratix II edition, with the FPGA device
4 * EP2S60.
5 *
6 * (C) Copyright 2003-2005
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * (C) Copyright 2008
10 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
11 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020012 * SPDX-License-Identifier: GPL-2.0+
Daniel Hellstrom69403832008-03-26 23:34:47 +010013 */
14
15#ifndef __CONFIG_H__
16#define __CONFIG_H__
17
18/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
22
Daniel Hellstrom69403832008-03-26 23:34:47 +010023/* Altera NIOS Development board, Stratix II board */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020024#define CONFIG_GR_EP2S60 1
Daniel Hellstrom69403832008-03-26 23:34:47 +010025
26/* CPU / AMBA BUS configuration */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020027#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
Daniel Hellstrom69403832008-03-26 23:34:47 +010028
Daniel Hellstrom69403832008-03-26 23:34:47 +010029/* Define this is the GR-2S60-MEZZ mezzanine is available and you
30 * want to use the USB and GRETH functionality of the board
31 */
32#undef GR_2S60_MEZZ
33
34#ifdef GR_2S60_MEZZ
35#define USE_GRETH 1
36#define USE_GRUSB 1
37#endif
38
39/*
40 * Serial console configuration
41 */
42#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Daniel Hellstrom69403832008-03-26 23:34:47 +010044
45/* Partitions */
46#define CONFIG_DOS_PARTITION
Daniel Hellstrom69403832008-03-26 23:34:47 +010047#define CONFIG_ISO_PARTITION
48
49/*
50 * Supported commands
51 */
Daniel Hellstrom69403832008-03-26 23:34:47 +010052#define CONFIG_CMD_REGINFO
Daniel Hellstrom69403832008-03-26 23:34:47 +010053#define CONFIG_CMD_DIAG
54#define CONFIG_CMD_IRQ
55
56/* USB support */
57#if USE_GRUSB
58#define CONFIG_USB_UHCI
Daniel Hellstrom69403832008-03-26 23:34:47 +010059/* Enable needed helper functions */
Daniel Hellstrom69403832008-03-26 23:34:47 +010060#endif
61
62/*
63 * Autobooting
64 */
Daniel Hellstrom69403832008-03-26 23:34:47 +010065
66#define CONFIG_PREBOOT "echo;" \
67 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
68 "echo"
69
70#undef CONFIG_BOOTARGS
71
72#define CONFIG_EXTRA_ENV_SETTINGS \
73 "netdev=eth0\0" \
74 "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
75 "nfsroot=${serverip}:${rootpath}\0" \
76 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
77 "addip=setenv bootargs ${bootargs} " \
78 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
79 ":${hostname}:${netdev}:off panic=1\0" \
80 "flash_nfs=run nfsargs addip;" \
81 "bootm ${kernel_addr}\0" \
82 "flash_self=run ramargs addip;" \
83 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
84 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
85 "scratch=40800000\0" \
Mike Frysinger3a2b9f22011-10-12 19:47:51 +000086 "getkernel=tftpboot $(scratch) $(bootfile)\0" \
Daniel Hellstrom69403832008-03-26 23:34:47 +010087 "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
88 ""
89
90#define CONFIG_NETMASK 255.255.255.0
91#define CONFIG_GATEWAYIP 192.168.0.1
92#define CONFIG_SERVERIP 192.168.0.20
93#define CONFIG_IPADDR 192.168.0.207
Joe Hershberger8b3637c2011-10-13 13:03:47 +000094#define CONFIG_ROOTPATH "/export/rootfs"
Daniel Hellstrom69403832008-03-26 23:34:47 +010095#define CONFIG_HOSTNAME ml401
Joe Hershbergerb3f44c22011-10-13 13:03:48 +000096#define CONFIG_BOOTFILE "/uImage"
Daniel Hellstrom69403832008-03-26 23:34:47 +010097
98#define CONFIG_BOOTCOMMAND "run flash_self"
99
100/* Memory MAP
101 *
102 * Flash:
103 * |--------------------------------|
104 * | 0x00000000 Text & Data & BSS | *
105 * | for Monitor | *
106 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
107 * | UNUSED / Growth | * 256kb
108 * |--------------------------------|
109 * | 0x00050000 Base custom area | *
110 * | kernel / FS | *
111 * | | * Rest of Flash
112 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
113 * | END-0x00008000 Environment | * 32kb
114 * |--------------------------------|
115 *
116 *
117 *
118 * Main Memory:
119 * |--------------------------------|
120 * | UNUSED / scratch area |
121 * | |
122 * | |
123 * | |
124 * | |
125 * |--------------------------------|
126 * | Monitor .Text / .DATA / .BSS | * 512kb
127 * | Relocated! | *
128 * |--------------------------------|
129 * | Monitor Malloc | * 128kb (contains relocated environment)
130 * |--------------------------------|
131 * | Monitor/kernel STACK | * 64kb
132 * |--------------------------------|
133 * | Page Table for MMU systems | * 2k
134 * |--------------------------------|
135 * | PROM Code accessed from Linux | * 6kb-128b
136 * |--------------------------------|
137 * | Global data (avail from kernel)| * 128b
138 * |--------------------------------|
139 *
140 */
141
142/*
143 * Flash configuration (8,16 or 32 MB)
144 * TEXT base always at 0xFFF00000
145 * ENV_ADDR always at 0xFFF40000
146 * FLASH_BASE at 0xFC000000 for 64 MB
147 * 0xFE000000 for 32 MB
148 * 0xFF000000 for 16 MB
149 * 0xFF800000 for 8 MB
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151/*#define CONFIG_SYS_NO_FLASH 1*/
152#define CONFIG_SYS_FLASH_BASE 0x00000000
153#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100154
155#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
157#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
160#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
161#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
162#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
163#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100164
165/*** CFI CONFIG ***/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200167#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_FLASH_CFI
Daniel Hellstrom69403832008-03-26 23:34:47 +0100169/* Bypass cache when reading regs from flash memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
Daniel Hellstrom69403832008-03-26 23:34:47 +0100171/* Buffered writes (32byte/go) instead of single accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Daniel Hellstrom69403832008-03-26 23:34:47 +0100173
174/*
175 * Environment settings
176 */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200177/*#define CONFIG_ENV_IS_NOWHERE 1*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200178#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200179/* CONFIG_ENV_ADDR need to be at sector boundary */
180#define CONFIG_ENV_SIZE 0x8000
181#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
Daniel Hellstrom69403832008-03-26 23:34:47 +0100183#define CONFIG_ENV_OVERWRITE 1
184
185/*
186 * Memory map
187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_SDRAM_BASE 0x40000000
189#define CONFIG_SYS_SDRAM_SIZE 0x02000000
190#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
Daniel Hellstrom69403832008-03-26 23:34:47 +0100191
192/* no SRAM available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#undef CONFIG_SYS_SRAM_BASE
194#undef CONFIG_SYS_SRAM_SIZE
Daniel Hellstrom69403832008-03-26 23:34:47 +0100195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
197#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
198#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
Daniel Hellstrom69403832008-03-26 23:34:47 +0100199
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200200#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
Daniel Hellstrom69403832008-03-26 23:34:47 +0100201
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200202#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
Daniel Hellstrom69403832008-03-26 23:34:47 +0100204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
206#define CONFIG_SYS_STACK_SIZE (0x10000-32)
Daniel Hellstrom69403832008-03-26 23:34:47 +0100207
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200208#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
210# define CONFIG_SYS_RAMBOOT 1
Daniel Hellstrom69403832008-03-26 23:34:47 +0100211#endif
212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
214#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
215#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
218#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
Daniel Hellstrom69403832008-03-26 23:34:47 +0100219
220/* relocated monitor area */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
222#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
Daniel Hellstrom69403832008-03-26 23:34:47 +0100223
224/* make un relocated address from relocated address */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200225#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
Daniel Hellstrom69403832008-03-26 23:34:47 +0100226
227/*
228 * Ethernet configuration uses on board SMC91C111, however if a mezzanine
229 * with a PHY is attached the GRETH can be used on this board.
230 * Define USE_GRETH in order to use the mezzanine provided PHY with the
231 * onchip GRETH network MAC, note that this is not supported by the
232 * template design.
233 */
234#ifndef USE_GRETH
235
236/* USE SMC91C111 MAC */
Ben Warren7194ab82009-10-04 22:37:03 -0700237#define CONFIG_SMC91111 1
Daniel Hellstrom69403832008-03-26 23:34:47 +0100238#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
239#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
240#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
241/*#define CONFIG_SHOW_ACTIVITY*/
242#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
243
244#else
245
246/* USE GRETH Ethernet Driver */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100247#define CONFIG_GRETH 1
Masahiro Yamada1e1f3532015-05-26 10:58:31 +0900248#endif
Daniel Hellstrom69403832008-03-26 23:34:47 +0100249
Daniel Hellstrom69403832008-03-26 23:34:47 +0100250#define CONFIG_PHY_ADDR 0x00
251
252/*
253 * Miscellaneous configurable options
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_LONGHELP /* undef to save memory */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100256#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100258#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100260#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
262#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
263#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
266#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Daniel Hellstrom69403832008-03-26 23:34:47 +0100269
Daniel Hellstrom69403832008-03-26 23:34:47 +0100270/*-----------------------------------------------------------------------
271 * USB stuff
272 *-----------------------------------------------------------------------
273 */
274#define CONFIG_USB_CLOCK 0x0001BBBB
275#define CONFIG_USB_CONFIG 0x00005000
276
277/***** Gaisler GRLIB IP-Cores Config ********/
278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_GRLIB_SDRAM 0
Daniel Hellstrom69403832008-03-26 23:34:47 +0100280
Daniel Hellstromcff009e2010-01-25 09:56:08 +0100281/* No SDRAM Configuration */
282#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
283
Daniel Hellstrom69403832008-03-26 23:34:47 +0100284/* See, GRLIB Docs (grip.pdf) on how to set up
285 * These the memory controller registers.
286 */
Daniel Hellstromcff009e2010-01-25 09:56:08 +0100287#define CONFIG_SYS_GRLIB_ESA_MCTRL1
288#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
289#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
290#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
Daniel Hellstrom69403832008-03-26 23:34:47 +0100291
Daniel Hellstromcff009e2010-01-25 09:56:08 +0100292/* GRLIB FT-MCTRL configuration */
293#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
294#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
295#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
296#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
Daniel Hellstrom69403832008-03-26 23:34:47 +0100297
Daniel Hellstromcff009e2010-01-25 09:56:08 +0100298/* DDR controller */
299#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
300#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
Daniel Hellstrom69403832008-03-26 23:34:47 +0100301
Daniel Hellstromcff009e2010-01-25 09:56:08 +0100302/* no DDR2 Controller */
303#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
Daniel Hellstrom69403832008-03-26 23:34:47 +0100304
Daniel Hellstrom69403832008-03-26 23:34:47 +0100305/* default kernel command line */
306#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
307
308#endif /* __CONFIG_H */