Roshan Pius | 6d4cf27 | 2021-08-11 18:18:46 -0700 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * Copyright (C) 1999-2012 Broadcom Corporation |
| 4 | * Copyright 2018-2020 NXP |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 7 | * you may not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at: |
| 9 | * |
| 10 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | * |
| 18 | ******************************************************************************/ |
| 19 | |
| 20 | #ifndef UWB_TARGET_H |
| 21 | #define UWB_TARGET_H |
| 22 | |
| 23 | #include "data_types.h" |
| 24 | |
| 25 | #ifndef USERIAL_DEBUG |
| 26 | #define USERIAL_DEBUG false |
| 27 | #endif |
| 28 | |
| 29 | /* Include common GKI definitions used by this platform */ |
| 30 | #include "uwb_gki_target.h" |
| 31 | |
| 32 | /* UCI Command, Notification or Data*/ |
| 33 | #define BT_EVT_TO_UWB_UCI 0x4000 |
| 34 | /* messages between UWB and UCI task */ |
| 35 | #define BT_EVT_TO_UWB_MSGS 0x4300 |
| 36 | |
| 37 | /* start timer */ |
| 38 | #define BT_EVT_TO_START_TIMER 0x3c00 |
| 39 | |
| 40 | /* start quick timer */ |
| 41 | #define BT_EVT_TO_START_QUICK_TIMER 0x3e00 |
| 42 | |
| 43 | /****************************************************************************** |
| 44 | ** |
| 45 | ** GKI Mail Box and Timer |
| 46 | ** |
| 47 | ******************************************************************************/ |
| 48 | |
| 49 | /* Mailbox event mask for UWB stack */ |
| 50 | #ifndef UWB_MBOX_EVT_MASK |
| 51 | #define UWB_MBOX_EVT_MASK (TASK_MBOX_0_EVT_MASK) |
| 52 | #endif |
| 53 | |
| 54 | /* Mailbox ID for UWB stack */ |
| 55 | #ifndef UWB_MBOX_ID |
| 56 | #define UWB_MBOX_ID (TASK_MBOX_0) |
| 57 | #endif |
| 58 | |
| 59 | /* Mailbox event mask for UWA */ |
| 60 | #ifndef UWA_MBOX_EVT_MASK |
| 61 | #define UWA_MBOX_EVT_MASK (TASK_MBOX_2_EVT_MASK) |
| 62 | #endif |
| 63 | |
| 64 | /* Mailbox ID for UWA */ |
| 65 | #ifndef UWA_MBOX_ID |
| 66 | #define UWA_MBOX_ID (TASK_MBOX_2) |
| 67 | #endif |
| 68 | |
| 69 | /* GKI timer id used for protocol timer in UWB stack */ |
| 70 | #ifndef UWB_TIMER_ID |
| 71 | #define UWB_TIMER_ID (TIMER_0) |
| 72 | #endif |
| 73 | |
| 74 | /* GKI timer event mask used for protocol timer in UWB stack */ |
| 75 | #ifndef UWB_TIMER_EVT_MASK |
| 76 | #define UWB_TIMER_EVT_MASK (TIMER_0_EVT_MASK) |
| 77 | #endif |
| 78 | |
| 79 | /* GKI timer id used for quick timer in UWB stack */ |
| 80 | #ifndef UWB_QUICK_TIMER_ID |
| 81 | #define UWB_QUICK_TIMER_ID (TIMER_1) |
| 82 | #endif |
| 83 | |
| 84 | /* GKI timer event mask used for quick timer in UWB stack */ |
| 85 | #ifndef UWB_QUICK_TIMER_EVT_MASK |
| 86 | #define UWB_QUICK_TIMER_EVT_MASK (TIMER_1_EVT_MASK) |
| 87 | #endif |
| 88 | |
| 89 | /* GKI timer id used for protocol timer in UWA */ |
| 90 | #ifndef UWA_TIMER_ID |
| 91 | #define UWA_TIMER_ID (TIMER_2) |
| 92 | #endif |
| 93 | |
| 94 | /* GKI timer event mask used for protocol timer in UWA */ |
| 95 | #ifndef UWA_TIMER_EVT_MASK |
| 96 | #define UWA_TIMER_EVT_MASK (TIMER_2_EVT_MASK) |
| 97 | #endif |
| 98 | |
| 99 | /* Quick Timer */ |
| 100 | #ifndef QUICK_TIMER_TICKS_PER_SEC |
| 101 | #define QUICK_TIMER_TICKS_PER_SEC 100 /* 10ms timer */ |
| 102 | #endif |
| 103 | |
| 104 | /****************************************************************************** |
| 105 | ** |
| 106 | ** GKI Buffer Pools |
| 107 | ** |
| 108 | ******************************************************************************/ |
| 109 | |
| 110 | /* UCI command/notification/data */ |
| 111 | #ifndef UWB_UCI_POOL_ID |
| 112 | #define UWB_UCI_POOL_ID GKI_POOL_ID_2 |
| 113 | #endif |
| 114 | |
| 115 | /****************************************************************************** |
| 116 | ** |
| 117 | ** UCI Transport definitions |
| 118 | ** |
| 119 | ******************************************************************************/ |
| 120 | /* offset of the first UCI packet in buffer for outgoing */ |
| 121 | #ifndef UCI_MSG_OFFSET_SIZE |
| 122 | #define UCI_MSG_OFFSET_SIZE 1 |
| 123 | #endif |
| 124 | |
| 125 | /****************************************************************************** |
| 126 | ** |
| 127 | ** UWB |
| 128 | ** |
| 129 | ******************************************************************************/ |
| 130 | |
| 131 | /* Timeout for receiving response to UCI command in case of retry */ |
| 132 | #ifndef UWB_CMD_RETRY_TIMEOUT |
| 133 | #define UWB_CMD_RETRY_TIMEOUT 75 // 75ms |
| 134 | #endif |
| 135 | |
| 136 | /* Timeout for receiving response to UCI command */ |
| 137 | #ifndef UWB_CMD_CMPL_TIMEOUT |
| 138 | #define UWB_CMD_CMPL_TIMEOUT 100 // 100ms |
| 139 | #endif |
| 140 | |
| 141 | /* Maximum number of UCI commands that the UWBC accepts without needing to wait |
| 142 | * for response */ |
| 143 | #ifndef UCI_MAX_CMD_WINDOW |
| 144 | #define UCI_MAX_CMD_WINDOW 1 |
| 145 | #endif |
| 146 | |
| 147 | #ifndef UCI_CMD_MAX_RETRY_COUNT |
| 148 | #define UCI_CMD_MAX_RETRY_COUNT 10 |
| 149 | #endif |
| 150 | |
| 151 | /***************************************************************************** |
| 152 | ** Define HAL_WRITE depending on whether HAL is using shared GKI resources |
| 153 | ** as the UWB stack. |
| 154 | *****************************************************************************/ |
| 155 | #ifndef HAL_WRITE |
| 156 | #define HAL_WRITE(p) \ |
| 157 | { \ |
| 158 | uwb_cb.p_hal->write(p->len, (uint8_t*)(p + 1) + p->offset); \ |
Roshan Pius | 81ec334 | 2021-10-19 10:00:01 -0700 | [diff] [blame] | 159 | phUwb_GKI_freebuf(p); \ |
Roshan Pius | 6d4cf27 | 2021-08-11 18:18:46 -0700 | [diff] [blame] | 160 | } |
| 161 | #define HAL_RE_WRITE(p) \ |
| 162 | { uwb_cb.p_hal->write(p->len, (uint8_t*)(p + 1) + p->offset); } |
| 163 | |
| 164 | #define HAL_UCI_CMD_WRITE(len, buf) \ |
| 165 | { uwb_cb.p_hal->write(len, (uint8_t*)buf); } |
| 166 | /* Mem allocation with 8 byte alignment */ |
| 167 | #define HAL_MALLOC(x) malloc(((x - 1) | 7) + 1) |
| 168 | #endif /* HAL_WRITE */ |
| 169 | |
| 170 | #endif /* UWB_TARGET_H */ |