mips64: modify load_indexed_instructions test
A little style improvement for load_indexed_instructions test including
addition of new instruction to be tested - lhx (supported as of VEX r3152).
Related issue - BZ #345987.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15340 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/none/tests/mips64/load_indexed_instructions.c b/none/tests/mips64/load_indexed_instructions.c
index a36d222..c521798 100644
--- a/none/tests/mips64/load_indexed_instructions.c
+++ b/none/tests/mips64/load_indexed_instructions.c
@@ -67,16 +67,16 @@
};
/*
-Test 1 macro is used for ldx instructions. After executing each instructions
-the macro performs following operations:
+TEST1 macro is used for load-indexed instructions. For each instruction,
+the macro will perform the following operations:
-1: Move arguments to registers.
-2: Execute instruction.
-3: Move result from register. */
+1: Move input arguments into registers.
+2: Execute the instruction.
+3: Move the result from a register to the out variable. */
#define TEST1(instruction, offset, mem) \
{ \
- unsigned long out = 0; \
+ unsigned long out = 0; \
__asm__ volatile( \
"move $t0, %1" "\n\t" \
"move $t1, %2" "\n\t" \
@@ -84,7 +84,7 @@
"move %0, $t2" "\n\t" \
: "=&r" (out) \
: "r" (mem) , "r" (offset) \
- : "t0", "t1", "t2", "cc", "memory" \
+ : "t0", "t1", "t2", "memory" \
); \
printf("%s :: offset: 0x%x, out: 0x%lx\n", \
instruction, offset, out); \
@@ -100,6 +100,8 @@
TEST1("lbux", i, reg_val);
for(i = 8; i <= 255; i += 8)
TEST1("lwx", i, reg_val);
+ for(i = 8; i <= 255; i += 8)
+ TEST1("lhx", i, reg_val);
#endif
return 0;
}
diff --git a/none/tests/mips64/load_indexed_instructions.stdout.exp-BE b/none/tests/mips64/load_indexed_instructions.stdout.exp-BE
index 5f8f272..7e8c534 100644
--- a/none/tests/mips64/load_indexed_instructions.stdout.exp-BE
+++ b/none/tests/mips64/load_indexed_instructions.stdout.exp-BE
@@ -91,3 +91,34 @@
lwx :: offset: 0xe8, out: 0xfffffffffbb8bb46
lwx :: offset: 0xf0, out: 0xffffffffe13ef6f4
lwx :: offset: 0xf8, out: 0xffffffffe8bccd9a
+lhx :: offset: 0x8, out: 0x982
+lhx :: offset: 0x10, out: 0x1304
+lhx :: offset: 0x18, out: 0x1a86
+lhx :: offset: 0x20, out: 0x2608
+lhx :: offset: 0x28, out: 0x2f8a
+lhx :: offset: 0x30, out: 0x350c
+lhx :: offset: 0x38, out: 0x3c8e
+lhx :: offset: 0x40, out: 0x4c11
+lhx :: offset: 0x48, out: 0x4593
+lhx :: offset: 0x50, out: 0x5f15
+lhx :: offset: 0x58, out: 0x5697
+lhx :: offset: 0x60, out: 0x6a19
+lhx :: offset: 0x68, out: 0x639b
+lhx :: offset: 0x70, out: 0x791d
+lhx :: offset: 0x78, out: 0x709f
+lhx :: offset: 0x80, out: 0xffffffffffff9823
+lhx :: offset: 0x88, out: 0xffffffffffff91a1
+lhx :: offset: 0x90, out: 0xffffffffffff8b27
+lhx :: offset: 0x98, out: 0xffffffffffff82a5
+lhx :: offset: 0xa0, out: 0xffffffffffffbe2b
+lhx :: offset: 0xa8, out: 0xffffffffffffb7a9
+lhx :: offset: 0xb0, out: 0xffffffffffffad2f
+lhx :: offset: 0xb8, out: 0xffffffffffffa4ad
+lhx :: offset: 0xc0, out: 0xffffffffffffd432
+lhx :: offset: 0xc8, out: 0xffffffffffffddb0
+lhx :: offset: 0xd0, out: 0xffffffffffffc736
+lhx :: offset: 0xd8, out: 0xffffffffffffceb4
+lhx :: offset: 0xe0, out: 0xfffffffffffff23a
+lhx :: offset: 0xe8, out: 0xfffffffffffffbb8
+lhx :: offset: 0xf0, out: 0xffffffffffffe13e
+lhx :: offset: 0xf8, out: 0xffffffffffffe8bc
diff --git a/none/tests/mips64/load_indexed_instructions.stdout.exp-LE b/none/tests/mips64/load_indexed_instructions.stdout.exp-LE
index 072a6f5..af44580 100644
--- a/none/tests/mips64/load_indexed_instructions.stdout.exp-LE
+++ b/none/tests/mips64/load_indexed_instructions.stdout.exp-LE
@@ -91,3 +91,34 @@
lwx :: offset: 0xe8, out: 0xfffffffffbb8bb46
lwx :: offset: 0xf0, out: 0xffffffffe13ef6f4
lwx :: offset: 0xf8, out: 0xffffffffe8bccd9a
+lhx :: offset: 0x8, out: 0x3b6e
+lhx :: offset: 0x10, out: 0x76dc
+lhx :: offset: 0x18, out: 0x4db2
+lhx :: offset: 0x20, out: 0xffffffffffffedb8
+lhx :: offset: 0x28, out: 0xffffffffffffd6d6
+lhx :: offset: 0x30, out: 0xffffffffffff9b64
+lhx :: offset: 0x38, out: 0xffffffffffffa00a
+lhx :: offset: 0x40, out: 0xffffffffffffdb70
+lhx :: offset: 0x48, out: 0xffffffffffffe01e
+lhx :: offset: 0x50, out: 0xffffffffffffadac
+lhx :: offset: 0x58, out: 0xffffffffffff96c2
+lhx :: offset: 0x60, out: 0x36c8
+lhx :: offset: 0x68, out: 0xda6
+lhx :: offset: 0x70, out: 0x4014
+lhx :: offset: 0x78, out: 0x7b7a
+lhx :: offset: 0x80, out: 0xffffffffffffb6e0
+lhx :: offset: 0x88, out: 0xffffffffffff8d8e
+lhx :: offset: 0x90, out: 0xffffffffffffc03c
+lhx :: offset: 0x98, out: 0xfffffffffffffb52
+lhx :: offset: 0xa0, out: 0x5b58
+lhx :: offset: 0xa8, out: 0x6036
+lhx :: offset: 0xb0, out: 0x2d84
+lhx :: offset: 0xb8, out: 0x16ea
+lhx :: offset: 0xc0, out: 0x6d90
+lhx :: offset: 0xc8, out: 0x56fe
+lhx :: offset: 0xd0, out: 0x1b4c
+lhx :: offset: 0xd8, out: 0x2022
+lhx :: offset: 0xe0, out: 0xffffffffffff8028
+lhx :: offset: 0xe8, out: 0xffffffffffffbb46
+lhx :: offset: 0xf0, out: 0xfffffffffffff6f4
+lhx :: offset: 0xf8, out: 0xffffffffffffcd9a